Searched refs:SUNXI_DRAM_PHY0_BASE (Results 1 – 10 of 10) sorted by relevance
| /u-boot/arch/arm/mach-sunxi/ |
| A D | dram_sun50i_h616.c | 277 writel(4, SUNXI_DRAM_PHY0_BASE + 0xc); in mctl_phy_write_leveling()
480 writel(0, SUNXI_DRAM_PHY0_BASE + 0x134); in mctl_phy_write_training()
481 writel(0, SUNXI_DRAM_PHY0_BASE + 0x138); in mctl_phy_write_training()
482 writel(0, SUNXI_DRAM_PHY0_BASE + 0x19c); in mctl_phy_write_training()
483 writel(0, SUNXI_DRAM_PHY0_BASE + 0x1a0); in mctl_phy_write_training()
694 writel(0, SUNXI_DRAM_PHY0_BASE + 0x18); in mctl_phy_init()
695 writel(0, SUNXI_DRAM_PHY0_BASE + 0x360); in mctl_phy_init()
696 writel(0, SUNXI_DRAM_PHY0_BASE + 0x36c); in mctl_phy_init()
697 writel(0, SUNXI_DRAM_PHY0_BASE + 0x378); in mctl_phy_init()
699 writel(9, SUNXI_DRAM_PHY0_BASE + 0x1c); in mctl_phy_init()
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| A D | dram_sun50i_h6.c | 61 (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE; in mctl_phy_pir_init()
292 (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE; in mctl_com_init()
358 (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE; in mctl_bit_delay_set()
421 (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE; in mctl_channel_init()
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| A D | dram_sun6i.c | 58 mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE; in mctl_dll_init()
113 mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE; in mctl_channel_init()
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| A D | dram_sun8i_a23.c | 101 (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE; in mctl_init()
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| A D | dram_sun9i.c | 455 mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE; in mctl_channel_init()
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| /u-boot/arch/arm/include/asm/arch-sunxi/ |
| A D | cpu_sun50i_h6.h | 34 #define SUNXI_DRAM_PHY0_BASE 0x04005000 macro
43 #define SUNXI_DRAM_PHY0_BASE 0x04800000 macro
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| A D | cpu_sun9i.h | 47 #define SUNXI_DRAM_PHY0_BASE (REGS_AHB0_BASE + 0x65000) macro
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| A D | cpu_sun4i.h | 158 #define SUNXI_DRAM_PHY0_BASE 0x01c65000 macro
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| /u-boot/arch/arm/mach-sunxi/dram_timings/ |
| A D | h6_lpddr3.c | 25 (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE; in mctl_set_timing_params()
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| A D | h6_ddr3_1333.c | 46 (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE; in mctl_set_timing_params()
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