| /u-boot/drivers/clk/aspeed/ |
| A D | clk_ast2500.c | 183 ulong input_rate; member
192 static bool ast2500_get_clock_config_default(ulong input_rate, in ast2500_get_clock_config_default() argument
201 if (default_cfg->input_rate == input_rate && in ast2500_get_clock_config_default()
221 static ulong ast2500_calc_clock_config(ulong input_rate, ulong requested_rate, in ast2500_calc_clock_config() argument
228 const ulong input_rate_khz = input_rate / 1000; in ast2500_calc_clock_config()
238 if (ast2500_get_clock_config_default(input_rate, requested_rate, cfg)) in ast2500_calc_clock_config()
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| /u-boot/arch/arm/include/asm/arch-rockchip/ |
| A D | clock.h | 134 static inline u32 clk_get_divisor(ulong input_rate, uint output_rate) in clk_get_divisor() argument
138 clk_div = input_rate / output_rate; in clk_get_divisor()
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| /u-boot/drivers/spi/ |
| A D | rk_spi.c | 61 uint input_rate; member
96 uint clk_div = DIV_ROUND_UP(priv->input_rate, speed); in rkspi_set_clk()
108 __func__, speed, priv->input_rate / clk_div); in rkspi_set_clk()
281 priv->input_rate = ret; in rockchip_spi_probe()
282 debug("%s: rate = %u\n", __func__, priv->input_rate); in rockchip_spi_probe()
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| /u-boot/drivers/clk/rockchip/ |
| A D | clk_rk3036.c | 31 #define RATE_TO_DIV(input_rate, output_rate) \ argument
32 ((input_rate) / (output_rate) - 1);
34 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
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| A D | clk_rk3328.c | 33 #define RATE_TO_DIV(input_rate, output_rate) \ argument
34 ((input_rate) / (output_rate) - 1);
35 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
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| A D | clk_rk322x.c | 32 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
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| A D | clk_rk3128.c | 31 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
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| A D | clk_rk3188.c | 76 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
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| A D | clk_rk3368.c | 46 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
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| A D | clk_rk3399.c | 48 #define RATE_TO_DIV(input_rate, output_rate) \ argument
49 ((input_rate) / (output_rate) - 1)
50 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
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| A D | clk_rv1108.c | 35 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
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| A D | clk_rk3288.c | 138 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
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| A D | clk_rk3308.c | 33 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
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| A D | clk_px30.c | 55 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
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| /u-boot/arch/arm/mach-exynos/ |
| A D | clock.c | 1409 unsigned int fine_scalar_bits, unsigned int input_rate, in clock_calc_best_scalar() argument
1418 debug("Input Rate is %u, Target is %u, Cap is %u\n", input_rate, in clock_calc_best_scalar()
1426 if (input_rate == 0 || target_rate == 0) in clock_calc_best_scalar()
1429 if (target_rate >= input_rate) in clock_calc_best_scalar()
1434 max(min(input_rate / i / target_rate, cap), 1U); in clock_calc_best_scalar()
1435 const unsigned int effective_rate = input_rate / i / in clock_calc_best_scalar()
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