1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * AMD Memory Encryption Support
4 *
5 * Copyright (C) 2016 Advanced Micro Devices, Inc.
6 *
7 * Author: Tom Lendacky <thomas.lendacky@amd.com>
8 */
9
10 #define DISABLE_BRANCH_PROFILING
11
12 /*
13 * Since we're dealing with identity mappings, physical and virtual
14 * addresses are the same, so override these defines which are ultimately
15 * used by the headers in misc.h.
16 */
17 #define __pa(x) ((unsigned long)(x))
18 #define __va(x) ((void *)((unsigned long)(x)))
19
20 /*
21 * Special hack: we have to be careful, because no indirections are
22 * allowed here, and paravirt_ops is a kind of one. As it will only run in
23 * baremetal anyway, we just keep it from happening. (This list needs to
24 * be extended when new paravirt and debugging variants are added.)
25 */
26 #undef CONFIG_PARAVIRT
27 #undef CONFIG_PARAVIRT_XXL
28 #undef CONFIG_PARAVIRT_SPINLOCKS
29
30 /*
31 * This code runs before CPU feature bits are set. By default, the
32 * pgtable_l5_enabled() function uses bit X86_FEATURE_LA57 to determine if
33 * 5-level paging is active, so that won't work here. USE_EARLY_PGTABLE_L5
34 * is provided to handle this situation and, instead, use a variable that
35 * has been set by the early boot code.
36 */
37 #define USE_EARLY_PGTABLE_L5
38
39 #include <linux/kernel.h>
40 #include <linux/mm.h>
41 #include <linux/mem_encrypt.h>
42 #include <linux/cc_platform.h>
43
44 #include <asm/setup.h>
45 #include <asm/sections.h>
46 #include <asm/cmdline.h>
47
48 #include "mm_internal.h"
49
50 #define PGD_FLAGS _KERNPG_TABLE_NOENC
51 #define P4D_FLAGS _KERNPG_TABLE_NOENC
52 #define PUD_FLAGS _KERNPG_TABLE_NOENC
53 #define PMD_FLAGS _KERNPG_TABLE_NOENC
54
55 #define PMD_FLAGS_LARGE (__PAGE_KERNEL_LARGE_EXEC & ~_PAGE_GLOBAL)
56
57 #define PMD_FLAGS_DEC PMD_FLAGS_LARGE
58 #define PMD_FLAGS_DEC_WP ((PMD_FLAGS_DEC & ~_PAGE_LARGE_CACHE_MASK) | \
59 (_PAGE_PAT_LARGE | _PAGE_PWT))
60
61 #define PMD_FLAGS_ENC (PMD_FLAGS_LARGE | _PAGE_ENC)
62
63 #define PTE_FLAGS (__PAGE_KERNEL_EXEC & ~_PAGE_GLOBAL)
64
65 #define PTE_FLAGS_DEC PTE_FLAGS
66 #define PTE_FLAGS_DEC_WP ((PTE_FLAGS_DEC & ~_PAGE_CACHE_MASK) | \
67 (_PAGE_PAT | _PAGE_PWT))
68
69 #define PTE_FLAGS_ENC (PTE_FLAGS | _PAGE_ENC)
70
71 struct sme_populate_pgd_data {
72 void *pgtable_area;
73 pgd_t *pgd;
74
75 pmdval_t pmd_flags;
76 pteval_t pte_flags;
77 unsigned long paddr;
78
79 unsigned long vaddr;
80 unsigned long vaddr_end;
81 };
82
83 /*
84 * This work area lives in the .init.scratch section, which lives outside of
85 * the kernel proper. It is sized to hold the intermediate copy buffer and
86 * more than enough pagetable pages.
87 *
88 * By using this section, the kernel can be encrypted in place and it
89 * avoids any possibility of boot parameters or initramfs images being
90 * placed such that the in-place encryption logic overwrites them. This
91 * section is 2MB aligned to allow for simple pagetable setup using only
92 * PMD entries (see vmlinux.lds.S).
93 */
94 static char sme_workarea[2 * PMD_PAGE_SIZE] __section(".init.scratch");
95
96 static char sme_cmdline_arg[] __initdata = "mem_encrypt";
97 static char sme_cmdline_on[] __initdata = "on";
98 static char sme_cmdline_off[] __initdata = "off";
99
sme_clear_pgd(struct sme_populate_pgd_data * ppd)100 static void __init sme_clear_pgd(struct sme_populate_pgd_data *ppd)
101 {
102 unsigned long pgd_start, pgd_end, pgd_size;
103 pgd_t *pgd_p;
104
105 pgd_start = ppd->vaddr & PGDIR_MASK;
106 pgd_end = ppd->vaddr_end & PGDIR_MASK;
107
108 pgd_size = (((pgd_end - pgd_start) / PGDIR_SIZE) + 1) * sizeof(pgd_t);
109
110 pgd_p = ppd->pgd + pgd_index(ppd->vaddr);
111
112 memset(pgd_p, 0, pgd_size);
113 }
114
sme_prepare_pgd(struct sme_populate_pgd_data * ppd)115 static pud_t __init *sme_prepare_pgd(struct sme_populate_pgd_data *ppd)
116 {
117 pgd_t *pgd;
118 p4d_t *p4d;
119 pud_t *pud;
120 pmd_t *pmd;
121
122 pgd = ppd->pgd + pgd_index(ppd->vaddr);
123 if (pgd_none(*pgd)) {
124 p4d = ppd->pgtable_area;
125 memset(p4d, 0, sizeof(*p4d) * PTRS_PER_P4D);
126 ppd->pgtable_area += sizeof(*p4d) * PTRS_PER_P4D;
127 set_pgd(pgd, __pgd(PGD_FLAGS | __pa(p4d)));
128 }
129
130 p4d = p4d_offset(pgd, ppd->vaddr);
131 if (p4d_none(*p4d)) {
132 pud = ppd->pgtable_area;
133 memset(pud, 0, sizeof(*pud) * PTRS_PER_PUD);
134 ppd->pgtable_area += sizeof(*pud) * PTRS_PER_PUD;
135 set_p4d(p4d, __p4d(P4D_FLAGS | __pa(pud)));
136 }
137
138 pud = pud_offset(p4d, ppd->vaddr);
139 if (pud_none(*pud)) {
140 pmd = ppd->pgtable_area;
141 memset(pmd, 0, sizeof(*pmd) * PTRS_PER_PMD);
142 ppd->pgtable_area += sizeof(*pmd) * PTRS_PER_PMD;
143 set_pud(pud, __pud(PUD_FLAGS | __pa(pmd)));
144 }
145
146 if (pud_large(*pud))
147 return NULL;
148
149 return pud;
150 }
151
sme_populate_pgd_large(struct sme_populate_pgd_data * ppd)152 static void __init sme_populate_pgd_large(struct sme_populate_pgd_data *ppd)
153 {
154 pud_t *pud;
155 pmd_t *pmd;
156
157 pud = sme_prepare_pgd(ppd);
158 if (!pud)
159 return;
160
161 pmd = pmd_offset(pud, ppd->vaddr);
162 if (pmd_large(*pmd))
163 return;
164
165 set_pmd(pmd, __pmd(ppd->paddr | ppd->pmd_flags));
166 }
167
sme_populate_pgd(struct sme_populate_pgd_data * ppd)168 static void __init sme_populate_pgd(struct sme_populate_pgd_data *ppd)
169 {
170 pud_t *pud;
171 pmd_t *pmd;
172 pte_t *pte;
173
174 pud = sme_prepare_pgd(ppd);
175 if (!pud)
176 return;
177
178 pmd = pmd_offset(pud, ppd->vaddr);
179 if (pmd_none(*pmd)) {
180 pte = ppd->pgtable_area;
181 memset(pte, 0, sizeof(*pte) * PTRS_PER_PTE);
182 ppd->pgtable_area += sizeof(*pte) * PTRS_PER_PTE;
183 set_pmd(pmd, __pmd(PMD_FLAGS | __pa(pte)));
184 }
185
186 if (pmd_large(*pmd))
187 return;
188
189 pte = pte_offset_map(pmd, ppd->vaddr);
190 if (pte_none(*pte))
191 set_pte(pte, __pte(ppd->paddr | ppd->pte_flags));
192 }
193
__sme_map_range_pmd(struct sme_populate_pgd_data * ppd)194 static void __init __sme_map_range_pmd(struct sme_populate_pgd_data *ppd)
195 {
196 while (ppd->vaddr < ppd->vaddr_end) {
197 sme_populate_pgd_large(ppd);
198
199 ppd->vaddr += PMD_PAGE_SIZE;
200 ppd->paddr += PMD_PAGE_SIZE;
201 }
202 }
203
__sme_map_range_pte(struct sme_populate_pgd_data * ppd)204 static void __init __sme_map_range_pte(struct sme_populate_pgd_data *ppd)
205 {
206 while (ppd->vaddr < ppd->vaddr_end) {
207 sme_populate_pgd(ppd);
208
209 ppd->vaddr += PAGE_SIZE;
210 ppd->paddr += PAGE_SIZE;
211 }
212 }
213
__sme_map_range(struct sme_populate_pgd_data * ppd,pmdval_t pmd_flags,pteval_t pte_flags)214 static void __init __sme_map_range(struct sme_populate_pgd_data *ppd,
215 pmdval_t pmd_flags, pteval_t pte_flags)
216 {
217 unsigned long vaddr_end;
218
219 ppd->pmd_flags = pmd_flags;
220 ppd->pte_flags = pte_flags;
221
222 /* Save original end value since we modify the struct value */
223 vaddr_end = ppd->vaddr_end;
224
225 /* If start is not 2MB aligned, create PTE entries */
226 ppd->vaddr_end = ALIGN(ppd->vaddr, PMD_PAGE_SIZE);
227 __sme_map_range_pte(ppd);
228
229 /* Create PMD entries */
230 ppd->vaddr_end = vaddr_end & PMD_PAGE_MASK;
231 __sme_map_range_pmd(ppd);
232
233 /* If end is not 2MB aligned, create PTE entries */
234 ppd->vaddr_end = vaddr_end;
235 __sme_map_range_pte(ppd);
236 }
237
sme_map_range_encrypted(struct sme_populate_pgd_data * ppd)238 static void __init sme_map_range_encrypted(struct sme_populate_pgd_data *ppd)
239 {
240 __sme_map_range(ppd, PMD_FLAGS_ENC, PTE_FLAGS_ENC);
241 }
242
sme_map_range_decrypted(struct sme_populate_pgd_data * ppd)243 static void __init sme_map_range_decrypted(struct sme_populate_pgd_data *ppd)
244 {
245 __sme_map_range(ppd, PMD_FLAGS_DEC, PTE_FLAGS_DEC);
246 }
247
sme_map_range_decrypted_wp(struct sme_populate_pgd_data * ppd)248 static void __init sme_map_range_decrypted_wp(struct sme_populate_pgd_data *ppd)
249 {
250 __sme_map_range(ppd, PMD_FLAGS_DEC_WP, PTE_FLAGS_DEC_WP);
251 }
252
sme_pgtable_calc(unsigned long len)253 static unsigned long __init sme_pgtable_calc(unsigned long len)
254 {
255 unsigned long entries = 0, tables = 0;
256
257 /*
258 * Perform a relatively simplistic calculation of the pagetable
259 * entries that are needed. Those mappings will be covered mostly
260 * by 2MB PMD entries so we can conservatively calculate the required
261 * number of P4D, PUD and PMD structures needed to perform the
262 * mappings. For mappings that are not 2MB aligned, PTE mappings
263 * would be needed for the start and end portion of the address range
264 * that fall outside of the 2MB alignment. This results in, at most,
265 * two extra pages to hold PTE entries for each range that is mapped.
266 * Incrementing the count for each covers the case where the addresses
267 * cross entries.
268 */
269
270 /* PGDIR_SIZE is equal to P4D_SIZE on 4-level machine. */
271 if (PTRS_PER_P4D > 1)
272 entries += (DIV_ROUND_UP(len, PGDIR_SIZE) + 1) * sizeof(p4d_t) * PTRS_PER_P4D;
273 entries += (DIV_ROUND_UP(len, P4D_SIZE) + 1) * sizeof(pud_t) * PTRS_PER_PUD;
274 entries += (DIV_ROUND_UP(len, PUD_SIZE) + 1) * sizeof(pmd_t) * PTRS_PER_PMD;
275 entries += 2 * sizeof(pte_t) * PTRS_PER_PTE;
276
277 /*
278 * Now calculate the added pagetable structures needed to populate
279 * the new pagetables.
280 */
281
282 if (PTRS_PER_P4D > 1)
283 tables += DIV_ROUND_UP(entries, PGDIR_SIZE) * sizeof(p4d_t) * PTRS_PER_P4D;
284 tables += DIV_ROUND_UP(entries, P4D_SIZE) * sizeof(pud_t) * PTRS_PER_PUD;
285 tables += DIV_ROUND_UP(entries, PUD_SIZE) * sizeof(pmd_t) * PTRS_PER_PMD;
286
287 return entries + tables;
288 }
289
sme_encrypt_kernel(struct boot_params * bp)290 void __init sme_encrypt_kernel(struct boot_params *bp)
291 {
292 unsigned long workarea_start, workarea_end, workarea_len;
293 unsigned long execute_start, execute_end, execute_len;
294 unsigned long kernel_start, kernel_end, kernel_len;
295 unsigned long initrd_start, initrd_end, initrd_len;
296 struct sme_populate_pgd_data ppd;
297 unsigned long pgtable_area_len;
298 unsigned long decrypted_base;
299
300 /*
301 * This is early code, use an open coded check for SME instead of
302 * using cc_platform_has(). This eliminates worries about removing
303 * instrumentation or checking boot_cpu_data in the cc_platform_has()
304 * function.
305 */
306 if (!sme_get_me_mask() || sev_status & MSR_AMD64_SEV_ENABLED)
307 return;
308
309 /*
310 * Prepare for encrypting the kernel and initrd by building new
311 * pagetables with the necessary attributes needed to encrypt the
312 * kernel in place.
313 *
314 * One range of virtual addresses will map the memory occupied
315 * by the kernel and initrd as encrypted.
316 *
317 * Another range of virtual addresses will map the memory occupied
318 * by the kernel and initrd as decrypted and write-protected.
319 *
320 * The use of write-protect attribute will prevent any of the
321 * memory from being cached.
322 */
323
324 /* Physical addresses gives us the identity mapped virtual addresses */
325 kernel_start = __pa_symbol(_text);
326 kernel_end = ALIGN(__pa_symbol(_end), PMD_PAGE_SIZE);
327 kernel_len = kernel_end - kernel_start;
328
329 initrd_start = 0;
330 initrd_end = 0;
331 initrd_len = 0;
332 #ifdef CONFIG_BLK_DEV_INITRD
333 initrd_len = (unsigned long)bp->hdr.ramdisk_size |
334 ((unsigned long)bp->ext_ramdisk_size << 32);
335 if (initrd_len) {
336 initrd_start = (unsigned long)bp->hdr.ramdisk_image |
337 ((unsigned long)bp->ext_ramdisk_image << 32);
338 initrd_end = PAGE_ALIGN(initrd_start + initrd_len);
339 initrd_len = initrd_end - initrd_start;
340 }
341 #endif
342
343 /*
344 * We're running identity mapped, so we must obtain the address to the
345 * SME encryption workarea using rip-relative addressing.
346 */
347 asm ("lea sme_workarea(%%rip), %0"
348 : "=r" (workarea_start)
349 : "p" (sme_workarea));
350
351 /*
352 * Calculate required number of workarea bytes needed:
353 * executable encryption area size:
354 * stack page (PAGE_SIZE)
355 * encryption routine page (PAGE_SIZE)
356 * intermediate copy buffer (PMD_PAGE_SIZE)
357 * pagetable structures for the encryption of the kernel
358 * pagetable structures for workarea (in case not currently mapped)
359 */
360 execute_start = workarea_start;
361 execute_end = execute_start + (PAGE_SIZE * 2) + PMD_PAGE_SIZE;
362 execute_len = execute_end - execute_start;
363
364 /*
365 * One PGD for both encrypted and decrypted mappings and a set of
366 * PUDs and PMDs for each of the encrypted and decrypted mappings.
367 */
368 pgtable_area_len = sizeof(pgd_t) * PTRS_PER_PGD;
369 pgtable_area_len += sme_pgtable_calc(execute_end - kernel_start) * 2;
370 if (initrd_len)
371 pgtable_area_len += sme_pgtable_calc(initrd_len) * 2;
372
373 /* PUDs and PMDs needed in the current pagetables for the workarea */
374 pgtable_area_len += sme_pgtable_calc(execute_len + pgtable_area_len);
375
376 /*
377 * The total workarea includes the executable encryption area and
378 * the pagetable area. The start of the workarea is already 2MB
379 * aligned, align the end of the workarea on a 2MB boundary so that
380 * we don't try to create/allocate PTE entries from the workarea
381 * before it is mapped.
382 */
383 workarea_len = execute_len + pgtable_area_len;
384 workarea_end = ALIGN(workarea_start + workarea_len, PMD_PAGE_SIZE);
385
386 /*
387 * Set the address to the start of where newly created pagetable
388 * structures (PGDs, PUDs and PMDs) will be allocated. New pagetable
389 * structures are created when the workarea is added to the current
390 * pagetables and when the new encrypted and decrypted kernel
391 * mappings are populated.
392 */
393 ppd.pgtable_area = (void *)execute_end;
394
395 /*
396 * Make sure the current pagetable structure has entries for
397 * addressing the workarea.
398 */
399 ppd.pgd = (pgd_t *)native_read_cr3_pa();
400 ppd.paddr = workarea_start;
401 ppd.vaddr = workarea_start;
402 ppd.vaddr_end = workarea_end;
403 sme_map_range_decrypted(&ppd);
404
405 /* Flush the TLB - no globals so cr3 is enough */
406 native_write_cr3(__native_read_cr3());
407
408 /*
409 * A new pagetable structure is being built to allow for the kernel
410 * and initrd to be encrypted. It starts with an empty PGD that will
411 * then be populated with new PUDs and PMDs as the encrypted and
412 * decrypted kernel mappings are created.
413 */
414 ppd.pgd = ppd.pgtable_area;
415 memset(ppd.pgd, 0, sizeof(pgd_t) * PTRS_PER_PGD);
416 ppd.pgtable_area += sizeof(pgd_t) * PTRS_PER_PGD;
417
418 /*
419 * A different PGD index/entry must be used to get different
420 * pagetable entries for the decrypted mapping. Choose the next
421 * PGD index and convert it to a virtual address to be used as
422 * the base of the mapping.
423 */
424 decrypted_base = (pgd_index(workarea_end) + 1) & (PTRS_PER_PGD - 1);
425 if (initrd_len) {
426 unsigned long check_base;
427
428 check_base = (pgd_index(initrd_end) + 1) & (PTRS_PER_PGD - 1);
429 decrypted_base = max(decrypted_base, check_base);
430 }
431 decrypted_base <<= PGDIR_SHIFT;
432
433 /* Add encrypted kernel (identity) mappings */
434 ppd.paddr = kernel_start;
435 ppd.vaddr = kernel_start;
436 ppd.vaddr_end = kernel_end;
437 sme_map_range_encrypted(&ppd);
438
439 /* Add decrypted, write-protected kernel (non-identity) mappings */
440 ppd.paddr = kernel_start;
441 ppd.vaddr = kernel_start + decrypted_base;
442 ppd.vaddr_end = kernel_end + decrypted_base;
443 sme_map_range_decrypted_wp(&ppd);
444
445 if (initrd_len) {
446 /* Add encrypted initrd (identity) mappings */
447 ppd.paddr = initrd_start;
448 ppd.vaddr = initrd_start;
449 ppd.vaddr_end = initrd_end;
450 sme_map_range_encrypted(&ppd);
451 /*
452 * Add decrypted, write-protected initrd (non-identity) mappings
453 */
454 ppd.paddr = initrd_start;
455 ppd.vaddr = initrd_start + decrypted_base;
456 ppd.vaddr_end = initrd_end + decrypted_base;
457 sme_map_range_decrypted_wp(&ppd);
458 }
459
460 /* Add decrypted workarea mappings to both kernel mappings */
461 ppd.paddr = workarea_start;
462 ppd.vaddr = workarea_start;
463 ppd.vaddr_end = workarea_end;
464 sme_map_range_decrypted(&ppd);
465
466 ppd.paddr = workarea_start;
467 ppd.vaddr = workarea_start + decrypted_base;
468 ppd.vaddr_end = workarea_end + decrypted_base;
469 sme_map_range_decrypted(&ppd);
470
471 /* Perform the encryption */
472 sme_encrypt_execute(kernel_start, kernel_start + decrypted_base,
473 kernel_len, workarea_start, (unsigned long)ppd.pgd);
474
475 if (initrd_len)
476 sme_encrypt_execute(initrd_start, initrd_start + decrypted_base,
477 initrd_len, workarea_start,
478 (unsigned long)ppd.pgd);
479
480 /*
481 * At this point we are running encrypted. Remove the mappings for
482 * the decrypted areas - all that is needed for this is to remove
483 * the PGD entry/entries.
484 */
485 ppd.vaddr = kernel_start + decrypted_base;
486 ppd.vaddr_end = kernel_end + decrypted_base;
487 sme_clear_pgd(&ppd);
488
489 if (initrd_len) {
490 ppd.vaddr = initrd_start + decrypted_base;
491 ppd.vaddr_end = initrd_end + decrypted_base;
492 sme_clear_pgd(&ppd);
493 }
494
495 ppd.vaddr = workarea_start + decrypted_base;
496 ppd.vaddr_end = workarea_end + decrypted_base;
497 sme_clear_pgd(&ppd);
498
499 /* Flush the TLB - no globals so cr3 is enough */
500 native_write_cr3(__native_read_cr3());
501 }
502
sme_enable(struct boot_params * bp)503 void __init sme_enable(struct boot_params *bp)
504 {
505 const char *cmdline_ptr, *cmdline_arg, *cmdline_on, *cmdline_off;
506 unsigned int eax, ebx, ecx, edx;
507 unsigned long feature_mask;
508 bool active_by_default;
509 unsigned long me_mask;
510 char buffer[16];
511 u64 msr;
512
513 /* Check for the SME/SEV support leaf */
514 eax = 0x80000000;
515 ecx = 0;
516 native_cpuid(&eax, &ebx, &ecx, &edx);
517 if (eax < 0x8000001f)
518 return;
519
520 #define AMD_SME_BIT BIT(0)
521 #define AMD_SEV_BIT BIT(1)
522
523 /*
524 * Check for the SME/SEV feature:
525 * CPUID Fn8000_001F[EAX]
526 * - Bit 0 - Secure Memory Encryption support
527 * - Bit 1 - Secure Encrypted Virtualization support
528 * CPUID Fn8000_001F[EBX]
529 * - Bits 5:0 - Pagetable bit position used to indicate encryption
530 */
531 eax = 0x8000001f;
532 ecx = 0;
533 native_cpuid(&eax, &ebx, &ecx, &edx);
534 /* Check whether SEV or SME is supported */
535 if (!(eax & (AMD_SEV_BIT | AMD_SME_BIT)))
536 return;
537
538 me_mask = 1UL << (ebx & 0x3f);
539
540 /* Check the SEV MSR whether SEV or SME is enabled */
541 sev_status = __rdmsr(MSR_AMD64_SEV);
542 feature_mask = (sev_status & MSR_AMD64_SEV_ENABLED) ? AMD_SEV_BIT : AMD_SME_BIT;
543
544 /* Check if memory encryption is enabled */
545 if (feature_mask == AMD_SME_BIT) {
546 /*
547 * No SME if Hypervisor bit is set. This check is here to
548 * prevent a guest from trying to enable SME. For running as a
549 * KVM guest the MSR_AMD64_SYSCFG will be sufficient, but there
550 * might be other hypervisors which emulate that MSR as non-zero
551 * or even pass it through to the guest.
552 * A malicious hypervisor can still trick a guest into this
553 * path, but there is no way to protect against that.
554 */
555 eax = 1;
556 ecx = 0;
557 native_cpuid(&eax, &ebx, &ecx, &edx);
558 if (ecx & BIT(31))
559 return;
560
561 /* For SME, check the SYSCFG MSR */
562 msr = __rdmsr(MSR_AMD64_SYSCFG);
563 if (!(msr & MSR_AMD64_SYSCFG_MEM_ENCRYPT))
564 return;
565 } else {
566 /* SEV state cannot be controlled by a command line option */
567 sme_me_mask = me_mask;
568 physical_mask &= ~sme_me_mask;
569 return;
570 }
571
572 /*
573 * Fixups have not been applied to phys_base yet and we're running
574 * identity mapped, so we must obtain the address to the SME command
575 * line argument data using rip-relative addressing.
576 */
577 asm ("lea sme_cmdline_arg(%%rip), %0"
578 : "=r" (cmdline_arg)
579 : "p" (sme_cmdline_arg));
580 asm ("lea sme_cmdline_on(%%rip), %0"
581 : "=r" (cmdline_on)
582 : "p" (sme_cmdline_on));
583 asm ("lea sme_cmdline_off(%%rip), %0"
584 : "=r" (cmdline_off)
585 : "p" (sme_cmdline_off));
586
587 if (IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT))
588 active_by_default = true;
589 else
590 active_by_default = false;
591
592 cmdline_ptr = (const char *)((u64)bp->hdr.cmd_line_ptr |
593 ((u64)bp->ext_cmd_line_ptr << 32));
594
595 cmdline_find_option(cmdline_ptr, cmdline_arg, buffer, sizeof(buffer));
596
597 if (!strncmp(buffer, cmdline_on, sizeof(buffer)))
598 sme_me_mask = me_mask;
599 else if (!strncmp(buffer, cmdline_off, sizeof(buffer)))
600 sme_me_mask = 0;
601 else
602 sme_me_mask = active_by_default ? me_mask : 0;
603
604 physical_mask &= ~sme_me_mask;
605 }
606