1 /*
2 * arch/xtensa/kernel/setup.c
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 1995 Linus Torvalds
9 * Copyright (C) 2001 - 2005 Tensilica Inc.
10 * Copyright (C) 2014 - 2016 Cadence Design Systems Inc.
11 *
12 * Chris Zankel <chris@zankel.net>
13 * Joe Taylor <joe@tensilica.com, joetylr@yahoo.com>
14 * Kevin Chea
15 * Marc Gauthier<marc@tensilica.com> <marc@alumni.uwaterloo.ca>
16 */
17
18 #include <linux/errno.h>
19 #include <linux/init.h>
20 #include <linux/mm.h>
21 #include <linux/proc_fs.h>
22 #include <linux/screen_info.h>
23 #include <linux/kernel.h>
24 #include <linux/percpu.h>
25 #include <linux/cpu.h>
26 #include <linux/of.h>
27 #include <linux/of_fdt.h>
28
29 #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
30 # include <linux/console.h>
31 #endif
32
33 #ifdef CONFIG_PROC_FS
34 # include <linux/seq_file.h>
35 #endif
36
37 #include <asm/bootparam.h>
38 #include <asm/kasan.h>
39 #include <asm/mmu_context.h>
40 #include <asm/page.h>
41 #include <asm/param.h>
42 #include <asm/platform.h>
43 #include <asm/processor.h>
44 #include <asm/sections.h>
45 #include <asm/setup.h>
46 #include <asm/smp.h>
47 #include <asm/sysmem.h>
48 #include <asm/timex.h>
49
50 #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
51 struct screen_info screen_info = {
52 .orig_x = 0,
53 .orig_y = 24,
54 .orig_video_cols = 80,
55 .orig_video_lines = 24,
56 .orig_video_isVGA = 1,
57 .orig_video_points = 16,
58 };
59 #endif
60
61 #ifdef CONFIG_BLK_DEV_INITRD
62 extern unsigned long initrd_start;
63 extern unsigned long initrd_end;
64 extern int initrd_below_start_ok;
65 #endif
66
67 #ifdef CONFIG_USE_OF
68 void *dtb_start = __dtb_start;
69 #endif
70
71 extern unsigned long loops_per_jiffy;
72
73 /* Command line specified as configuration option. */
74
75 static char __initdata command_line[COMMAND_LINE_SIZE];
76
77 #ifdef CONFIG_CMDLINE_BOOL
78 static char default_command_line[COMMAND_LINE_SIZE] __initdata = CONFIG_CMDLINE;
79 #endif
80
81 #ifdef CONFIG_PARSE_BOOTPARAM
82 /*
83 * Boot parameter parsing.
84 *
85 * The Xtensa port uses a list of variable-sized tags to pass data to
86 * the kernel. The first tag must be a BP_TAG_FIRST tag for the list
87 * to be recognised. The list is terminated with a zero-sized
88 * BP_TAG_LAST tag.
89 */
90
91 typedef struct tagtable {
92 u32 tag;
93 int (*parse)(const bp_tag_t*);
94 } tagtable_t;
95
96 #define __tagtable(tag, fn) static tagtable_t __tagtable_##fn \
97 __section(".taglist") __attribute__((used)) = { tag, fn }
98
99 /* parse current tag */
100
parse_tag_mem(const bp_tag_t * tag)101 static int __init parse_tag_mem(const bp_tag_t *tag)
102 {
103 struct bp_meminfo *mi = (struct bp_meminfo *)(tag->data);
104
105 if (mi->type != MEMORY_TYPE_CONVENTIONAL)
106 return -1;
107
108 return memblock_add(mi->start, mi->end - mi->start);
109 }
110
111 __tagtable(BP_TAG_MEMORY, parse_tag_mem);
112
113 #ifdef CONFIG_BLK_DEV_INITRD
114
parse_tag_initrd(const bp_tag_t * tag)115 static int __init parse_tag_initrd(const bp_tag_t* tag)
116 {
117 struct bp_meminfo *mi = (struct bp_meminfo *)(tag->data);
118
119 initrd_start = (unsigned long)__va(mi->start);
120 initrd_end = (unsigned long)__va(mi->end);
121
122 return 0;
123 }
124
125 __tagtable(BP_TAG_INITRD, parse_tag_initrd);
126
127 #endif /* CONFIG_BLK_DEV_INITRD */
128
129 #ifdef CONFIG_USE_OF
130
parse_tag_fdt(const bp_tag_t * tag)131 static int __init parse_tag_fdt(const bp_tag_t *tag)
132 {
133 dtb_start = __va(tag->data[0]);
134 return 0;
135 }
136
137 __tagtable(BP_TAG_FDT, parse_tag_fdt);
138
139 #endif /* CONFIG_USE_OF */
140
parse_tag_cmdline(const bp_tag_t * tag)141 static int __init parse_tag_cmdline(const bp_tag_t* tag)
142 {
143 strlcpy(command_line, (char *)(tag->data), COMMAND_LINE_SIZE);
144 return 0;
145 }
146
147 __tagtable(BP_TAG_COMMAND_LINE, parse_tag_cmdline);
148
parse_bootparam(const bp_tag_t * tag)149 static int __init parse_bootparam(const bp_tag_t* tag)
150 {
151 extern tagtable_t __tagtable_begin, __tagtable_end;
152 tagtable_t *t;
153
154 /* Boot parameters must start with a BP_TAG_FIRST tag. */
155
156 if (tag->id != BP_TAG_FIRST) {
157 pr_warn("Invalid boot parameters!\n");
158 return 0;
159 }
160
161 tag = (bp_tag_t*)((unsigned long)tag + sizeof(bp_tag_t) + tag->size);
162
163 /* Parse all tags. */
164
165 while (tag != NULL && tag->id != BP_TAG_LAST) {
166 for (t = &__tagtable_begin; t < &__tagtable_end; t++) {
167 if (tag->id == t->tag) {
168 t->parse(tag);
169 break;
170 }
171 }
172 if (t == &__tagtable_end)
173 pr_warn("Ignoring tag 0x%08x\n", tag->id);
174 tag = (bp_tag_t*)((unsigned long)(tag + 1) + tag->size);
175 }
176
177 return 0;
178 }
179 #else
parse_bootparam(const bp_tag_t * tag)180 static int __init parse_bootparam(const bp_tag_t *tag)
181 {
182 pr_info("Ignoring boot parameters at %p\n", tag);
183 return 0;
184 }
185 #endif
186
187 #ifdef CONFIG_USE_OF
188
189 #if !XCHAL_HAVE_PTP_MMU || XCHAL_HAVE_SPANNING_WAY
190 unsigned long xtensa_kio_paddr = XCHAL_KIO_DEFAULT_PADDR;
191 EXPORT_SYMBOL(xtensa_kio_paddr);
192
xtensa_dt_io_area(unsigned long node,const char * uname,int depth,void * data)193 static int __init xtensa_dt_io_area(unsigned long node, const char *uname,
194 int depth, void *data)
195 {
196 const __be32 *ranges;
197 int len;
198
199 if (depth > 1)
200 return 0;
201
202 if (!of_flat_dt_is_compatible(node, "simple-bus"))
203 return 0;
204
205 ranges = of_get_flat_dt_prop(node, "ranges", &len);
206 if (!ranges)
207 return 1;
208 if (len == 0)
209 return 1;
210
211 xtensa_kio_paddr = of_read_ulong(ranges+1, 1);
212 /* round down to nearest 256MB boundary */
213 xtensa_kio_paddr &= 0xf0000000;
214
215 init_kio();
216
217 return 1;
218 }
219 #else
xtensa_dt_io_area(unsigned long node,const char * uname,int depth,void * data)220 static int __init xtensa_dt_io_area(unsigned long node, const char *uname,
221 int depth, void *data)
222 {
223 return 1;
224 }
225 #endif
226
early_init_devtree(void * params)227 void __init early_init_devtree(void *params)
228 {
229 early_init_dt_scan(params);
230 of_scan_flat_dt(xtensa_dt_io_area, NULL);
231
232 if (!command_line[0])
233 strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
234 }
235
236 #endif /* CONFIG_USE_OF */
237
238 /*
239 * Initialize architecture. (Early stage)
240 */
241
init_arch(bp_tag_t * bp_start)242 void __init init_arch(bp_tag_t *bp_start)
243 {
244 /* Initialize MMU. */
245
246 init_mmu();
247
248 /* Initialize initial KASAN shadow map */
249
250 kasan_early_init();
251
252 /* Parse boot parameters */
253
254 if (bp_start)
255 parse_bootparam(bp_start);
256
257 #ifdef CONFIG_USE_OF
258 early_init_devtree(dtb_start);
259 #endif
260
261 #ifdef CONFIG_CMDLINE_BOOL
262 if (!command_line[0])
263 strlcpy(command_line, default_command_line, COMMAND_LINE_SIZE);
264 #endif
265
266 /* Early hook for platforms */
267
268 platform_init(bp_start);
269 }
270
271 /*
272 * Initialize system. Setup memory and reserve regions.
273 */
274
mem_reserve(unsigned long start,unsigned long end)275 static inline int __init_memblock mem_reserve(unsigned long start,
276 unsigned long end)
277 {
278 return memblock_reserve(start, end - start);
279 }
280
setup_arch(char ** cmdline_p)281 void __init setup_arch(char **cmdline_p)
282 {
283 pr_info("config ID: %08x:%08x\n",
284 xtensa_get_sr(SREG_EPC), xtensa_get_sr(SREG_EXCSAVE));
285 if (xtensa_get_sr(SREG_EPC) != XCHAL_HW_CONFIGID0 ||
286 xtensa_get_sr(SREG_EXCSAVE) != XCHAL_HW_CONFIGID1)
287 pr_info("built for config ID: %08x:%08x\n",
288 XCHAL_HW_CONFIGID0, XCHAL_HW_CONFIGID1);
289
290 *cmdline_p = command_line;
291 platform_setup(cmdline_p);
292 strlcpy(boot_command_line, *cmdline_p, COMMAND_LINE_SIZE);
293
294 /* Reserve some memory regions */
295
296 #ifdef CONFIG_BLK_DEV_INITRD
297 if (initrd_start < initrd_end &&
298 !mem_reserve(__pa(initrd_start), __pa(initrd_end)))
299 initrd_below_start_ok = 1;
300 else
301 initrd_start = 0;
302 #endif
303
304 mem_reserve(__pa(_stext), __pa(_end));
305 #ifdef CONFIG_XIP_KERNEL
306 mem_reserve(__pa(_xip_start), __pa(_xip_end));
307 #endif
308
309 #ifdef CONFIG_VECTORS_ADDR
310 #ifdef SUPPORT_WINDOWED
311 mem_reserve(__pa(_WindowVectors_text_start),
312 __pa(_WindowVectors_text_end));
313 #endif
314
315 mem_reserve(__pa(_DebugInterruptVector_text_start),
316 __pa(_DebugInterruptVector_text_end));
317
318 mem_reserve(__pa(_KernelExceptionVector_text_start),
319 __pa(_KernelExceptionVector_text_end));
320
321 mem_reserve(__pa(_UserExceptionVector_text_start),
322 __pa(_UserExceptionVector_text_end));
323
324 mem_reserve(__pa(_DoubleExceptionVector_text_start),
325 __pa(_DoubleExceptionVector_text_end));
326
327 mem_reserve(__pa(_exception_text_start),
328 __pa(_exception_text_end));
329 #if XCHAL_EXCM_LEVEL >= 2
330 mem_reserve(__pa(_Level2InterruptVector_text_start),
331 __pa(_Level2InterruptVector_text_end));
332 #endif
333 #if XCHAL_EXCM_LEVEL >= 3
334 mem_reserve(__pa(_Level3InterruptVector_text_start),
335 __pa(_Level3InterruptVector_text_end));
336 #endif
337 #if XCHAL_EXCM_LEVEL >= 4
338 mem_reserve(__pa(_Level4InterruptVector_text_start),
339 __pa(_Level4InterruptVector_text_end));
340 #endif
341 #if XCHAL_EXCM_LEVEL >= 5
342 mem_reserve(__pa(_Level5InterruptVector_text_start),
343 __pa(_Level5InterruptVector_text_end));
344 #endif
345 #if XCHAL_EXCM_LEVEL >= 6
346 mem_reserve(__pa(_Level6InterruptVector_text_start),
347 __pa(_Level6InterruptVector_text_end));
348 #endif
349
350 #endif /* CONFIG_VECTORS_ADDR */
351
352 #ifdef CONFIG_SMP
353 mem_reserve(__pa(_SecondaryResetVector_text_start),
354 __pa(_SecondaryResetVector_text_end));
355 #endif
356 parse_early_param();
357 bootmem_init();
358 kasan_init();
359 unflatten_and_copy_device_tree();
360
361 #ifdef CONFIG_SMP
362 smp_init_cpus();
363 #endif
364
365 paging_init();
366 zones_init();
367
368 #ifdef CONFIG_VT
369 # if defined(CONFIG_VGA_CONSOLE)
370 conswitchp = &vga_con;
371 # endif
372 #endif
373 }
374
375 static DEFINE_PER_CPU(struct cpu, cpu_data);
376
topology_init(void)377 static int __init topology_init(void)
378 {
379 int i;
380
381 for_each_possible_cpu(i) {
382 struct cpu *cpu = &per_cpu(cpu_data, i);
383 cpu->hotpluggable = !!i;
384 register_cpu(cpu, i);
385 }
386
387 return 0;
388 }
389 subsys_initcall(topology_init);
390
cpu_reset(void)391 void cpu_reset(void)
392 {
393 #if XCHAL_HAVE_PTP_MMU && IS_ENABLED(CONFIG_MMU)
394 local_irq_disable();
395 /*
396 * We have full MMU: all autoload ways, ways 7, 8 and 9 of DTLB must
397 * be flushed.
398 * Way 4 is not currently used by linux.
399 * Ways 5 and 6 shall not be touched on MMUv2 as they are hardwired.
400 * Way 5 shall be flushed and way 6 shall be set to identity mapping
401 * on MMUv3.
402 */
403 local_flush_tlb_all();
404 invalidate_page_directory();
405 #if XCHAL_HAVE_SPANNING_WAY
406 /* MMU v3 */
407 {
408 unsigned long vaddr = (unsigned long)cpu_reset;
409 unsigned long paddr = __pa(vaddr);
410 unsigned long tmpaddr = vaddr + SZ_512M;
411 unsigned long tmp0, tmp1, tmp2, tmp3;
412
413 /*
414 * Find a place for the temporary mapping. It must not be
415 * in the same 512MB region with vaddr or paddr, otherwise
416 * there may be multihit exception either on entry to the
417 * temporary mapping, or on entry to the identity mapping.
418 * (512MB is the biggest page size supported by TLB.)
419 */
420 while (((tmpaddr ^ paddr) & -SZ_512M) == 0)
421 tmpaddr += SZ_512M;
422
423 /* Invalidate mapping in the selected temporary area */
424 if (itlb_probe(tmpaddr) & BIT(ITLB_HIT_BIT))
425 invalidate_itlb_entry(itlb_probe(tmpaddr));
426 if (itlb_probe(tmpaddr + PAGE_SIZE) & BIT(ITLB_HIT_BIT))
427 invalidate_itlb_entry(itlb_probe(tmpaddr + PAGE_SIZE));
428
429 /*
430 * Map two consecutive pages starting at the physical address
431 * of this function to the temporary mapping area.
432 */
433 write_itlb_entry(__pte((paddr & PAGE_MASK) |
434 _PAGE_HW_VALID |
435 _PAGE_HW_EXEC |
436 _PAGE_CA_BYPASS),
437 tmpaddr & PAGE_MASK);
438 write_itlb_entry(__pte(((paddr & PAGE_MASK) + PAGE_SIZE) |
439 _PAGE_HW_VALID |
440 _PAGE_HW_EXEC |
441 _PAGE_CA_BYPASS),
442 (tmpaddr & PAGE_MASK) + PAGE_SIZE);
443
444 /* Reinitialize TLB */
445 __asm__ __volatile__ ("movi %0, 1f\n\t"
446 "movi %3, 2f\n\t"
447 "add %0, %0, %4\n\t"
448 "add %3, %3, %5\n\t"
449 "jx %0\n"
450 /*
451 * No literal, data or stack access
452 * below this point
453 */
454 "1:\n\t"
455 /* Initialize *tlbcfg */
456 "movi %0, 0\n\t"
457 "wsr %0, itlbcfg\n\t"
458 "wsr %0, dtlbcfg\n\t"
459 /* Invalidate TLB way 5 */
460 "movi %0, 4\n\t"
461 "movi %1, 5\n"
462 "1:\n\t"
463 "iitlb %1\n\t"
464 "idtlb %1\n\t"
465 "add %1, %1, %6\n\t"
466 "addi %0, %0, -1\n\t"
467 "bnez %0, 1b\n\t"
468 /* Initialize TLB way 6 */
469 "movi %0, 7\n\t"
470 "addi %1, %9, 3\n\t"
471 "addi %2, %9, 6\n"
472 "1:\n\t"
473 "witlb %1, %2\n\t"
474 "wdtlb %1, %2\n\t"
475 "add %1, %1, %7\n\t"
476 "add %2, %2, %7\n\t"
477 "addi %0, %0, -1\n\t"
478 "bnez %0, 1b\n\t"
479 "isync\n\t"
480 /* Jump to identity mapping */
481 "jx %3\n"
482 "2:\n\t"
483 /* Complete way 6 initialization */
484 "witlb %1, %2\n\t"
485 "wdtlb %1, %2\n\t"
486 /* Invalidate temporary mapping */
487 "sub %0, %9, %7\n\t"
488 "iitlb %0\n\t"
489 "add %0, %0, %8\n\t"
490 "iitlb %0"
491 : "=&a"(tmp0), "=&a"(tmp1), "=&a"(tmp2),
492 "=&a"(tmp3)
493 : "a"(tmpaddr - vaddr),
494 "a"(paddr - vaddr),
495 "a"(SZ_128M), "a"(SZ_512M),
496 "a"(PAGE_SIZE),
497 "a"((tmpaddr + SZ_512M) & PAGE_MASK)
498 : "memory");
499 }
500 #endif
501 #endif
502 __asm__ __volatile__ ("movi a2, 0\n\t"
503 "wsr a2, icountlevel\n\t"
504 "movi a2, 0\n\t"
505 "wsr a2, icount\n\t"
506 #if XCHAL_NUM_IBREAK > 0
507 "wsr a2, ibreakenable\n\t"
508 #endif
509 #if XCHAL_HAVE_LOOPS
510 "wsr a2, lcount\n\t"
511 #endif
512 "movi a2, 0x1f\n\t"
513 "wsr a2, ps\n\t"
514 "isync\n\t"
515 "jx %0\n\t"
516 :
517 : "a" (XCHAL_RESET_VECTOR_VADDR)
518 : "a2");
519 for (;;)
520 ;
521 }
522
machine_restart(char * cmd)523 void machine_restart(char * cmd)
524 {
525 platform_restart();
526 }
527
machine_halt(void)528 void machine_halt(void)
529 {
530 platform_halt();
531 while (1);
532 }
533
machine_power_off(void)534 void machine_power_off(void)
535 {
536 platform_power_off();
537 while (1);
538 }
539 #ifdef CONFIG_PROC_FS
540
541 /*
542 * Display some core information through /proc/cpuinfo.
543 */
544
545 static int
c_show(struct seq_file * f,void * slot)546 c_show(struct seq_file *f, void *slot)
547 {
548 /* high-level stuff */
549 seq_printf(f, "CPU count\t: %u\n"
550 "CPU list\t: %*pbl\n"
551 "vendor_id\t: Tensilica\n"
552 "model\t\t: Xtensa " XCHAL_HW_VERSION_NAME "\n"
553 "core ID\t\t: " XCHAL_CORE_ID "\n"
554 "build ID\t: 0x%x\n"
555 "config ID\t: %08x:%08x\n"
556 "byte order\t: %s\n"
557 "cpu MHz\t\t: %lu.%02lu\n"
558 "bogomips\t: %lu.%02lu\n",
559 num_online_cpus(),
560 cpumask_pr_args(cpu_online_mask),
561 XCHAL_BUILD_UNIQUE_ID,
562 xtensa_get_sr(SREG_EPC), xtensa_get_sr(SREG_EXCSAVE),
563 XCHAL_HAVE_BE ? "big" : "little",
564 ccount_freq/1000000,
565 (ccount_freq/10000) % 100,
566 loops_per_jiffy/(500000/HZ),
567 (loops_per_jiffy/(5000/HZ)) % 100);
568 seq_puts(f, "flags\t\t: "
569 #if XCHAL_HAVE_NMI
570 "nmi "
571 #endif
572 #if XCHAL_HAVE_DEBUG
573 "debug "
574 # if XCHAL_HAVE_OCD
575 "ocd "
576 # endif
577 #endif
578 #if XCHAL_HAVE_DENSITY
579 "density "
580 #endif
581 #if XCHAL_HAVE_BOOLEANS
582 "boolean "
583 #endif
584 #if XCHAL_HAVE_LOOPS
585 "loop "
586 #endif
587 #if XCHAL_HAVE_NSA
588 "nsa "
589 #endif
590 #if XCHAL_HAVE_MINMAX
591 "minmax "
592 #endif
593 #if XCHAL_HAVE_SEXT
594 "sext "
595 #endif
596 #if XCHAL_HAVE_CLAMPS
597 "clamps "
598 #endif
599 #if XCHAL_HAVE_MAC16
600 "mac16 "
601 #endif
602 #if XCHAL_HAVE_MUL16
603 "mul16 "
604 #endif
605 #if XCHAL_HAVE_MUL32
606 "mul32 "
607 #endif
608 #if XCHAL_HAVE_MUL32_HIGH
609 "mul32h "
610 #endif
611 #if XCHAL_HAVE_FP
612 "fpu "
613 #endif
614 #if XCHAL_HAVE_S32C1I
615 "s32c1i "
616 #endif
617 #if XCHAL_HAVE_EXCLUSIVE
618 "exclusive "
619 #endif
620 "\n");
621
622 /* Registers. */
623 seq_printf(f,"physical aregs\t: %d\n"
624 "misc regs\t: %d\n"
625 "ibreak\t\t: %d\n"
626 "dbreak\t\t: %d\n",
627 XCHAL_NUM_AREGS,
628 XCHAL_NUM_MISC_REGS,
629 XCHAL_NUM_IBREAK,
630 XCHAL_NUM_DBREAK);
631
632
633 /* Interrupt. */
634 seq_printf(f,"num ints\t: %d\n"
635 "ext ints\t: %d\n"
636 "int levels\t: %d\n"
637 "timers\t\t: %d\n"
638 "debug level\t: %d\n",
639 XCHAL_NUM_INTERRUPTS,
640 XCHAL_NUM_EXTINTERRUPTS,
641 XCHAL_NUM_INTLEVELS,
642 XCHAL_NUM_TIMERS,
643 XCHAL_DEBUGLEVEL);
644
645 /* Cache */
646 seq_printf(f,"icache line size: %d\n"
647 "icache ways\t: %d\n"
648 "icache size\t: %d\n"
649 "icache flags\t: "
650 #if XCHAL_ICACHE_LINE_LOCKABLE
651 "lock "
652 #endif
653 "\n"
654 "dcache line size: %d\n"
655 "dcache ways\t: %d\n"
656 "dcache size\t: %d\n"
657 "dcache flags\t: "
658 #if XCHAL_DCACHE_IS_WRITEBACK
659 "writeback "
660 #endif
661 #if XCHAL_DCACHE_LINE_LOCKABLE
662 "lock "
663 #endif
664 "\n",
665 XCHAL_ICACHE_LINESIZE,
666 XCHAL_ICACHE_WAYS,
667 XCHAL_ICACHE_SIZE,
668 XCHAL_DCACHE_LINESIZE,
669 XCHAL_DCACHE_WAYS,
670 XCHAL_DCACHE_SIZE);
671
672 return 0;
673 }
674
675 /*
676 * We show only CPU #0 info.
677 */
678 static void *
c_start(struct seq_file * f,loff_t * pos)679 c_start(struct seq_file *f, loff_t *pos)
680 {
681 return (*pos == 0) ? (void *)1 : NULL;
682 }
683
684 static void *
c_next(struct seq_file * f,void * v,loff_t * pos)685 c_next(struct seq_file *f, void *v, loff_t *pos)
686 {
687 ++*pos;
688 return c_start(f, pos);
689 }
690
691 static void
c_stop(struct seq_file * f,void * v)692 c_stop(struct seq_file *f, void *v)
693 {
694 }
695
696 const struct seq_operations cpuinfo_op =
697 {
698 .start = c_start,
699 .next = c_next,
700 .stop = c_stop,
701 .show = c_show,
702 };
703
704 #endif /* CONFIG_PROC_FS */
705