1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * libahci.c - Common AHCI SATA low-level routines
4 *
5 * Maintained by: Tejun Heo <tj@kernel.org>
6 * Please ALWAYS copy linux-ide@vger.kernel.org
7 * on emails.
8 *
9 * Copyright 2004-2005 Red Hat, Inc.
10 *
11 * libata documentation is available via 'make {ps|pdf}docs',
12 * as Documentation/driver-api/libata.rst
13 *
14 * AHCI hardware documentation:
15 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
16 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
17 */
18
19 #include <linux/kernel.h>
20 #include <linux/gfp.h>
21 #include <linux/module.h>
22 #include <linux/nospec.h>
23 #include <linux/blkdev.h>
24 #include <linux/delay.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/device.h>
28 #include <scsi/scsi_host.h>
29 #include <scsi/scsi_cmnd.h>
30 #include <linux/libata.h>
31 #include <linux/pci.h>
32 #include "ahci.h"
33 #include "libata.h"
34
35 static int ahci_skip_host_reset;
36 int ahci_ignore_sss;
37 EXPORT_SYMBOL_GPL(ahci_ignore_sss);
38
39 module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
40 MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
41
42 module_param_named(ignore_sss, ahci_ignore_sss, int, 0444);
43 MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)");
44
45 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
46 unsigned hints);
47 static ssize_t ahci_led_show(struct ata_port *ap, char *buf);
48 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
49 size_t size);
50 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
51 ssize_t size);
52
53
54
55 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
56 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
57 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
58 static int ahci_port_start(struct ata_port *ap);
59 static void ahci_port_stop(struct ata_port *ap);
60 static enum ata_completion_errors ahci_qc_prep(struct ata_queued_cmd *qc);
61 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc);
62 static void ahci_freeze(struct ata_port *ap);
63 static void ahci_thaw(struct ata_port *ap);
64 static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep);
65 static void ahci_enable_fbs(struct ata_port *ap);
66 static void ahci_disable_fbs(struct ata_port *ap);
67 static void ahci_pmp_attach(struct ata_port *ap);
68 static void ahci_pmp_detach(struct ata_port *ap);
69 static int ahci_softreset(struct ata_link *link, unsigned int *class,
70 unsigned long deadline);
71 static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
72 unsigned long deadline);
73 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
74 unsigned long deadline);
75 static void ahci_postreset(struct ata_link *link, unsigned int *class);
76 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
77 static void ahci_dev_config(struct ata_device *dev);
78 #ifdef CONFIG_PM
79 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
80 #endif
81 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf);
82 static ssize_t ahci_activity_store(struct ata_device *dev,
83 enum sw_activity val);
84 static void ahci_init_sw_activity(struct ata_link *link);
85
86 static ssize_t ahci_show_host_caps(struct device *dev,
87 struct device_attribute *attr, char *buf);
88 static ssize_t ahci_show_host_cap2(struct device *dev,
89 struct device_attribute *attr, char *buf);
90 static ssize_t ahci_show_host_version(struct device *dev,
91 struct device_attribute *attr, char *buf);
92 static ssize_t ahci_show_port_cmd(struct device *dev,
93 struct device_attribute *attr, char *buf);
94 static ssize_t ahci_read_em_buffer(struct device *dev,
95 struct device_attribute *attr, char *buf);
96 static ssize_t ahci_store_em_buffer(struct device *dev,
97 struct device_attribute *attr,
98 const char *buf, size_t size);
99 static ssize_t ahci_show_em_supported(struct device *dev,
100 struct device_attribute *attr, char *buf);
101 static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance);
102
103 static DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL);
104 static DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL);
105 static DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL);
106 static DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL);
107 static DEVICE_ATTR(em_buffer, S_IWUSR | S_IRUGO,
108 ahci_read_em_buffer, ahci_store_em_buffer);
109 static DEVICE_ATTR(em_message_supported, S_IRUGO, ahci_show_em_supported, NULL);
110
111 static struct attribute *ahci_shost_attrs[] = {
112 &dev_attr_link_power_management_policy.attr,
113 &dev_attr_em_message_type.attr,
114 &dev_attr_em_message.attr,
115 &dev_attr_ahci_host_caps.attr,
116 &dev_attr_ahci_host_cap2.attr,
117 &dev_attr_ahci_host_version.attr,
118 &dev_attr_ahci_port_cmd.attr,
119 &dev_attr_em_buffer.attr,
120 &dev_attr_em_message_supported.attr,
121 NULL
122 };
123
124 static const struct attribute_group ahci_shost_attr_group = {
125 .attrs = ahci_shost_attrs
126 };
127
128 const struct attribute_group *ahci_shost_groups[] = {
129 &ahci_shost_attr_group,
130 NULL
131 };
132 EXPORT_SYMBOL_GPL(ahci_shost_groups);
133
134 static struct attribute *ahci_sdev_attrs[] = {
135 &dev_attr_sw_activity.attr,
136 &dev_attr_unload_heads.attr,
137 &dev_attr_ncq_prio_supported.attr,
138 &dev_attr_ncq_prio_enable.attr,
139 NULL
140 };
141
142 static const struct attribute_group ahci_sdev_attr_group = {
143 .attrs = ahci_sdev_attrs
144 };
145
146 const struct attribute_group *ahci_sdev_groups[] = {
147 &ahci_sdev_attr_group,
148 NULL
149 };
150 EXPORT_SYMBOL_GPL(ahci_sdev_groups);
151
152 struct ata_port_operations ahci_ops = {
153 .inherits = &sata_pmp_port_ops,
154
155 .qc_defer = ahci_pmp_qc_defer,
156 .qc_prep = ahci_qc_prep,
157 .qc_issue = ahci_qc_issue,
158 .qc_fill_rtf = ahci_qc_fill_rtf,
159
160 .freeze = ahci_freeze,
161 .thaw = ahci_thaw,
162 .softreset = ahci_softreset,
163 .hardreset = ahci_hardreset,
164 .postreset = ahci_postreset,
165 .pmp_softreset = ahci_softreset,
166 .error_handler = ahci_error_handler,
167 .post_internal_cmd = ahci_post_internal_cmd,
168 .dev_config = ahci_dev_config,
169
170 .scr_read = ahci_scr_read,
171 .scr_write = ahci_scr_write,
172 .pmp_attach = ahci_pmp_attach,
173 .pmp_detach = ahci_pmp_detach,
174
175 .set_lpm = ahci_set_lpm,
176 .em_show = ahci_led_show,
177 .em_store = ahci_led_store,
178 .sw_activity_show = ahci_activity_show,
179 .sw_activity_store = ahci_activity_store,
180 .transmit_led_message = ahci_transmit_led_message,
181 #ifdef CONFIG_PM
182 .port_suspend = ahci_port_suspend,
183 .port_resume = ahci_port_resume,
184 #endif
185 .port_start = ahci_port_start,
186 .port_stop = ahci_port_stop,
187 };
188 EXPORT_SYMBOL_GPL(ahci_ops);
189
190 struct ata_port_operations ahci_pmp_retry_srst_ops = {
191 .inherits = &ahci_ops,
192 .softreset = ahci_pmp_retry_softreset,
193 };
194 EXPORT_SYMBOL_GPL(ahci_pmp_retry_srst_ops);
195
196 static bool ahci_em_messages __read_mostly = true;
197 module_param(ahci_em_messages, bool, 0444);
198 /* add other LED protocol types when they become supported */
199 MODULE_PARM_DESC(ahci_em_messages,
200 "AHCI Enclosure Management Message control (0 = off, 1 = on)");
201
202 /* device sleep idle timeout in ms */
203 static int devslp_idle_timeout __read_mostly = 1000;
204 module_param(devslp_idle_timeout, int, 0644);
205 MODULE_PARM_DESC(devslp_idle_timeout, "device sleep idle timeout");
206
ahci_enable_ahci(void __iomem * mmio)207 static void ahci_enable_ahci(void __iomem *mmio)
208 {
209 int i;
210 u32 tmp;
211
212 /* turn on AHCI_EN */
213 tmp = readl(mmio + HOST_CTL);
214 if (tmp & HOST_AHCI_EN)
215 return;
216
217 /* Some controllers need AHCI_EN to be written multiple times.
218 * Try a few times before giving up.
219 */
220 for (i = 0; i < 5; i++) {
221 tmp |= HOST_AHCI_EN;
222 writel(tmp, mmio + HOST_CTL);
223 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
224 if (tmp & HOST_AHCI_EN)
225 return;
226 msleep(10);
227 }
228
229 WARN_ON(1);
230 }
231
232 /**
233 * ahci_rpm_get_port - Make sure the port is powered on
234 * @ap: Port to power on
235 *
236 * Whenever there is need to access the AHCI host registers outside of
237 * normal execution paths, call this function to make sure the host is
238 * actually powered on.
239 */
ahci_rpm_get_port(struct ata_port * ap)240 static int ahci_rpm_get_port(struct ata_port *ap)
241 {
242 return pm_runtime_get_sync(ap->dev);
243 }
244
245 /**
246 * ahci_rpm_put_port - Undoes ahci_rpm_get_port()
247 * @ap: Port to power down
248 *
249 * Undoes ahci_rpm_get_port() and possibly powers down the AHCI host
250 * if it has no more active users.
251 */
ahci_rpm_put_port(struct ata_port * ap)252 static void ahci_rpm_put_port(struct ata_port *ap)
253 {
254 pm_runtime_put(ap->dev);
255 }
256
ahci_show_host_caps(struct device * dev,struct device_attribute * attr,char * buf)257 static ssize_t ahci_show_host_caps(struct device *dev,
258 struct device_attribute *attr, char *buf)
259 {
260 struct Scsi_Host *shost = class_to_shost(dev);
261 struct ata_port *ap = ata_shost_to_port(shost);
262 struct ahci_host_priv *hpriv = ap->host->private_data;
263
264 return sprintf(buf, "%x\n", hpriv->cap);
265 }
266
ahci_show_host_cap2(struct device * dev,struct device_attribute * attr,char * buf)267 static ssize_t ahci_show_host_cap2(struct device *dev,
268 struct device_attribute *attr, char *buf)
269 {
270 struct Scsi_Host *shost = class_to_shost(dev);
271 struct ata_port *ap = ata_shost_to_port(shost);
272 struct ahci_host_priv *hpriv = ap->host->private_data;
273
274 return sprintf(buf, "%x\n", hpriv->cap2);
275 }
276
ahci_show_host_version(struct device * dev,struct device_attribute * attr,char * buf)277 static ssize_t ahci_show_host_version(struct device *dev,
278 struct device_attribute *attr, char *buf)
279 {
280 struct Scsi_Host *shost = class_to_shost(dev);
281 struct ata_port *ap = ata_shost_to_port(shost);
282 struct ahci_host_priv *hpriv = ap->host->private_data;
283
284 return sprintf(buf, "%x\n", hpriv->version);
285 }
286
ahci_show_port_cmd(struct device * dev,struct device_attribute * attr,char * buf)287 static ssize_t ahci_show_port_cmd(struct device *dev,
288 struct device_attribute *attr, char *buf)
289 {
290 struct Scsi_Host *shost = class_to_shost(dev);
291 struct ata_port *ap = ata_shost_to_port(shost);
292 void __iomem *port_mmio = ahci_port_base(ap);
293 ssize_t ret;
294
295 ahci_rpm_get_port(ap);
296 ret = sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD));
297 ahci_rpm_put_port(ap);
298
299 return ret;
300 }
301
ahci_read_em_buffer(struct device * dev,struct device_attribute * attr,char * buf)302 static ssize_t ahci_read_em_buffer(struct device *dev,
303 struct device_attribute *attr, char *buf)
304 {
305 struct Scsi_Host *shost = class_to_shost(dev);
306 struct ata_port *ap = ata_shost_to_port(shost);
307 struct ahci_host_priv *hpriv = ap->host->private_data;
308 void __iomem *mmio = hpriv->mmio;
309 void __iomem *em_mmio = mmio + hpriv->em_loc;
310 u32 em_ctl, msg;
311 unsigned long flags;
312 size_t count;
313 int i;
314
315 ahci_rpm_get_port(ap);
316 spin_lock_irqsave(ap->lock, flags);
317
318 em_ctl = readl(mmio + HOST_EM_CTL);
319 if (!(ap->flags & ATA_FLAG_EM) || em_ctl & EM_CTL_XMT ||
320 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO)) {
321 spin_unlock_irqrestore(ap->lock, flags);
322 ahci_rpm_put_port(ap);
323 return -EINVAL;
324 }
325
326 if (!(em_ctl & EM_CTL_MR)) {
327 spin_unlock_irqrestore(ap->lock, flags);
328 ahci_rpm_put_port(ap);
329 return -EAGAIN;
330 }
331
332 if (!(em_ctl & EM_CTL_SMB))
333 em_mmio += hpriv->em_buf_sz;
334
335 count = hpriv->em_buf_sz;
336
337 /* the count should not be larger than PAGE_SIZE */
338 if (count > PAGE_SIZE) {
339 if (printk_ratelimit())
340 ata_port_warn(ap,
341 "EM read buffer size too large: "
342 "buffer size %u, page size %lu\n",
343 hpriv->em_buf_sz, PAGE_SIZE);
344 count = PAGE_SIZE;
345 }
346
347 for (i = 0; i < count; i += 4) {
348 msg = readl(em_mmio + i);
349 buf[i] = msg & 0xff;
350 buf[i + 1] = (msg >> 8) & 0xff;
351 buf[i + 2] = (msg >> 16) & 0xff;
352 buf[i + 3] = (msg >> 24) & 0xff;
353 }
354
355 spin_unlock_irqrestore(ap->lock, flags);
356 ahci_rpm_put_port(ap);
357
358 return i;
359 }
360
ahci_store_em_buffer(struct device * dev,struct device_attribute * attr,const char * buf,size_t size)361 static ssize_t ahci_store_em_buffer(struct device *dev,
362 struct device_attribute *attr,
363 const char *buf, size_t size)
364 {
365 struct Scsi_Host *shost = class_to_shost(dev);
366 struct ata_port *ap = ata_shost_to_port(shost);
367 struct ahci_host_priv *hpriv = ap->host->private_data;
368 void __iomem *mmio = hpriv->mmio;
369 void __iomem *em_mmio = mmio + hpriv->em_loc;
370 const unsigned char *msg_buf = buf;
371 u32 em_ctl, msg;
372 unsigned long flags;
373 int i;
374
375 /* check size validity */
376 if (!(ap->flags & ATA_FLAG_EM) ||
377 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO) ||
378 size % 4 || size > hpriv->em_buf_sz)
379 return -EINVAL;
380
381 ahci_rpm_get_port(ap);
382 spin_lock_irqsave(ap->lock, flags);
383
384 em_ctl = readl(mmio + HOST_EM_CTL);
385 if (em_ctl & EM_CTL_TM) {
386 spin_unlock_irqrestore(ap->lock, flags);
387 ahci_rpm_put_port(ap);
388 return -EBUSY;
389 }
390
391 for (i = 0; i < size; i += 4) {
392 msg = msg_buf[i] | msg_buf[i + 1] << 8 |
393 msg_buf[i + 2] << 16 | msg_buf[i + 3] << 24;
394 writel(msg, em_mmio + i);
395 }
396
397 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
398
399 spin_unlock_irqrestore(ap->lock, flags);
400 ahci_rpm_put_port(ap);
401
402 return size;
403 }
404
ahci_show_em_supported(struct device * dev,struct device_attribute * attr,char * buf)405 static ssize_t ahci_show_em_supported(struct device *dev,
406 struct device_attribute *attr, char *buf)
407 {
408 struct Scsi_Host *shost = class_to_shost(dev);
409 struct ata_port *ap = ata_shost_to_port(shost);
410 struct ahci_host_priv *hpriv = ap->host->private_data;
411 void __iomem *mmio = hpriv->mmio;
412 u32 em_ctl;
413
414 ahci_rpm_get_port(ap);
415 em_ctl = readl(mmio + HOST_EM_CTL);
416 ahci_rpm_put_port(ap);
417
418 return sprintf(buf, "%s%s%s%s\n",
419 em_ctl & EM_CTL_LED ? "led " : "",
420 em_ctl & EM_CTL_SAFTE ? "saf-te " : "",
421 em_ctl & EM_CTL_SES ? "ses-2 " : "",
422 em_ctl & EM_CTL_SGPIO ? "sgpio " : "");
423 }
424
425 /**
426 * ahci_save_initial_config - Save and fixup initial config values
427 * @dev: target AHCI device
428 * @hpriv: host private area to store config values
429 *
430 * Some registers containing configuration info might be setup by
431 * BIOS and might be cleared on reset. This function saves the
432 * initial values of those registers into @hpriv such that they
433 * can be restored after controller reset.
434 *
435 * If inconsistent, config values are fixed up by this function.
436 *
437 * If it is not set already this function sets hpriv->start_engine to
438 * ahci_start_engine.
439 *
440 * LOCKING:
441 * None.
442 */
ahci_save_initial_config(struct device * dev,struct ahci_host_priv * hpriv)443 void ahci_save_initial_config(struct device *dev, struct ahci_host_priv *hpriv)
444 {
445 void __iomem *mmio = hpriv->mmio;
446 u32 cap, cap2, vers, port_map;
447 int i;
448
449 /* make sure AHCI mode is enabled before accessing CAP */
450 ahci_enable_ahci(mmio);
451
452 /* Values prefixed with saved_ are written back to host after
453 * reset. Values without are used for driver operation.
454 */
455 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
456 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
457
458 /* CAP2 register is only defined for AHCI 1.2 and later */
459 vers = readl(mmio + HOST_VERSION);
460 if ((vers >> 16) > 1 ||
461 ((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200))
462 hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2);
463 else
464 hpriv->saved_cap2 = cap2 = 0;
465
466 /* some chips have errata preventing 64bit use */
467 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
468 dev_info(dev, "controller can't do 64bit DMA, forcing 32bit\n");
469 cap &= ~HOST_CAP_64;
470 }
471
472 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
473 dev_info(dev, "controller can't do NCQ, turning off CAP_NCQ\n");
474 cap &= ~HOST_CAP_NCQ;
475 }
476
477 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
478 dev_info(dev, "controller can do NCQ, turning on CAP_NCQ\n");
479 cap |= HOST_CAP_NCQ;
480 }
481
482 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
483 dev_info(dev, "controller can't do PMP, turning off CAP_PMP\n");
484 cap &= ~HOST_CAP_PMP;
485 }
486
487 if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) {
488 dev_info(dev,
489 "controller can't do SNTF, turning off CAP_SNTF\n");
490 cap &= ~HOST_CAP_SNTF;
491 }
492
493 if ((cap2 & HOST_CAP2_SDS) && (hpriv->flags & AHCI_HFLAG_NO_DEVSLP)) {
494 dev_info(dev,
495 "controller can't do DEVSLP, turning off\n");
496 cap2 &= ~HOST_CAP2_SDS;
497 cap2 &= ~HOST_CAP2_SADM;
498 }
499
500 if (!(cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_YES_FBS)) {
501 dev_info(dev, "controller can do FBS, turning on CAP_FBS\n");
502 cap |= HOST_CAP_FBS;
503 }
504
505 if ((cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_NO_FBS)) {
506 dev_info(dev, "controller can't do FBS, turning off CAP_FBS\n");
507 cap &= ~HOST_CAP_FBS;
508 }
509
510 if (!(cap & HOST_CAP_ALPM) && (hpriv->flags & AHCI_HFLAG_YES_ALPM)) {
511 dev_info(dev, "controller can do ALPM, turning on CAP_ALPM\n");
512 cap |= HOST_CAP_ALPM;
513 }
514
515 if ((cap & HOST_CAP_SXS) && (hpriv->flags & AHCI_HFLAG_NO_SXS)) {
516 dev_info(dev, "controller does not support SXS, disabling CAP_SXS\n");
517 cap &= ~HOST_CAP_SXS;
518 }
519
520 if (hpriv->force_port_map && port_map != hpriv->force_port_map) {
521 dev_info(dev, "forcing port_map 0x%x -> 0x%x\n",
522 port_map, hpriv->force_port_map);
523 port_map = hpriv->force_port_map;
524 hpriv->saved_port_map = port_map;
525 }
526
527 if (hpriv->mask_port_map) {
528 dev_warn(dev, "masking port_map 0x%x -> 0x%x\n",
529 port_map,
530 port_map & hpriv->mask_port_map);
531 port_map &= hpriv->mask_port_map;
532 }
533
534 /* cross check port_map and cap.n_ports */
535 if (port_map) {
536 int map_ports = 0;
537
538 for (i = 0; i < AHCI_MAX_PORTS; i++)
539 if (port_map & (1 << i))
540 map_ports++;
541
542 /* If PI has more ports than n_ports, whine, clear
543 * port_map and let it be generated from n_ports.
544 */
545 if (map_ports > ahci_nr_ports(cap)) {
546 dev_warn(dev,
547 "implemented port map (0x%x) contains more ports than nr_ports (%u), using nr_ports\n",
548 port_map, ahci_nr_ports(cap));
549 port_map = 0;
550 }
551 }
552
553 /* fabricate port_map from cap.nr_ports for < AHCI 1.3 */
554 if (!port_map && vers < 0x10300) {
555 port_map = (1 << ahci_nr_ports(cap)) - 1;
556 dev_warn(dev, "forcing PORTS_IMPL to 0x%x\n", port_map);
557
558 /* write the fixed up value to the PI register */
559 hpriv->saved_port_map = port_map;
560 }
561
562 /* record values to use during operation */
563 hpriv->cap = cap;
564 hpriv->cap2 = cap2;
565 hpriv->version = readl(mmio + HOST_VERSION);
566 hpriv->port_map = port_map;
567
568 if (!hpriv->start_engine)
569 hpriv->start_engine = ahci_start_engine;
570
571 if (!hpriv->stop_engine)
572 hpriv->stop_engine = ahci_stop_engine;
573
574 if (!hpriv->irq_handler)
575 hpriv->irq_handler = ahci_single_level_irq_intr;
576 }
577 EXPORT_SYMBOL_GPL(ahci_save_initial_config);
578
579 /**
580 * ahci_restore_initial_config - Restore initial config
581 * @host: target ATA host
582 *
583 * Restore initial config stored by ahci_save_initial_config().
584 *
585 * LOCKING:
586 * None.
587 */
ahci_restore_initial_config(struct ata_host * host)588 static void ahci_restore_initial_config(struct ata_host *host)
589 {
590 struct ahci_host_priv *hpriv = host->private_data;
591 void __iomem *mmio = hpriv->mmio;
592
593 writel(hpriv->saved_cap, mmio + HOST_CAP);
594 if (hpriv->saved_cap2)
595 writel(hpriv->saved_cap2, mmio + HOST_CAP2);
596 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
597 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
598 }
599
ahci_scr_offset(struct ata_port * ap,unsigned int sc_reg)600 static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
601 {
602 static const int offset[] = {
603 [SCR_STATUS] = PORT_SCR_STAT,
604 [SCR_CONTROL] = PORT_SCR_CTL,
605 [SCR_ERROR] = PORT_SCR_ERR,
606 [SCR_ACTIVE] = PORT_SCR_ACT,
607 [SCR_NOTIFICATION] = PORT_SCR_NTF,
608 };
609 struct ahci_host_priv *hpriv = ap->host->private_data;
610
611 if (sc_reg < ARRAY_SIZE(offset) &&
612 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
613 return offset[sc_reg];
614 return 0;
615 }
616
ahci_scr_read(struct ata_link * link,unsigned int sc_reg,u32 * val)617 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
618 {
619 void __iomem *port_mmio = ahci_port_base(link->ap);
620 int offset = ahci_scr_offset(link->ap, sc_reg);
621
622 if (offset) {
623 *val = readl(port_mmio + offset);
624 return 0;
625 }
626 return -EINVAL;
627 }
628
ahci_scr_write(struct ata_link * link,unsigned int sc_reg,u32 val)629 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
630 {
631 void __iomem *port_mmio = ahci_port_base(link->ap);
632 int offset = ahci_scr_offset(link->ap, sc_reg);
633
634 if (offset) {
635 writel(val, port_mmio + offset);
636 return 0;
637 }
638 return -EINVAL;
639 }
640
ahci_start_engine(struct ata_port * ap)641 void ahci_start_engine(struct ata_port *ap)
642 {
643 void __iomem *port_mmio = ahci_port_base(ap);
644 u32 tmp;
645
646 /* start DMA */
647 tmp = readl(port_mmio + PORT_CMD);
648 tmp |= PORT_CMD_START;
649 writel(tmp, port_mmio + PORT_CMD);
650 readl(port_mmio + PORT_CMD); /* flush */
651 }
652 EXPORT_SYMBOL_GPL(ahci_start_engine);
653
ahci_stop_engine(struct ata_port * ap)654 int ahci_stop_engine(struct ata_port *ap)
655 {
656 void __iomem *port_mmio = ahci_port_base(ap);
657 struct ahci_host_priv *hpriv = ap->host->private_data;
658 u32 tmp;
659
660 /*
661 * On some controllers, stopping a port's DMA engine while the port
662 * is in ALPM state (partial or slumber) results in failures on
663 * subsequent DMA engine starts. For those controllers, put the
664 * port back in active state before stopping its DMA engine.
665 */
666 if ((hpriv->flags & AHCI_HFLAG_WAKE_BEFORE_STOP) &&
667 (ap->link.lpm_policy > ATA_LPM_MAX_POWER) &&
668 ahci_set_lpm(&ap->link, ATA_LPM_MAX_POWER, ATA_LPM_WAKE_ONLY)) {
669 dev_err(ap->host->dev, "Failed to wake up port before engine stop\n");
670 return -EIO;
671 }
672
673 tmp = readl(port_mmio + PORT_CMD);
674
675 /* check if the HBA is idle */
676 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
677 return 0;
678
679 /*
680 * Don't try to issue commands but return with ENODEV if the
681 * AHCI controller not available anymore (e.g. due to PCIe hot
682 * unplugging). Otherwise a 500ms delay for each port is added.
683 */
684 if (tmp == 0xffffffff) {
685 dev_err(ap->host->dev, "AHCI controller unavailable!\n");
686 return -ENODEV;
687 }
688
689 /* setting HBA to idle */
690 tmp &= ~PORT_CMD_START;
691 writel(tmp, port_mmio + PORT_CMD);
692
693 /* wait for engine to stop. This could be as long as 500 msec */
694 tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
695 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
696 if (tmp & PORT_CMD_LIST_ON)
697 return -EIO;
698
699 return 0;
700 }
701 EXPORT_SYMBOL_GPL(ahci_stop_engine);
702
ahci_start_fis_rx(struct ata_port * ap)703 void ahci_start_fis_rx(struct ata_port *ap)
704 {
705 void __iomem *port_mmio = ahci_port_base(ap);
706 struct ahci_host_priv *hpriv = ap->host->private_data;
707 struct ahci_port_priv *pp = ap->private_data;
708 u32 tmp;
709
710 /* set FIS registers */
711 if (hpriv->cap & HOST_CAP_64)
712 writel((pp->cmd_slot_dma >> 16) >> 16,
713 port_mmio + PORT_LST_ADDR_HI);
714 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
715
716 if (hpriv->cap & HOST_CAP_64)
717 writel((pp->rx_fis_dma >> 16) >> 16,
718 port_mmio + PORT_FIS_ADDR_HI);
719 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
720
721 /* enable FIS reception */
722 tmp = readl(port_mmio + PORT_CMD);
723 tmp |= PORT_CMD_FIS_RX;
724 writel(tmp, port_mmio + PORT_CMD);
725
726 /* flush */
727 readl(port_mmio + PORT_CMD);
728 }
729 EXPORT_SYMBOL_GPL(ahci_start_fis_rx);
730
ahci_stop_fis_rx(struct ata_port * ap)731 static int ahci_stop_fis_rx(struct ata_port *ap)
732 {
733 void __iomem *port_mmio = ahci_port_base(ap);
734 u32 tmp;
735
736 /* disable FIS reception */
737 tmp = readl(port_mmio + PORT_CMD);
738 tmp &= ~PORT_CMD_FIS_RX;
739 writel(tmp, port_mmio + PORT_CMD);
740
741 /* wait for completion, spec says 500ms, give it 1000 */
742 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
743 PORT_CMD_FIS_ON, 10, 1000);
744 if (tmp & PORT_CMD_FIS_ON)
745 return -EBUSY;
746
747 return 0;
748 }
749
ahci_power_up(struct ata_port * ap)750 static void ahci_power_up(struct ata_port *ap)
751 {
752 struct ahci_host_priv *hpriv = ap->host->private_data;
753 void __iomem *port_mmio = ahci_port_base(ap);
754 u32 cmd;
755
756 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
757
758 /* spin up device */
759 if (hpriv->cap & HOST_CAP_SSS) {
760 cmd |= PORT_CMD_SPIN_UP;
761 writel(cmd, port_mmio + PORT_CMD);
762 }
763
764 /* wake up link */
765 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
766 }
767
ahci_set_lpm(struct ata_link * link,enum ata_lpm_policy policy,unsigned int hints)768 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
769 unsigned int hints)
770 {
771 struct ata_port *ap = link->ap;
772 struct ahci_host_priv *hpriv = ap->host->private_data;
773 struct ahci_port_priv *pp = ap->private_data;
774 void __iomem *port_mmio = ahci_port_base(ap);
775
776 if (policy != ATA_LPM_MAX_POWER) {
777 /* wakeup flag only applies to the max power policy */
778 hints &= ~ATA_LPM_WAKE_ONLY;
779
780 /*
781 * Disable interrupts on Phy Ready. This keeps us from
782 * getting woken up due to spurious phy ready
783 * interrupts.
784 */
785 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
786 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
787
788 sata_link_scr_lpm(link, policy, false);
789 }
790
791 if (hpriv->cap & HOST_CAP_ALPM) {
792 u32 cmd = readl(port_mmio + PORT_CMD);
793
794 if (policy == ATA_LPM_MAX_POWER || !(hints & ATA_LPM_HIPM)) {
795 if (!(hints & ATA_LPM_WAKE_ONLY))
796 cmd &= ~(PORT_CMD_ASP | PORT_CMD_ALPE);
797 cmd |= PORT_CMD_ICC_ACTIVE;
798
799 writel(cmd, port_mmio + PORT_CMD);
800 readl(port_mmio + PORT_CMD);
801
802 /* wait 10ms to be sure we've come out of LPM state */
803 ata_msleep(ap, 10);
804
805 if (hints & ATA_LPM_WAKE_ONLY)
806 return 0;
807 } else {
808 cmd |= PORT_CMD_ALPE;
809 if (policy == ATA_LPM_MIN_POWER)
810 cmd |= PORT_CMD_ASP;
811 else if (policy == ATA_LPM_MIN_POWER_WITH_PARTIAL)
812 cmd &= ~PORT_CMD_ASP;
813
814 /* write out new cmd value */
815 writel(cmd, port_mmio + PORT_CMD);
816 }
817 }
818
819 /* set aggressive device sleep */
820 if ((hpriv->cap2 & HOST_CAP2_SDS) &&
821 (hpriv->cap2 & HOST_CAP2_SADM) &&
822 (link->device->flags & ATA_DFLAG_DEVSLP)) {
823 if (policy == ATA_LPM_MIN_POWER ||
824 policy == ATA_LPM_MIN_POWER_WITH_PARTIAL)
825 ahci_set_aggressive_devslp(ap, true);
826 else
827 ahci_set_aggressive_devslp(ap, false);
828 }
829
830 if (policy == ATA_LPM_MAX_POWER) {
831 sata_link_scr_lpm(link, policy, false);
832
833 /* turn PHYRDY IRQ back on */
834 pp->intr_mask |= PORT_IRQ_PHYRDY;
835 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
836 }
837
838 return 0;
839 }
840
841 #ifdef CONFIG_PM
ahci_power_down(struct ata_port * ap)842 static void ahci_power_down(struct ata_port *ap)
843 {
844 struct ahci_host_priv *hpriv = ap->host->private_data;
845 void __iomem *port_mmio = ahci_port_base(ap);
846 u32 cmd, scontrol;
847
848 if (!(hpriv->cap & HOST_CAP_SSS))
849 return;
850
851 /* put device into listen mode, first set PxSCTL.DET to 0 */
852 scontrol = readl(port_mmio + PORT_SCR_CTL);
853 scontrol &= ~0xf;
854 writel(scontrol, port_mmio + PORT_SCR_CTL);
855
856 /* then set PxCMD.SUD to 0 */
857 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
858 cmd &= ~PORT_CMD_SPIN_UP;
859 writel(cmd, port_mmio + PORT_CMD);
860 }
861 #endif
862
ahci_start_port(struct ata_port * ap)863 static void ahci_start_port(struct ata_port *ap)
864 {
865 struct ahci_host_priv *hpriv = ap->host->private_data;
866 struct ahci_port_priv *pp = ap->private_data;
867 struct ata_link *link;
868 struct ahci_em_priv *emp;
869 ssize_t rc;
870 int i;
871
872 /* enable FIS reception */
873 ahci_start_fis_rx(ap);
874
875 /* enable DMA */
876 if (!(hpriv->flags & AHCI_HFLAG_DELAY_ENGINE))
877 hpriv->start_engine(ap);
878
879 /* turn on LEDs */
880 if (ap->flags & ATA_FLAG_EM) {
881 ata_for_each_link(link, ap, EDGE) {
882 emp = &pp->em_priv[link->pmp];
883
884 /* EM Transmit bit maybe busy during init */
885 for (i = 0; i < EM_MAX_RETRY; i++) {
886 rc = ap->ops->transmit_led_message(ap,
887 emp->led_state,
888 4);
889 /*
890 * If busy, give a breather but do not
891 * release EH ownership by using msleep()
892 * instead of ata_msleep(). EM Transmit
893 * bit is busy for the whole host and
894 * releasing ownership will cause other
895 * ports to fail the same way.
896 */
897 if (rc == -EBUSY)
898 msleep(1);
899 else
900 break;
901 }
902 }
903 }
904
905 if (ap->flags & ATA_FLAG_SW_ACTIVITY)
906 ata_for_each_link(link, ap, EDGE)
907 ahci_init_sw_activity(link);
908
909 }
910
ahci_deinit_port(struct ata_port * ap,const char ** emsg)911 static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
912 {
913 int rc;
914 struct ahci_host_priv *hpriv = ap->host->private_data;
915
916 /* disable DMA */
917 rc = hpriv->stop_engine(ap);
918 if (rc) {
919 *emsg = "failed to stop engine";
920 return rc;
921 }
922
923 /* disable FIS reception */
924 rc = ahci_stop_fis_rx(ap);
925 if (rc) {
926 *emsg = "failed stop FIS RX";
927 return rc;
928 }
929
930 return 0;
931 }
932
ahci_reset_controller(struct ata_host * host)933 int ahci_reset_controller(struct ata_host *host)
934 {
935 struct ahci_host_priv *hpriv = host->private_data;
936 void __iomem *mmio = hpriv->mmio;
937 u32 tmp;
938
939 /* we must be in AHCI mode, before using anything
940 * AHCI-specific, such as HOST_RESET.
941 */
942 ahci_enable_ahci(mmio);
943
944 /* global controller reset */
945 if (!ahci_skip_host_reset) {
946 tmp = readl(mmio + HOST_CTL);
947 if ((tmp & HOST_RESET) == 0) {
948 writel(tmp | HOST_RESET, mmio + HOST_CTL);
949 readl(mmio + HOST_CTL); /* flush */
950 }
951
952 /*
953 * to perform host reset, OS should set HOST_RESET
954 * and poll until this bit is read to be "0".
955 * reset must complete within 1 second, or
956 * the hardware should be considered fried.
957 */
958 tmp = ata_wait_register(NULL, mmio + HOST_CTL, HOST_RESET,
959 HOST_RESET, 10, 1000);
960
961 if (tmp & HOST_RESET) {
962 dev_err(host->dev, "controller reset failed (0x%x)\n",
963 tmp);
964 return -EIO;
965 }
966
967 /* turn on AHCI mode */
968 ahci_enable_ahci(mmio);
969
970 /* Some registers might be cleared on reset. Restore
971 * initial values.
972 */
973 if (!(hpriv->flags & AHCI_HFLAG_NO_WRITE_TO_RO))
974 ahci_restore_initial_config(host);
975 } else
976 dev_info(host->dev, "skipping global host reset\n");
977
978 return 0;
979 }
980 EXPORT_SYMBOL_GPL(ahci_reset_controller);
981
ahci_sw_activity(struct ata_link * link)982 static void ahci_sw_activity(struct ata_link *link)
983 {
984 struct ata_port *ap = link->ap;
985 struct ahci_port_priv *pp = ap->private_data;
986 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
987
988 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY))
989 return;
990
991 emp->activity++;
992 if (!timer_pending(&emp->timer))
993 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));
994 }
995
ahci_sw_activity_blink(struct timer_list * t)996 static void ahci_sw_activity_blink(struct timer_list *t)
997 {
998 struct ahci_em_priv *emp = from_timer(emp, t, timer);
999 struct ata_link *link = emp->link;
1000 struct ata_port *ap = link->ap;
1001
1002 unsigned long led_message = emp->led_state;
1003 u32 activity_led_state;
1004 unsigned long flags;
1005
1006 led_message &= EM_MSG_LED_VALUE;
1007 led_message |= ap->port_no | (link->pmp << 8);
1008
1009 /* check to see if we've had activity. If so,
1010 * toggle state of LED and reset timer. If not,
1011 * turn LED to desired idle state.
1012 */
1013 spin_lock_irqsave(ap->lock, flags);
1014 if (emp->saved_activity != emp->activity) {
1015 emp->saved_activity = emp->activity;
1016 /* get the current LED state */
1017 activity_led_state = led_message & EM_MSG_LED_VALUE_ON;
1018
1019 if (activity_led_state)
1020 activity_led_state = 0;
1021 else
1022 activity_led_state = 1;
1023
1024 /* clear old state */
1025 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
1026
1027 /* toggle state */
1028 led_message |= (activity_led_state << 16);
1029 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100));
1030 } else {
1031 /* switch to idle */
1032 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
1033 if (emp->blink_policy == BLINK_OFF)
1034 led_message |= (1 << 16);
1035 }
1036 spin_unlock_irqrestore(ap->lock, flags);
1037 ap->ops->transmit_led_message(ap, led_message, 4);
1038 }
1039
ahci_init_sw_activity(struct ata_link * link)1040 static void ahci_init_sw_activity(struct ata_link *link)
1041 {
1042 struct ata_port *ap = link->ap;
1043 struct ahci_port_priv *pp = ap->private_data;
1044 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1045
1046 /* init activity stats, setup timer */
1047 emp->saved_activity = emp->activity = 0;
1048 emp->link = link;
1049 timer_setup(&emp->timer, ahci_sw_activity_blink, 0);
1050
1051 /* check our blink policy and set flag for link if it's enabled */
1052 if (emp->blink_policy)
1053 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1054 }
1055
ahci_reset_em(struct ata_host * host)1056 int ahci_reset_em(struct ata_host *host)
1057 {
1058 struct ahci_host_priv *hpriv = host->private_data;
1059 void __iomem *mmio = hpriv->mmio;
1060 u32 em_ctl;
1061
1062 em_ctl = readl(mmio + HOST_EM_CTL);
1063 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST))
1064 return -EINVAL;
1065
1066 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL);
1067 return 0;
1068 }
1069 EXPORT_SYMBOL_GPL(ahci_reset_em);
1070
ahci_transmit_led_message(struct ata_port * ap,u32 state,ssize_t size)1071 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
1072 ssize_t size)
1073 {
1074 struct ahci_host_priv *hpriv = ap->host->private_data;
1075 struct ahci_port_priv *pp = ap->private_data;
1076 void __iomem *mmio = hpriv->mmio;
1077 u32 em_ctl;
1078 u32 message[] = {0, 0};
1079 unsigned long flags;
1080 int pmp;
1081 struct ahci_em_priv *emp;
1082
1083 /* get the slot number from the message */
1084 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1085 if (pmp < EM_MAX_SLOTS)
1086 emp = &pp->em_priv[pmp];
1087 else
1088 return -EINVAL;
1089
1090 ahci_rpm_get_port(ap);
1091 spin_lock_irqsave(ap->lock, flags);
1092
1093 /*
1094 * if we are still busy transmitting a previous message,
1095 * do not allow
1096 */
1097 em_ctl = readl(mmio + HOST_EM_CTL);
1098 if (em_ctl & EM_CTL_TM) {
1099 spin_unlock_irqrestore(ap->lock, flags);
1100 ahci_rpm_put_port(ap);
1101 return -EBUSY;
1102 }
1103
1104 if (hpriv->em_msg_type & EM_MSG_TYPE_LED) {
1105 /*
1106 * create message header - this is all zero except for
1107 * the message size, which is 4 bytes.
1108 */
1109 message[0] |= (4 << 8);
1110
1111 /* ignore 0:4 of byte zero, fill in port info yourself */
1112 message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no);
1113
1114 /* write message to EM_LOC */
1115 writel(message[0], mmio + hpriv->em_loc);
1116 writel(message[1], mmio + hpriv->em_loc+4);
1117
1118 /*
1119 * tell hardware to transmit the message
1120 */
1121 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
1122 }
1123
1124 /* save off new led state for port/slot */
1125 emp->led_state = state;
1126
1127 spin_unlock_irqrestore(ap->lock, flags);
1128 ahci_rpm_put_port(ap);
1129
1130 return size;
1131 }
1132
ahci_led_show(struct ata_port * ap,char * buf)1133 static ssize_t ahci_led_show(struct ata_port *ap, char *buf)
1134 {
1135 struct ahci_port_priv *pp = ap->private_data;
1136 struct ata_link *link;
1137 struct ahci_em_priv *emp;
1138 int rc = 0;
1139
1140 ata_for_each_link(link, ap, EDGE) {
1141 emp = &pp->em_priv[link->pmp];
1142 rc += sprintf(buf, "%lx\n", emp->led_state);
1143 }
1144 return rc;
1145 }
1146
ahci_led_store(struct ata_port * ap,const char * buf,size_t size)1147 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
1148 size_t size)
1149 {
1150 unsigned int state;
1151 int pmp;
1152 struct ahci_port_priv *pp = ap->private_data;
1153 struct ahci_em_priv *emp;
1154
1155 if (kstrtouint(buf, 0, &state) < 0)
1156 return -EINVAL;
1157
1158 /* get the slot number from the message */
1159 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1160 if (pmp < EM_MAX_SLOTS) {
1161 pmp = array_index_nospec(pmp, EM_MAX_SLOTS);
1162 emp = &pp->em_priv[pmp];
1163 } else {
1164 return -EINVAL;
1165 }
1166
1167 /* mask off the activity bits if we are in sw_activity
1168 * mode, user should turn off sw_activity before setting
1169 * activity led through em_message
1170 */
1171 if (emp->blink_policy)
1172 state &= ~EM_MSG_LED_VALUE_ACTIVITY;
1173
1174 return ap->ops->transmit_led_message(ap, state, size);
1175 }
1176
ahci_activity_store(struct ata_device * dev,enum sw_activity val)1177 static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val)
1178 {
1179 struct ata_link *link = dev->link;
1180 struct ata_port *ap = link->ap;
1181 struct ahci_port_priv *pp = ap->private_data;
1182 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1183 u32 port_led_state = emp->led_state;
1184
1185 /* save the desired Activity LED behavior */
1186 if (val == OFF) {
1187 /* clear LFLAG */
1188 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY);
1189
1190 /* set the LED to OFF */
1191 port_led_state &= EM_MSG_LED_VALUE_OFF;
1192 port_led_state |= (ap->port_no | (link->pmp << 8));
1193 ap->ops->transmit_led_message(ap, port_led_state, 4);
1194 } else {
1195 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1196 if (val == BLINK_OFF) {
1197 /* set LED to ON for idle */
1198 port_led_state &= EM_MSG_LED_VALUE_OFF;
1199 port_led_state |= (ap->port_no | (link->pmp << 8));
1200 port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */
1201 ap->ops->transmit_led_message(ap, port_led_state, 4);
1202 }
1203 }
1204 emp->blink_policy = val;
1205 return 0;
1206 }
1207
ahci_activity_show(struct ata_device * dev,char * buf)1208 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
1209 {
1210 struct ata_link *link = dev->link;
1211 struct ata_port *ap = link->ap;
1212 struct ahci_port_priv *pp = ap->private_data;
1213 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1214
1215 /* display the saved value of activity behavior for this
1216 * disk.
1217 */
1218 return sprintf(buf, "%d\n", emp->blink_policy);
1219 }
1220
ahci_port_init(struct device * dev,struct ata_port * ap,int port_no,void __iomem * mmio,void __iomem * port_mmio)1221 static void ahci_port_init(struct device *dev, struct ata_port *ap,
1222 int port_no, void __iomem *mmio,
1223 void __iomem *port_mmio)
1224 {
1225 struct ahci_host_priv *hpriv = ap->host->private_data;
1226 const char *emsg = NULL;
1227 int rc;
1228 u32 tmp;
1229
1230 /* make sure port is not active */
1231 rc = ahci_deinit_port(ap, &emsg);
1232 if (rc)
1233 dev_warn(dev, "%s (%d)\n", emsg, rc);
1234
1235 /* clear SError */
1236 tmp = readl(port_mmio + PORT_SCR_ERR);
1237 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1238 writel(tmp, port_mmio + PORT_SCR_ERR);
1239
1240 /* clear port IRQ */
1241 tmp = readl(port_mmio + PORT_IRQ_STAT);
1242 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1243 if (tmp)
1244 writel(tmp, port_mmio + PORT_IRQ_STAT);
1245
1246 writel(1 << port_no, mmio + HOST_IRQ_STAT);
1247
1248 /* mark esata ports */
1249 tmp = readl(port_mmio + PORT_CMD);
1250 if ((tmp & PORT_CMD_ESP) && (hpriv->cap & HOST_CAP_SXS))
1251 ap->pflags |= ATA_PFLAG_EXTERNAL;
1252 }
1253
ahci_init_controller(struct ata_host * host)1254 void ahci_init_controller(struct ata_host *host)
1255 {
1256 struct ahci_host_priv *hpriv = host->private_data;
1257 void __iomem *mmio = hpriv->mmio;
1258 int i;
1259 void __iomem *port_mmio;
1260 u32 tmp;
1261
1262 for (i = 0; i < host->n_ports; i++) {
1263 struct ata_port *ap = host->ports[i];
1264
1265 port_mmio = ahci_port_base(ap);
1266 if (ata_port_is_dummy(ap))
1267 continue;
1268
1269 ahci_port_init(host->dev, ap, i, mmio, port_mmio);
1270 }
1271
1272 tmp = readl(mmio + HOST_CTL);
1273 VPRINTK("HOST_CTL 0x%x\n", tmp);
1274 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1275 tmp = readl(mmio + HOST_CTL);
1276 VPRINTK("HOST_CTL 0x%x\n", tmp);
1277 }
1278 EXPORT_SYMBOL_GPL(ahci_init_controller);
1279
ahci_dev_config(struct ata_device * dev)1280 static void ahci_dev_config(struct ata_device *dev)
1281 {
1282 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1283
1284 if (hpriv->flags & AHCI_HFLAG_SECT255) {
1285 dev->max_sectors = 255;
1286 ata_dev_info(dev,
1287 "SB600 AHCI: limiting to 255 sectors per cmd\n");
1288 }
1289 }
1290
ahci_dev_classify(struct ata_port * ap)1291 unsigned int ahci_dev_classify(struct ata_port *ap)
1292 {
1293 void __iomem *port_mmio = ahci_port_base(ap);
1294 struct ata_taskfile tf;
1295 u32 tmp;
1296
1297 tmp = readl(port_mmio + PORT_SIG);
1298 tf.lbah = (tmp >> 24) & 0xff;
1299 tf.lbam = (tmp >> 16) & 0xff;
1300 tf.lbal = (tmp >> 8) & 0xff;
1301 tf.nsect = (tmp) & 0xff;
1302
1303 return ata_dev_classify(&tf);
1304 }
1305 EXPORT_SYMBOL_GPL(ahci_dev_classify);
1306
ahci_fill_cmd_slot(struct ahci_port_priv * pp,unsigned int tag,u32 opts)1307 void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1308 u32 opts)
1309 {
1310 dma_addr_t cmd_tbl_dma;
1311
1312 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1313
1314 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1315 pp->cmd_slot[tag].status = 0;
1316 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1317 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
1318 }
1319 EXPORT_SYMBOL_GPL(ahci_fill_cmd_slot);
1320
ahci_kick_engine(struct ata_port * ap)1321 int ahci_kick_engine(struct ata_port *ap)
1322 {
1323 void __iomem *port_mmio = ahci_port_base(ap);
1324 struct ahci_host_priv *hpriv = ap->host->private_data;
1325 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1326 u32 tmp;
1327 int busy, rc;
1328
1329 /* stop engine */
1330 rc = hpriv->stop_engine(ap);
1331 if (rc)
1332 goto out_restart;
1333
1334 /* need to do CLO?
1335 * always do CLO if PMP is attached (AHCI-1.3 9.2)
1336 */
1337 busy = status & (ATA_BUSY | ATA_DRQ);
1338 if (!busy && !sata_pmp_attached(ap)) {
1339 rc = 0;
1340 goto out_restart;
1341 }
1342
1343 if (!(hpriv->cap & HOST_CAP_CLO)) {
1344 rc = -EOPNOTSUPP;
1345 goto out_restart;
1346 }
1347
1348 /* perform CLO */
1349 tmp = readl(port_mmio + PORT_CMD);
1350 tmp |= PORT_CMD_CLO;
1351 writel(tmp, port_mmio + PORT_CMD);
1352
1353 rc = 0;
1354 tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
1355 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1356 if (tmp & PORT_CMD_CLO)
1357 rc = -EIO;
1358
1359 /* restart engine */
1360 out_restart:
1361 hpriv->start_engine(ap);
1362 return rc;
1363 }
1364 EXPORT_SYMBOL_GPL(ahci_kick_engine);
1365
ahci_exec_polled_cmd(struct ata_port * ap,int pmp,struct ata_taskfile * tf,int is_cmd,u16 flags,unsigned long timeout_msec)1366 static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1367 struct ata_taskfile *tf, int is_cmd, u16 flags,
1368 unsigned long timeout_msec)
1369 {
1370 const u32 cmd_fis_len = 5; /* five dwords */
1371 struct ahci_port_priv *pp = ap->private_data;
1372 void __iomem *port_mmio = ahci_port_base(ap);
1373 u8 *fis = pp->cmd_tbl;
1374 u32 tmp;
1375
1376 /* prep the command */
1377 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1378 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1379
1380 /* set port value for softreset of Port Multiplier */
1381 if (pp->fbs_enabled && pp->fbs_last_dev != pmp) {
1382 tmp = readl(port_mmio + PORT_FBS);
1383 tmp &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
1384 tmp |= pmp << PORT_FBS_DEV_OFFSET;
1385 writel(tmp, port_mmio + PORT_FBS);
1386 pp->fbs_last_dev = pmp;
1387 }
1388
1389 /* issue & wait */
1390 writel(1, port_mmio + PORT_CMD_ISSUE);
1391
1392 if (timeout_msec) {
1393 tmp = ata_wait_register(ap, port_mmio + PORT_CMD_ISSUE,
1394 0x1, 0x1, 1, timeout_msec);
1395 if (tmp & 0x1) {
1396 ahci_kick_engine(ap);
1397 return -EBUSY;
1398 }
1399 } else
1400 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1401
1402 return 0;
1403 }
1404
ahci_do_softreset(struct ata_link * link,unsigned int * class,int pmp,unsigned long deadline,int (* check_ready)(struct ata_link * link))1405 int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1406 int pmp, unsigned long deadline,
1407 int (*check_ready)(struct ata_link *link))
1408 {
1409 struct ata_port *ap = link->ap;
1410 struct ahci_host_priv *hpriv = ap->host->private_data;
1411 struct ahci_port_priv *pp = ap->private_data;
1412 const char *reason = NULL;
1413 unsigned long now, msecs;
1414 struct ata_taskfile tf;
1415 bool fbs_disabled = false;
1416 int rc;
1417
1418 DPRINTK("ENTER\n");
1419
1420 /* prepare for SRST (AHCI-1.1 10.4.1) */
1421 rc = ahci_kick_engine(ap);
1422 if (rc && rc != -EOPNOTSUPP)
1423 ata_link_warn(link, "failed to reset engine (errno=%d)\n", rc);
1424
1425 /*
1426 * According to AHCI-1.2 9.3.9: if FBS is enable, software shall
1427 * clear PxFBS.EN to '0' prior to issuing software reset to devices
1428 * that is attached to port multiplier.
1429 */
1430 if (!ata_is_host_link(link) && pp->fbs_enabled) {
1431 ahci_disable_fbs(ap);
1432 fbs_disabled = true;
1433 }
1434
1435 ata_tf_init(link->device, &tf);
1436
1437 /* issue the first H2D Register FIS */
1438 msecs = 0;
1439 now = jiffies;
1440 if (time_after(deadline, now))
1441 msecs = jiffies_to_msecs(deadline - now);
1442
1443 tf.ctl |= ATA_SRST;
1444 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1445 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1446 rc = -EIO;
1447 reason = "1st FIS failed";
1448 goto fail;
1449 }
1450
1451 /* spec says at least 5us, but be generous and sleep for 1ms */
1452 ata_msleep(ap, 1);
1453
1454 /* issue the second H2D Register FIS */
1455 tf.ctl &= ~ATA_SRST;
1456 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1457
1458 /* wait for link to become ready */
1459 rc = ata_wait_after_reset(link, deadline, check_ready);
1460 if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) {
1461 /*
1462 * Workaround for cases where link online status can't
1463 * be trusted. Treat device readiness timeout as link
1464 * offline.
1465 */
1466 ata_link_info(link, "device not ready, treating as offline\n");
1467 *class = ATA_DEV_NONE;
1468 } else if (rc) {
1469 /* link occupied, -ENODEV too is an error */
1470 reason = "device not ready";
1471 goto fail;
1472 } else
1473 *class = ahci_dev_classify(ap);
1474
1475 /* re-enable FBS if disabled before */
1476 if (fbs_disabled)
1477 ahci_enable_fbs(ap);
1478
1479 DPRINTK("EXIT, class=%u\n", *class);
1480 return 0;
1481
1482 fail:
1483 ata_link_err(link, "softreset failed (%s)\n", reason);
1484 return rc;
1485 }
1486
ahci_check_ready(struct ata_link * link)1487 int ahci_check_ready(struct ata_link *link)
1488 {
1489 void __iomem *port_mmio = ahci_port_base(link->ap);
1490 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1491
1492 return ata_check_ready(status);
1493 }
1494 EXPORT_SYMBOL_GPL(ahci_check_ready);
1495
ahci_softreset(struct ata_link * link,unsigned int * class,unsigned long deadline)1496 static int ahci_softreset(struct ata_link *link, unsigned int *class,
1497 unsigned long deadline)
1498 {
1499 int pmp = sata_srst_pmp(link);
1500
1501 DPRINTK("ENTER\n");
1502
1503 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
1504 }
1505 EXPORT_SYMBOL_GPL(ahci_do_softreset);
1506
ahci_bad_pmp_check_ready(struct ata_link * link)1507 static int ahci_bad_pmp_check_ready(struct ata_link *link)
1508 {
1509 void __iomem *port_mmio = ahci_port_base(link->ap);
1510 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1511 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
1512
1513 /*
1514 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
1515 * which can save timeout delay.
1516 */
1517 if (irq_status & PORT_IRQ_BAD_PMP)
1518 return -EIO;
1519
1520 return ata_check_ready(status);
1521 }
1522
ahci_pmp_retry_softreset(struct ata_link * link,unsigned int * class,unsigned long deadline)1523 static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
1524 unsigned long deadline)
1525 {
1526 struct ata_port *ap = link->ap;
1527 void __iomem *port_mmio = ahci_port_base(ap);
1528 int pmp = sata_srst_pmp(link);
1529 int rc;
1530 u32 irq_sts;
1531
1532 DPRINTK("ENTER\n");
1533
1534 rc = ahci_do_softreset(link, class, pmp, deadline,
1535 ahci_bad_pmp_check_ready);
1536
1537 /*
1538 * Soft reset fails with IPMS set when PMP is enabled but
1539 * SATA HDD/ODD is connected to SATA port, do soft reset
1540 * again to port 0.
1541 */
1542 if (rc == -EIO) {
1543 irq_sts = readl(port_mmio + PORT_IRQ_STAT);
1544 if (irq_sts & PORT_IRQ_BAD_PMP) {
1545 ata_link_warn(link,
1546 "applying PMP SRST workaround "
1547 "and retrying\n");
1548 rc = ahci_do_softreset(link, class, 0, deadline,
1549 ahci_check_ready);
1550 }
1551 }
1552
1553 return rc;
1554 }
1555
ahci_do_hardreset(struct ata_link * link,unsigned int * class,unsigned long deadline,bool * online)1556 int ahci_do_hardreset(struct ata_link *link, unsigned int *class,
1557 unsigned long deadline, bool *online)
1558 {
1559 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
1560 struct ata_port *ap = link->ap;
1561 struct ahci_port_priv *pp = ap->private_data;
1562 struct ahci_host_priv *hpriv = ap->host->private_data;
1563 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1564 struct ata_taskfile tf;
1565 int rc;
1566
1567 DPRINTK("ENTER\n");
1568
1569 hpriv->stop_engine(ap);
1570
1571 /* clear D2H reception area to properly wait for D2H FIS */
1572 ata_tf_init(link->device, &tf);
1573 tf.command = ATA_BUSY;
1574 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1575
1576 rc = sata_link_hardreset(link, timing, deadline, online,
1577 ahci_check_ready);
1578
1579 hpriv->start_engine(ap);
1580
1581 if (*online)
1582 *class = ahci_dev_classify(ap);
1583
1584 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1585 return rc;
1586 }
1587 EXPORT_SYMBOL_GPL(ahci_do_hardreset);
1588
ahci_hardreset(struct ata_link * link,unsigned int * class,unsigned long deadline)1589 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1590 unsigned long deadline)
1591 {
1592 bool online;
1593
1594 return ahci_do_hardreset(link, class, deadline, &online);
1595 }
1596
ahci_postreset(struct ata_link * link,unsigned int * class)1597 static void ahci_postreset(struct ata_link *link, unsigned int *class)
1598 {
1599 struct ata_port *ap = link->ap;
1600 void __iomem *port_mmio = ahci_port_base(ap);
1601 u32 new_tmp, tmp;
1602
1603 ata_std_postreset(link, class);
1604
1605 /* Make sure port's ATAPI bit is set appropriately */
1606 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1607 if (*class == ATA_DEV_ATAPI)
1608 new_tmp |= PORT_CMD_ATAPI;
1609 else
1610 new_tmp &= ~PORT_CMD_ATAPI;
1611 if (new_tmp != tmp) {
1612 writel(new_tmp, port_mmio + PORT_CMD);
1613 readl(port_mmio + PORT_CMD); /* flush */
1614 }
1615 }
1616
ahci_fill_sg(struct ata_queued_cmd * qc,void * cmd_tbl)1617 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1618 {
1619 struct scatterlist *sg;
1620 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1621 unsigned int si;
1622
1623 VPRINTK("ENTER\n");
1624
1625 /*
1626 * Next, the S/G list.
1627 */
1628 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1629 dma_addr_t addr = sg_dma_address(sg);
1630 u32 sg_len = sg_dma_len(sg);
1631
1632 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1633 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1634 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
1635 }
1636
1637 return si;
1638 }
1639
ahci_pmp_qc_defer(struct ata_queued_cmd * qc)1640 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc)
1641 {
1642 struct ata_port *ap = qc->ap;
1643 struct ahci_port_priv *pp = ap->private_data;
1644
1645 if (!sata_pmp_attached(ap) || pp->fbs_enabled)
1646 return ata_std_qc_defer(qc);
1647 else
1648 return sata_pmp_qc_defer_cmd_switch(qc);
1649 }
1650
ahci_qc_prep(struct ata_queued_cmd * qc)1651 static enum ata_completion_errors ahci_qc_prep(struct ata_queued_cmd *qc)
1652 {
1653 struct ata_port *ap = qc->ap;
1654 struct ahci_port_priv *pp = ap->private_data;
1655 int is_atapi = ata_is_atapi(qc->tf.protocol);
1656 void *cmd_tbl;
1657 u32 opts;
1658 const u32 cmd_fis_len = 5; /* five dwords */
1659 unsigned int n_elem;
1660
1661 /*
1662 * Fill in command table information. First, the header,
1663 * a SATA Register - Host to Device command FIS.
1664 */
1665 cmd_tbl = pp->cmd_tbl + qc->hw_tag * AHCI_CMD_TBL_SZ;
1666
1667 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
1668 if (is_atapi) {
1669 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1670 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1671 }
1672
1673 n_elem = 0;
1674 if (qc->flags & ATA_QCFLAG_DMAMAP)
1675 n_elem = ahci_fill_sg(qc, cmd_tbl);
1676
1677 /*
1678 * Fill in command slot information.
1679 */
1680 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
1681 if (qc->tf.flags & ATA_TFLAG_WRITE)
1682 opts |= AHCI_CMD_WRITE;
1683 if (is_atapi)
1684 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1685
1686 ahci_fill_cmd_slot(pp, qc->hw_tag, opts);
1687
1688 return AC_ERR_OK;
1689 }
1690
ahci_fbs_dec_intr(struct ata_port * ap)1691 static void ahci_fbs_dec_intr(struct ata_port *ap)
1692 {
1693 struct ahci_port_priv *pp = ap->private_data;
1694 void __iomem *port_mmio = ahci_port_base(ap);
1695 u32 fbs = readl(port_mmio + PORT_FBS);
1696 int retries = 3;
1697
1698 DPRINTK("ENTER\n");
1699 BUG_ON(!pp->fbs_enabled);
1700
1701 /* time to wait for DEC is not specified by AHCI spec,
1702 * add a retry loop for safety.
1703 */
1704 writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS);
1705 fbs = readl(port_mmio + PORT_FBS);
1706 while ((fbs & PORT_FBS_DEC) && retries--) {
1707 udelay(1);
1708 fbs = readl(port_mmio + PORT_FBS);
1709 }
1710
1711 if (fbs & PORT_FBS_DEC)
1712 dev_err(ap->host->dev, "failed to clear device error\n");
1713 }
1714
ahci_error_intr(struct ata_port * ap,u32 irq_stat)1715 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1716 {
1717 struct ahci_host_priv *hpriv = ap->host->private_data;
1718 struct ahci_port_priv *pp = ap->private_data;
1719 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1720 struct ata_link *link = NULL;
1721 struct ata_queued_cmd *active_qc;
1722 struct ata_eh_info *active_ehi;
1723 bool fbs_need_dec = false;
1724 u32 serror;
1725
1726 /* determine active link with error */
1727 if (pp->fbs_enabled) {
1728 void __iomem *port_mmio = ahci_port_base(ap);
1729 u32 fbs = readl(port_mmio + PORT_FBS);
1730 int pmp = fbs >> PORT_FBS_DWE_OFFSET;
1731
1732 if ((fbs & PORT_FBS_SDE) && (pmp < ap->nr_pmp_links)) {
1733 link = &ap->pmp_link[pmp];
1734 fbs_need_dec = true;
1735 }
1736
1737 } else
1738 ata_for_each_link(link, ap, EDGE)
1739 if (ata_link_active(link))
1740 break;
1741
1742 if (!link)
1743 link = &ap->link;
1744
1745 active_qc = ata_qc_from_tag(ap, link->active_tag);
1746 active_ehi = &link->eh_info;
1747
1748 /* record irq stat */
1749 ata_ehi_clear_desc(host_ehi);
1750 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1751
1752 /* AHCI needs SError cleared; otherwise, it might lock up */
1753 ahci_scr_read(&ap->link, SCR_ERROR, &serror);
1754 ahci_scr_write(&ap->link, SCR_ERROR, serror);
1755 host_ehi->serror |= serror;
1756
1757 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1758 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
1759 irq_stat &= ~PORT_IRQ_IF_ERR;
1760
1761 if (irq_stat & PORT_IRQ_TF_ERR) {
1762 /* If qc is active, charge it; otherwise, the active
1763 * link. There's no active qc on NCQ errors. It will
1764 * be determined by EH by reading log page 10h.
1765 */
1766 if (active_qc)
1767 active_qc->err_mask |= AC_ERR_DEV;
1768 else
1769 active_ehi->err_mask |= AC_ERR_DEV;
1770
1771 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
1772 host_ehi->serror &= ~SERR_INTERNAL;
1773 }
1774
1775 if (irq_stat & PORT_IRQ_UNK_FIS) {
1776 u32 *unk = pp->rx_fis + RX_FIS_UNK;
1777
1778 active_ehi->err_mask |= AC_ERR_HSM;
1779 active_ehi->action |= ATA_EH_RESET;
1780 ata_ehi_push_desc(active_ehi,
1781 "unknown FIS %08x %08x %08x %08x" ,
1782 unk[0], unk[1], unk[2], unk[3]);
1783 }
1784
1785 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
1786 active_ehi->err_mask |= AC_ERR_HSM;
1787 active_ehi->action |= ATA_EH_RESET;
1788 ata_ehi_push_desc(active_ehi, "incorrect PMP");
1789 }
1790
1791 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1792 host_ehi->err_mask |= AC_ERR_HOST_BUS;
1793 host_ehi->action |= ATA_EH_RESET;
1794 ata_ehi_push_desc(host_ehi, "host bus error");
1795 }
1796
1797 if (irq_stat & PORT_IRQ_IF_ERR) {
1798 if (fbs_need_dec)
1799 active_ehi->err_mask |= AC_ERR_DEV;
1800 else {
1801 host_ehi->err_mask |= AC_ERR_ATA_BUS;
1802 host_ehi->action |= ATA_EH_RESET;
1803 }
1804
1805 ata_ehi_push_desc(host_ehi, "interface fatal error");
1806 }
1807
1808 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1809 ata_ehi_hotplugged(host_ehi);
1810 ata_ehi_push_desc(host_ehi, "%s",
1811 irq_stat & PORT_IRQ_CONNECT ?
1812 "connection status changed" : "PHY RDY changed");
1813 }
1814
1815 /* okay, let's hand over to EH */
1816
1817 if (irq_stat & PORT_IRQ_FREEZE)
1818 ata_port_freeze(ap);
1819 else if (fbs_need_dec) {
1820 ata_link_abort(link);
1821 ahci_fbs_dec_intr(ap);
1822 } else
1823 ata_port_abort(ap);
1824 }
1825
ahci_handle_port_interrupt(struct ata_port * ap,void __iomem * port_mmio,u32 status)1826 static void ahci_handle_port_interrupt(struct ata_port *ap,
1827 void __iomem *port_mmio, u32 status)
1828 {
1829 struct ata_eh_info *ehi = &ap->link.eh_info;
1830 struct ahci_port_priv *pp = ap->private_data;
1831 struct ahci_host_priv *hpriv = ap->host->private_data;
1832 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
1833 u32 qc_active = 0;
1834 int rc;
1835
1836 /* ignore BAD_PMP while resetting */
1837 if (unlikely(resetting))
1838 status &= ~PORT_IRQ_BAD_PMP;
1839
1840 if (sata_lpm_ignore_phy_events(&ap->link)) {
1841 status &= ~PORT_IRQ_PHYRDY;
1842 ahci_scr_write(&ap->link, SCR_ERROR, SERR_PHYRDY_CHG);
1843 }
1844
1845 if (unlikely(status & PORT_IRQ_ERROR)) {
1846 ahci_error_intr(ap, status);
1847 return;
1848 }
1849
1850 if (status & PORT_IRQ_SDB_FIS) {
1851 /* If SNotification is available, leave notification
1852 * handling to sata_async_notification(). If not,
1853 * emulate it by snooping SDB FIS RX area.
1854 *
1855 * Snooping FIS RX area is probably cheaper than
1856 * poking SNotification but some constrollers which
1857 * implement SNotification, ICH9 for example, don't
1858 * store AN SDB FIS into receive area.
1859 */
1860 if (hpriv->cap & HOST_CAP_SNTF)
1861 sata_async_notification(ap);
1862 else {
1863 /* If the 'N' bit in word 0 of the FIS is set,
1864 * we just received asynchronous notification.
1865 * Tell libata about it.
1866 *
1867 * Lack of SNotification should not appear in
1868 * ahci 1.2, so the workaround is unnecessary
1869 * when FBS is enabled.
1870 */
1871 if (pp->fbs_enabled)
1872 WARN_ON_ONCE(1);
1873 else {
1874 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1875 u32 f0 = le32_to_cpu(f[0]);
1876 if (f0 & (1 << 15))
1877 sata_async_notification(ap);
1878 }
1879 }
1880 }
1881
1882 /* pp->active_link is not reliable once FBS is enabled, both
1883 * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because
1884 * NCQ and non-NCQ commands may be in flight at the same time.
1885 */
1886 if (pp->fbs_enabled) {
1887 if (ap->qc_active) {
1888 qc_active = readl(port_mmio + PORT_SCR_ACT);
1889 qc_active |= readl(port_mmio + PORT_CMD_ISSUE);
1890 }
1891 } else {
1892 /* pp->active_link is valid iff any command is in flight */
1893 if (ap->qc_active && pp->active_link->sactive)
1894 qc_active = readl(port_mmio + PORT_SCR_ACT);
1895 else
1896 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1897 }
1898
1899
1900 rc = ata_qc_complete_multiple(ap, qc_active);
1901
1902 /* while resetting, invalid completions are expected */
1903 if (unlikely(rc < 0 && !resetting)) {
1904 ehi->err_mask |= AC_ERR_HSM;
1905 ehi->action |= ATA_EH_RESET;
1906 ata_port_freeze(ap);
1907 }
1908 }
1909
ahci_port_intr(struct ata_port * ap)1910 static void ahci_port_intr(struct ata_port *ap)
1911 {
1912 void __iomem *port_mmio = ahci_port_base(ap);
1913 u32 status;
1914
1915 status = readl(port_mmio + PORT_IRQ_STAT);
1916 writel(status, port_mmio + PORT_IRQ_STAT);
1917
1918 ahci_handle_port_interrupt(ap, port_mmio, status);
1919 }
1920
ahci_multi_irqs_intr_hard(int irq,void * dev_instance)1921 static irqreturn_t ahci_multi_irqs_intr_hard(int irq, void *dev_instance)
1922 {
1923 struct ata_port *ap = dev_instance;
1924 void __iomem *port_mmio = ahci_port_base(ap);
1925 u32 status;
1926
1927 VPRINTK("ENTER\n");
1928
1929 status = readl(port_mmio + PORT_IRQ_STAT);
1930 writel(status, port_mmio + PORT_IRQ_STAT);
1931
1932 spin_lock(ap->lock);
1933 ahci_handle_port_interrupt(ap, port_mmio, status);
1934 spin_unlock(ap->lock);
1935
1936 VPRINTK("EXIT\n");
1937
1938 return IRQ_HANDLED;
1939 }
1940
ahci_handle_port_intr(struct ata_host * host,u32 irq_masked)1941 u32 ahci_handle_port_intr(struct ata_host *host, u32 irq_masked)
1942 {
1943 unsigned int i, handled = 0;
1944
1945 for (i = 0; i < host->n_ports; i++) {
1946 struct ata_port *ap;
1947
1948 if (!(irq_masked & (1 << i)))
1949 continue;
1950
1951 ap = host->ports[i];
1952 if (ap) {
1953 ahci_port_intr(ap);
1954 VPRINTK("port %u\n", i);
1955 } else {
1956 VPRINTK("port %u (no irq)\n", i);
1957 if (ata_ratelimit())
1958 dev_warn(host->dev,
1959 "interrupt on disabled port %u\n", i);
1960 }
1961
1962 handled = 1;
1963 }
1964
1965 return handled;
1966 }
1967 EXPORT_SYMBOL_GPL(ahci_handle_port_intr);
1968
ahci_single_level_irq_intr(int irq,void * dev_instance)1969 static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance)
1970 {
1971 struct ata_host *host = dev_instance;
1972 struct ahci_host_priv *hpriv;
1973 unsigned int rc = 0;
1974 void __iomem *mmio;
1975 u32 irq_stat, irq_masked;
1976
1977 VPRINTK("ENTER\n");
1978
1979 hpriv = host->private_data;
1980 mmio = hpriv->mmio;
1981
1982 /* sigh. 0xffffffff is a valid return from h/w */
1983 irq_stat = readl(mmio + HOST_IRQ_STAT);
1984 if (!irq_stat)
1985 return IRQ_NONE;
1986
1987 irq_masked = irq_stat & hpriv->port_map;
1988
1989 spin_lock(&host->lock);
1990
1991 rc = ahci_handle_port_intr(host, irq_masked);
1992
1993 /* HOST_IRQ_STAT behaves as level triggered latch meaning that
1994 * it should be cleared after all the port events are cleared;
1995 * otherwise, it will raise a spurious interrupt after each
1996 * valid one. Please read section 10.6.2 of ahci 1.1 for more
1997 * information.
1998 *
1999 * Also, use the unmasked value to clear interrupt as spurious
2000 * pending event on a dummy port might cause screaming IRQ.
2001 */
2002 writel(irq_stat, mmio + HOST_IRQ_STAT);
2003
2004 spin_unlock(&host->lock);
2005
2006 VPRINTK("EXIT\n");
2007
2008 return IRQ_RETVAL(rc);
2009 }
2010
ahci_qc_issue(struct ata_queued_cmd * qc)2011 unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
2012 {
2013 struct ata_port *ap = qc->ap;
2014 void __iomem *port_mmio = ahci_port_base(ap);
2015 struct ahci_port_priv *pp = ap->private_data;
2016
2017 /* Keep track of the currently active link. It will be used
2018 * in completion path to determine whether NCQ phase is in
2019 * progress.
2020 */
2021 pp->active_link = qc->dev->link;
2022
2023 if (ata_is_ncq(qc->tf.protocol))
2024 writel(1 << qc->hw_tag, port_mmio + PORT_SCR_ACT);
2025
2026 if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) {
2027 u32 fbs = readl(port_mmio + PORT_FBS);
2028 fbs &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
2029 fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET;
2030 writel(fbs, port_mmio + PORT_FBS);
2031 pp->fbs_last_dev = qc->dev->link->pmp;
2032 }
2033
2034 writel(1 << qc->hw_tag, port_mmio + PORT_CMD_ISSUE);
2035
2036 ahci_sw_activity(qc->dev->link);
2037
2038 return 0;
2039 }
2040 EXPORT_SYMBOL_GPL(ahci_qc_issue);
2041
ahci_qc_fill_rtf(struct ata_queued_cmd * qc)2042 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
2043 {
2044 struct ahci_port_priv *pp = qc->ap->private_data;
2045 u8 *rx_fis = pp->rx_fis;
2046
2047 if (pp->fbs_enabled)
2048 rx_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ;
2049
2050 /*
2051 * After a successful execution of an ATA PIO data-in command,
2052 * the device doesn't send D2H Reg FIS to update the TF and
2053 * the host should take TF and E_Status from the preceding PIO
2054 * Setup FIS.
2055 */
2056 if (qc->tf.protocol == ATA_PROT_PIO && qc->dma_dir == DMA_FROM_DEVICE &&
2057 !(qc->flags & ATA_QCFLAG_FAILED)) {
2058 ata_tf_from_fis(rx_fis + RX_FIS_PIO_SETUP, &qc->result_tf);
2059 qc->result_tf.command = (rx_fis + RX_FIS_PIO_SETUP)[15];
2060 } else
2061 ata_tf_from_fis(rx_fis + RX_FIS_D2H_REG, &qc->result_tf);
2062
2063 return true;
2064 }
2065
ahci_freeze(struct ata_port * ap)2066 static void ahci_freeze(struct ata_port *ap)
2067 {
2068 void __iomem *port_mmio = ahci_port_base(ap);
2069
2070 /* turn IRQ off */
2071 writel(0, port_mmio + PORT_IRQ_MASK);
2072 }
2073
ahci_thaw(struct ata_port * ap)2074 static void ahci_thaw(struct ata_port *ap)
2075 {
2076 struct ahci_host_priv *hpriv = ap->host->private_data;
2077 void __iomem *mmio = hpriv->mmio;
2078 void __iomem *port_mmio = ahci_port_base(ap);
2079 u32 tmp;
2080 struct ahci_port_priv *pp = ap->private_data;
2081
2082 /* clear IRQ */
2083 tmp = readl(port_mmio + PORT_IRQ_STAT);
2084 writel(tmp, port_mmio + PORT_IRQ_STAT);
2085 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
2086
2087 /* turn IRQ back on */
2088 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2089 }
2090
ahci_error_handler(struct ata_port * ap)2091 void ahci_error_handler(struct ata_port *ap)
2092 {
2093 struct ahci_host_priv *hpriv = ap->host->private_data;
2094
2095 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
2096 /* restart engine */
2097 hpriv->stop_engine(ap);
2098 hpriv->start_engine(ap);
2099 }
2100
2101 sata_pmp_error_handler(ap);
2102
2103 if (!ata_dev_enabled(ap->link.device))
2104 hpriv->stop_engine(ap);
2105 }
2106 EXPORT_SYMBOL_GPL(ahci_error_handler);
2107
ahci_post_internal_cmd(struct ata_queued_cmd * qc)2108 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
2109 {
2110 struct ata_port *ap = qc->ap;
2111
2112 /* make DMA engine forget about the failed command */
2113 if (qc->flags & ATA_QCFLAG_FAILED)
2114 ahci_kick_engine(ap);
2115 }
2116
ahci_set_aggressive_devslp(struct ata_port * ap,bool sleep)2117 static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep)
2118 {
2119 struct ahci_host_priv *hpriv = ap->host->private_data;
2120 void __iomem *port_mmio = ahci_port_base(ap);
2121 struct ata_device *dev = ap->link.device;
2122 u32 devslp, dm, dito, mdat, deto, dito_conf;
2123 int rc;
2124 unsigned int err_mask;
2125
2126 devslp = readl(port_mmio + PORT_DEVSLP);
2127 if (!(devslp & PORT_DEVSLP_DSP)) {
2128 dev_info(ap->host->dev, "port does not support device sleep\n");
2129 return;
2130 }
2131
2132 /* disable device sleep */
2133 if (!sleep) {
2134 if (devslp & PORT_DEVSLP_ADSE) {
2135 writel(devslp & ~PORT_DEVSLP_ADSE,
2136 port_mmio + PORT_DEVSLP);
2137 err_mask = ata_dev_set_feature(dev,
2138 SETFEATURES_SATA_DISABLE,
2139 SATA_DEVSLP);
2140 if (err_mask && err_mask != AC_ERR_DEV)
2141 ata_dev_warn(dev, "failed to disable DEVSLP\n");
2142 }
2143 return;
2144 }
2145
2146 dm = (devslp & PORT_DEVSLP_DM_MASK) >> PORT_DEVSLP_DM_OFFSET;
2147 dito = devslp_idle_timeout / (dm + 1);
2148 if (dito > 0x3ff)
2149 dito = 0x3ff;
2150
2151 dito_conf = (devslp >> PORT_DEVSLP_DITO_OFFSET) & 0x3FF;
2152
2153 /* device sleep was already enabled and same dito */
2154 if ((devslp & PORT_DEVSLP_ADSE) && (dito_conf == dito))
2155 return;
2156
2157 /* set DITO, MDAT, DETO and enable DevSlp, need to stop engine first */
2158 rc = hpriv->stop_engine(ap);
2159 if (rc)
2160 return;
2161
2162 /* Use the nominal value 10 ms if the read MDAT is zero,
2163 * the nominal value of DETO is 20 ms.
2164 */
2165 if (dev->devslp_timing[ATA_LOG_DEVSLP_VALID] &
2166 ATA_LOG_DEVSLP_VALID_MASK) {
2167 mdat = dev->devslp_timing[ATA_LOG_DEVSLP_MDAT] &
2168 ATA_LOG_DEVSLP_MDAT_MASK;
2169 if (!mdat)
2170 mdat = 10;
2171 deto = dev->devslp_timing[ATA_LOG_DEVSLP_DETO];
2172 if (!deto)
2173 deto = 20;
2174 } else {
2175 mdat = 10;
2176 deto = 20;
2177 }
2178
2179 /* Make dito, mdat, deto bits to 0s */
2180 devslp &= ~GENMASK_ULL(24, 2);
2181 devslp |= ((dito << PORT_DEVSLP_DITO_OFFSET) |
2182 (mdat << PORT_DEVSLP_MDAT_OFFSET) |
2183 (deto << PORT_DEVSLP_DETO_OFFSET) |
2184 PORT_DEVSLP_ADSE);
2185 writel(devslp, port_mmio + PORT_DEVSLP);
2186
2187 hpriv->start_engine(ap);
2188
2189 /* enable device sleep feature for the drive */
2190 err_mask = ata_dev_set_feature(dev,
2191 SETFEATURES_SATA_ENABLE,
2192 SATA_DEVSLP);
2193 if (err_mask && err_mask != AC_ERR_DEV)
2194 ata_dev_warn(dev, "failed to enable DEVSLP\n");
2195 }
2196
ahci_enable_fbs(struct ata_port * ap)2197 static void ahci_enable_fbs(struct ata_port *ap)
2198 {
2199 struct ahci_host_priv *hpriv = ap->host->private_data;
2200 struct ahci_port_priv *pp = ap->private_data;
2201 void __iomem *port_mmio = ahci_port_base(ap);
2202 u32 fbs;
2203 int rc;
2204
2205 if (!pp->fbs_supported)
2206 return;
2207
2208 fbs = readl(port_mmio + PORT_FBS);
2209 if (fbs & PORT_FBS_EN) {
2210 pp->fbs_enabled = true;
2211 pp->fbs_last_dev = -1; /* initialization */
2212 return;
2213 }
2214
2215 rc = hpriv->stop_engine(ap);
2216 if (rc)
2217 return;
2218
2219 writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS);
2220 fbs = readl(port_mmio + PORT_FBS);
2221 if (fbs & PORT_FBS_EN) {
2222 dev_info(ap->host->dev, "FBS is enabled\n");
2223 pp->fbs_enabled = true;
2224 pp->fbs_last_dev = -1; /* initialization */
2225 } else
2226 dev_err(ap->host->dev, "Failed to enable FBS\n");
2227
2228 hpriv->start_engine(ap);
2229 }
2230
ahci_disable_fbs(struct ata_port * ap)2231 static void ahci_disable_fbs(struct ata_port *ap)
2232 {
2233 struct ahci_host_priv *hpriv = ap->host->private_data;
2234 struct ahci_port_priv *pp = ap->private_data;
2235 void __iomem *port_mmio = ahci_port_base(ap);
2236 u32 fbs;
2237 int rc;
2238
2239 if (!pp->fbs_supported)
2240 return;
2241
2242 fbs = readl(port_mmio + PORT_FBS);
2243 if ((fbs & PORT_FBS_EN) == 0) {
2244 pp->fbs_enabled = false;
2245 return;
2246 }
2247
2248 rc = hpriv->stop_engine(ap);
2249 if (rc)
2250 return;
2251
2252 writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS);
2253 fbs = readl(port_mmio + PORT_FBS);
2254 if (fbs & PORT_FBS_EN)
2255 dev_err(ap->host->dev, "Failed to disable FBS\n");
2256 else {
2257 dev_info(ap->host->dev, "FBS is disabled\n");
2258 pp->fbs_enabled = false;
2259 }
2260
2261 hpriv->start_engine(ap);
2262 }
2263
ahci_pmp_attach(struct ata_port * ap)2264 static void ahci_pmp_attach(struct ata_port *ap)
2265 {
2266 void __iomem *port_mmio = ahci_port_base(ap);
2267 struct ahci_port_priv *pp = ap->private_data;
2268 u32 cmd;
2269
2270 cmd = readl(port_mmio + PORT_CMD);
2271 cmd |= PORT_CMD_PMP;
2272 writel(cmd, port_mmio + PORT_CMD);
2273
2274 ahci_enable_fbs(ap);
2275
2276 pp->intr_mask |= PORT_IRQ_BAD_PMP;
2277
2278 /*
2279 * We must not change the port interrupt mask register if the
2280 * port is marked frozen, the value in pp->intr_mask will be
2281 * restored later when the port is thawed.
2282 *
2283 * Note that during initialization, the port is marked as
2284 * frozen since the irq handler is not yet registered.
2285 */
2286 if (!(ap->pflags & ATA_PFLAG_FROZEN))
2287 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2288 }
2289
ahci_pmp_detach(struct ata_port * ap)2290 static void ahci_pmp_detach(struct ata_port *ap)
2291 {
2292 void __iomem *port_mmio = ahci_port_base(ap);
2293 struct ahci_port_priv *pp = ap->private_data;
2294 u32 cmd;
2295
2296 ahci_disable_fbs(ap);
2297
2298 cmd = readl(port_mmio + PORT_CMD);
2299 cmd &= ~PORT_CMD_PMP;
2300 writel(cmd, port_mmio + PORT_CMD);
2301
2302 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
2303
2304 /* see comment above in ahci_pmp_attach() */
2305 if (!(ap->pflags & ATA_PFLAG_FROZEN))
2306 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2307 }
2308
ahci_port_resume(struct ata_port * ap)2309 int ahci_port_resume(struct ata_port *ap)
2310 {
2311 ahci_rpm_get_port(ap);
2312
2313 ahci_power_up(ap);
2314 ahci_start_port(ap);
2315
2316 if (sata_pmp_attached(ap))
2317 ahci_pmp_attach(ap);
2318 else
2319 ahci_pmp_detach(ap);
2320
2321 return 0;
2322 }
2323 EXPORT_SYMBOL_GPL(ahci_port_resume);
2324
2325 #ifdef CONFIG_PM
ahci_handle_s2idle(struct ata_port * ap)2326 static void ahci_handle_s2idle(struct ata_port *ap)
2327 {
2328 void __iomem *port_mmio = ahci_port_base(ap);
2329 u32 devslp;
2330
2331 if (pm_suspend_via_firmware())
2332 return;
2333 devslp = readl(port_mmio + PORT_DEVSLP);
2334 if ((devslp & PORT_DEVSLP_ADSE))
2335 ata_msleep(ap, devslp_idle_timeout);
2336 }
2337
ahci_port_suspend(struct ata_port * ap,pm_message_t mesg)2338 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
2339 {
2340 const char *emsg = NULL;
2341 int rc;
2342
2343 rc = ahci_deinit_port(ap, &emsg);
2344 if (rc == 0)
2345 ahci_power_down(ap);
2346 else {
2347 ata_port_err(ap, "%s (%d)\n", emsg, rc);
2348 ata_port_freeze(ap);
2349 }
2350
2351 if (acpi_storage_d3(ap->host->dev))
2352 ahci_handle_s2idle(ap);
2353
2354 ahci_rpm_put_port(ap);
2355 return rc;
2356 }
2357 #endif
2358
ahci_port_start(struct ata_port * ap)2359 static int ahci_port_start(struct ata_port *ap)
2360 {
2361 struct ahci_host_priv *hpriv = ap->host->private_data;
2362 struct device *dev = ap->host->dev;
2363 struct ahci_port_priv *pp;
2364 void *mem;
2365 dma_addr_t mem_dma;
2366 size_t dma_sz, rx_fis_sz;
2367
2368 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
2369 if (!pp)
2370 return -ENOMEM;
2371
2372 if (ap->host->n_ports > 1) {
2373 pp->irq_desc = devm_kzalloc(dev, 8, GFP_KERNEL);
2374 if (!pp->irq_desc) {
2375 devm_kfree(dev, pp);
2376 return -ENOMEM;
2377 }
2378 snprintf(pp->irq_desc, 8,
2379 "%s%d", dev_driver_string(dev), ap->port_no);
2380 }
2381
2382 /* check FBS capability */
2383 if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) {
2384 void __iomem *port_mmio = ahci_port_base(ap);
2385 u32 cmd = readl(port_mmio + PORT_CMD);
2386 if (cmd & PORT_CMD_FBSCP)
2387 pp->fbs_supported = true;
2388 else if (hpriv->flags & AHCI_HFLAG_YES_FBS) {
2389 dev_info(dev, "port %d can do FBS, forcing FBSCP\n",
2390 ap->port_no);
2391 pp->fbs_supported = true;
2392 } else
2393 dev_warn(dev, "port %d is not capable of FBS\n",
2394 ap->port_no);
2395 }
2396
2397 if (pp->fbs_supported) {
2398 dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ;
2399 rx_fis_sz = AHCI_RX_FIS_SZ * 16;
2400 } else {
2401 dma_sz = AHCI_PORT_PRIV_DMA_SZ;
2402 rx_fis_sz = AHCI_RX_FIS_SZ;
2403 }
2404
2405 mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL);
2406 if (!mem)
2407 return -ENOMEM;
2408
2409 /*
2410 * First item in chunk of DMA memory: 32-slot command table,
2411 * 32 bytes each in size
2412 */
2413 pp->cmd_slot = mem;
2414 pp->cmd_slot_dma = mem_dma;
2415
2416 mem += AHCI_CMD_SLOT_SZ;
2417 mem_dma += AHCI_CMD_SLOT_SZ;
2418
2419 /*
2420 * Second item: Received-FIS area
2421 */
2422 pp->rx_fis = mem;
2423 pp->rx_fis_dma = mem_dma;
2424
2425 mem += rx_fis_sz;
2426 mem_dma += rx_fis_sz;
2427
2428 /*
2429 * Third item: data area for storing a single command
2430 * and its scatter-gather table
2431 */
2432 pp->cmd_tbl = mem;
2433 pp->cmd_tbl_dma = mem_dma;
2434
2435 /*
2436 * Save off initial list of interrupts to be enabled.
2437 * This could be changed later
2438 */
2439 pp->intr_mask = DEF_PORT_IRQ;
2440
2441 /*
2442 * Switch to per-port locking in case each port has its own MSI vector.
2443 */
2444 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI) {
2445 spin_lock_init(&pp->lock);
2446 ap->lock = &pp->lock;
2447 }
2448
2449 ap->private_data = pp;
2450
2451 /* engage engines, captain */
2452 return ahci_port_resume(ap);
2453 }
2454
ahci_port_stop(struct ata_port * ap)2455 static void ahci_port_stop(struct ata_port *ap)
2456 {
2457 const char *emsg = NULL;
2458 struct ahci_host_priv *hpriv = ap->host->private_data;
2459 void __iomem *host_mmio = hpriv->mmio;
2460 int rc;
2461
2462 /* de-initialize port */
2463 rc = ahci_deinit_port(ap, &emsg);
2464 if (rc)
2465 ata_port_warn(ap, "%s (%d)\n", emsg, rc);
2466
2467 /*
2468 * Clear GHC.IS to prevent stuck INTx after disabling MSI and
2469 * re-enabling INTx.
2470 */
2471 writel(1 << ap->port_no, host_mmio + HOST_IRQ_STAT);
2472
2473 ahci_rpm_put_port(ap);
2474 }
2475
ahci_print_info(struct ata_host * host,const char * scc_s)2476 void ahci_print_info(struct ata_host *host, const char *scc_s)
2477 {
2478 struct ahci_host_priv *hpriv = host->private_data;
2479 u32 vers, cap, cap2, impl, speed;
2480 const char *speed_s;
2481
2482 vers = hpriv->version;
2483 cap = hpriv->cap;
2484 cap2 = hpriv->cap2;
2485 impl = hpriv->port_map;
2486
2487 speed = (cap >> 20) & 0xf;
2488 if (speed == 1)
2489 speed_s = "1.5";
2490 else if (speed == 2)
2491 speed_s = "3";
2492 else if (speed == 3)
2493 speed_s = "6";
2494 else
2495 speed_s = "?";
2496
2497 dev_info(host->dev,
2498 "AHCI %02x%02x.%02x%02x "
2499 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2500 ,
2501
2502 (vers >> 24) & 0xff,
2503 (vers >> 16) & 0xff,
2504 (vers >> 8) & 0xff,
2505 vers & 0xff,
2506
2507 ((cap >> 8) & 0x1f) + 1,
2508 (cap & 0x1f) + 1,
2509 speed_s,
2510 impl,
2511 scc_s);
2512
2513 dev_info(host->dev,
2514 "flags: "
2515 "%s%s%s%s%s%s%s"
2516 "%s%s%s%s%s%s%s"
2517 "%s%s%s%s%s%s%s"
2518 "%s%s\n"
2519 ,
2520
2521 cap & HOST_CAP_64 ? "64bit " : "",
2522 cap & HOST_CAP_NCQ ? "ncq " : "",
2523 cap & HOST_CAP_SNTF ? "sntf " : "",
2524 cap & HOST_CAP_MPS ? "ilck " : "",
2525 cap & HOST_CAP_SSS ? "stag " : "",
2526 cap & HOST_CAP_ALPM ? "pm " : "",
2527 cap & HOST_CAP_LED ? "led " : "",
2528 cap & HOST_CAP_CLO ? "clo " : "",
2529 cap & HOST_CAP_ONLY ? "only " : "",
2530 cap & HOST_CAP_PMP ? "pmp " : "",
2531 cap & HOST_CAP_FBS ? "fbs " : "",
2532 cap & HOST_CAP_PIO_MULTI ? "pio " : "",
2533 cap & HOST_CAP_SSC ? "slum " : "",
2534 cap & HOST_CAP_PART ? "part " : "",
2535 cap & HOST_CAP_CCC ? "ccc " : "",
2536 cap & HOST_CAP_EMS ? "ems " : "",
2537 cap & HOST_CAP_SXS ? "sxs " : "",
2538 cap2 & HOST_CAP2_DESO ? "deso " : "",
2539 cap2 & HOST_CAP2_SADM ? "sadm " : "",
2540 cap2 & HOST_CAP2_SDS ? "sds " : "",
2541 cap2 & HOST_CAP2_APST ? "apst " : "",
2542 cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "",
2543 cap2 & HOST_CAP2_BOH ? "boh " : ""
2544 );
2545 }
2546 EXPORT_SYMBOL_GPL(ahci_print_info);
2547
ahci_set_em_messages(struct ahci_host_priv * hpriv,struct ata_port_info * pi)2548 void ahci_set_em_messages(struct ahci_host_priv *hpriv,
2549 struct ata_port_info *pi)
2550 {
2551 u8 messages;
2552 void __iomem *mmio = hpriv->mmio;
2553 u32 em_loc = readl(mmio + HOST_EM_LOC);
2554 u32 em_ctl = readl(mmio + HOST_EM_CTL);
2555
2556 if (!ahci_em_messages || !(hpriv->cap & HOST_CAP_EMS))
2557 return;
2558
2559 messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16;
2560
2561 if (messages) {
2562 /* store em_loc */
2563 hpriv->em_loc = ((em_loc >> 16) * 4);
2564 hpriv->em_buf_sz = ((em_loc & 0xff) * 4);
2565 hpriv->em_msg_type = messages;
2566 pi->flags |= ATA_FLAG_EM;
2567 if (!(em_ctl & EM_CTL_ALHD))
2568 pi->flags |= ATA_FLAG_SW_ACTIVITY;
2569 }
2570 }
2571 EXPORT_SYMBOL_GPL(ahci_set_em_messages);
2572
ahci_host_activate_multi_irqs(struct ata_host * host,struct scsi_host_template * sht)2573 static int ahci_host_activate_multi_irqs(struct ata_host *host,
2574 struct scsi_host_template *sht)
2575 {
2576 struct ahci_host_priv *hpriv = host->private_data;
2577 int i, rc;
2578
2579 rc = ata_host_start(host);
2580 if (rc)
2581 return rc;
2582 /*
2583 * Requests IRQs according to AHCI-1.1 when multiple MSIs were
2584 * allocated. That is one MSI per port, starting from @irq.
2585 */
2586 for (i = 0; i < host->n_ports; i++) {
2587 struct ahci_port_priv *pp = host->ports[i]->private_data;
2588 int irq = hpriv->get_irq_vector(host, i);
2589
2590 /* Do not receive interrupts sent by dummy ports */
2591 if (!pp) {
2592 disable_irq(irq);
2593 continue;
2594 }
2595
2596 rc = devm_request_irq(host->dev, irq, ahci_multi_irqs_intr_hard,
2597 0, pp->irq_desc, host->ports[i]);
2598
2599 if (rc)
2600 return rc;
2601 ata_port_desc(host->ports[i], "irq %d", irq);
2602 }
2603
2604 return ata_host_register(host, sht);
2605 }
2606
2607 /**
2608 * ahci_host_activate - start AHCI host, request IRQs and register it
2609 * @host: target ATA host
2610 * @sht: scsi_host_template to use when registering the host
2611 *
2612 * LOCKING:
2613 * Inherited from calling layer (may sleep).
2614 *
2615 * RETURNS:
2616 * 0 on success, -errno otherwise.
2617 */
ahci_host_activate(struct ata_host * host,struct scsi_host_template * sht)2618 int ahci_host_activate(struct ata_host *host, struct scsi_host_template *sht)
2619 {
2620 struct ahci_host_priv *hpriv = host->private_data;
2621 int irq = hpriv->irq;
2622 int rc;
2623
2624 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI) {
2625 if (hpriv->irq_handler &&
2626 hpriv->irq_handler != ahci_single_level_irq_intr)
2627 dev_warn(host->dev,
2628 "both AHCI_HFLAG_MULTI_MSI flag set and custom irq handler implemented\n");
2629 if (!hpriv->get_irq_vector) {
2630 dev_err(host->dev,
2631 "AHCI_HFLAG_MULTI_MSI requires ->get_irq_vector!\n");
2632 return -EIO;
2633 }
2634
2635 rc = ahci_host_activate_multi_irqs(host, sht);
2636 } else {
2637 rc = ata_host_activate(host, irq, hpriv->irq_handler,
2638 IRQF_SHARED, sht);
2639 }
2640
2641
2642 return rc;
2643 }
2644 EXPORT_SYMBOL_GPL(ahci_host_activate);
2645
2646 MODULE_AUTHOR("Jeff Garzik");
2647 MODULE_DESCRIPTION("Common AHCI SATA low-level routines");
2648 MODULE_LICENSE("GPL");
2649