1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * MHI PCI driver - MHI over PCI controller driver
4 *
5 * This module is a generic driver for registering MHI-over-PCI devices,
6 * such as PCIe QCOM modems.
7 *
8 * Copyright (C) 2020 Linaro Ltd <loic.poulain@linaro.org>
9 */
10
11 #include <linux/aer.h>
12 #include <linux/delay.h>
13 #include <linux/device.h>
14 #include <linux/mhi.h>
15 #include <linux/module.h>
16 #include <linux/pci.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/timer.h>
19 #include <linux/workqueue.h>
20
21 #define MHI_PCI_DEFAULT_BAR_NUM 0
22
23 #define MHI_POST_RESET_DELAY_MS 2000
24
25 #define HEALTH_CHECK_PERIOD (HZ * 2)
26
27 /**
28 * struct mhi_pci_dev_info - MHI PCI device specific information
29 * @config: MHI controller configuration
30 * @name: name of the PCI module
31 * @fw: firmware path (if any)
32 * @edl: emergency download mode firmware path (if any)
33 * @bar_num: PCI base address register to use for MHI MMIO register space
34 * @dma_data_width: DMA transfer word size (32 or 64 bits)
35 * @mru_default: default MRU size for MBIM network packets
36 * @sideband_wake: Devices using dedicated sideband GPIO for wakeup instead
37 * of inband wake support (such as sdx24)
38 */
39 struct mhi_pci_dev_info {
40 const struct mhi_controller_config *config;
41 const char *name;
42 const char *fw;
43 const char *edl;
44 unsigned int bar_num;
45 unsigned int dma_data_width;
46 unsigned int mru_default;
47 bool sideband_wake;
48 };
49
50 #define MHI_CHANNEL_CONFIG_UL(ch_num, ch_name, el_count, ev_ring) \
51 { \
52 .num = ch_num, \
53 .name = ch_name, \
54 .num_elements = el_count, \
55 .event_ring = ev_ring, \
56 .dir = DMA_TO_DEVICE, \
57 .ee_mask = BIT(MHI_EE_AMSS), \
58 .pollcfg = 0, \
59 .doorbell = MHI_DB_BRST_DISABLE, \
60 .lpm_notify = false, \
61 .offload_channel = false, \
62 .doorbell_mode_switch = false, \
63 } \
64
65 #define MHI_CHANNEL_CONFIG_DL(ch_num, ch_name, el_count, ev_ring) \
66 { \
67 .num = ch_num, \
68 .name = ch_name, \
69 .num_elements = el_count, \
70 .event_ring = ev_ring, \
71 .dir = DMA_FROM_DEVICE, \
72 .ee_mask = BIT(MHI_EE_AMSS), \
73 .pollcfg = 0, \
74 .doorbell = MHI_DB_BRST_DISABLE, \
75 .lpm_notify = false, \
76 .offload_channel = false, \
77 .doorbell_mode_switch = false, \
78 }
79
80 #define MHI_CHANNEL_CONFIG_DL_AUTOQUEUE(ch_num, ch_name, el_count, ev_ring) \
81 { \
82 .num = ch_num, \
83 .name = ch_name, \
84 .num_elements = el_count, \
85 .event_ring = ev_ring, \
86 .dir = DMA_FROM_DEVICE, \
87 .ee_mask = BIT(MHI_EE_AMSS), \
88 .pollcfg = 0, \
89 .doorbell = MHI_DB_BRST_DISABLE, \
90 .lpm_notify = false, \
91 .offload_channel = false, \
92 .doorbell_mode_switch = false, \
93 .auto_queue = true, \
94 }
95
96 #define MHI_EVENT_CONFIG_CTRL(ev_ring, el_count) \
97 { \
98 .num_elements = el_count, \
99 .irq_moderation_ms = 0, \
100 .irq = (ev_ring) + 1, \
101 .priority = 1, \
102 .mode = MHI_DB_BRST_DISABLE, \
103 .data_type = MHI_ER_CTRL, \
104 .hardware_event = false, \
105 .client_managed = false, \
106 .offload_channel = false, \
107 }
108
109 #define MHI_CHANNEL_CONFIG_HW_UL(ch_num, ch_name, el_count, ev_ring) \
110 { \
111 .num = ch_num, \
112 .name = ch_name, \
113 .num_elements = el_count, \
114 .event_ring = ev_ring, \
115 .dir = DMA_TO_DEVICE, \
116 .ee_mask = BIT(MHI_EE_AMSS), \
117 .pollcfg = 0, \
118 .doorbell = MHI_DB_BRST_ENABLE, \
119 .lpm_notify = false, \
120 .offload_channel = false, \
121 .doorbell_mode_switch = true, \
122 } \
123
124 #define MHI_CHANNEL_CONFIG_HW_DL(ch_num, ch_name, el_count, ev_ring) \
125 { \
126 .num = ch_num, \
127 .name = ch_name, \
128 .num_elements = el_count, \
129 .event_ring = ev_ring, \
130 .dir = DMA_FROM_DEVICE, \
131 .ee_mask = BIT(MHI_EE_AMSS), \
132 .pollcfg = 0, \
133 .doorbell = MHI_DB_BRST_ENABLE, \
134 .lpm_notify = false, \
135 .offload_channel = false, \
136 .doorbell_mode_switch = true, \
137 }
138
139 #define MHI_CHANNEL_CONFIG_UL_SBL(ch_num, ch_name, el_count, ev_ring) \
140 { \
141 .num = ch_num, \
142 .name = ch_name, \
143 .num_elements = el_count, \
144 .event_ring = ev_ring, \
145 .dir = DMA_TO_DEVICE, \
146 .ee_mask = BIT(MHI_EE_SBL), \
147 .pollcfg = 0, \
148 .doorbell = MHI_DB_BRST_DISABLE, \
149 .lpm_notify = false, \
150 .offload_channel = false, \
151 .doorbell_mode_switch = false, \
152 } \
153
154 #define MHI_CHANNEL_CONFIG_DL_SBL(ch_num, ch_name, el_count, ev_ring) \
155 { \
156 .num = ch_num, \
157 .name = ch_name, \
158 .num_elements = el_count, \
159 .event_ring = ev_ring, \
160 .dir = DMA_FROM_DEVICE, \
161 .ee_mask = BIT(MHI_EE_SBL), \
162 .pollcfg = 0, \
163 .doorbell = MHI_DB_BRST_DISABLE, \
164 .lpm_notify = false, \
165 .offload_channel = false, \
166 .doorbell_mode_switch = false, \
167 }
168
169 #define MHI_CHANNEL_CONFIG_UL_FP(ch_num, ch_name, el_count, ev_ring) \
170 { \
171 .num = ch_num, \
172 .name = ch_name, \
173 .num_elements = el_count, \
174 .event_ring = ev_ring, \
175 .dir = DMA_TO_DEVICE, \
176 .ee_mask = BIT(MHI_EE_FP), \
177 .pollcfg = 0, \
178 .doorbell = MHI_DB_BRST_DISABLE, \
179 .lpm_notify = false, \
180 .offload_channel = false, \
181 .doorbell_mode_switch = false, \
182 } \
183
184 #define MHI_CHANNEL_CONFIG_DL_FP(ch_num, ch_name, el_count, ev_ring) \
185 { \
186 .num = ch_num, \
187 .name = ch_name, \
188 .num_elements = el_count, \
189 .event_ring = ev_ring, \
190 .dir = DMA_FROM_DEVICE, \
191 .ee_mask = BIT(MHI_EE_FP), \
192 .pollcfg = 0, \
193 .doorbell = MHI_DB_BRST_DISABLE, \
194 .lpm_notify = false, \
195 .offload_channel = false, \
196 .doorbell_mode_switch = false, \
197 }
198
199 #define MHI_EVENT_CONFIG_DATA(ev_ring, el_count) \
200 { \
201 .num_elements = el_count, \
202 .irq_moderation_ms = 5, \
203 .irq = (ev_ring) + 1, \
204 .priority = 1, \
205 .mode = MHI_DB_BRST_DISABLE, \
206 .data_type = MHI_ER_DATA, \
207 .hardware_event = false, \
208 .client_managed = false, \
209 .offload_channel = false, \
210 }
211
212 #define MHI_EVENT_CONFIG_HW_DATA(ev_ring, el_count, ch_num) \
213 { \
214 .num_elements = el_count, \
215 .irq_moderation_ms = 1, \
216 .irq = (ev_ring) + 1, \
217 .priority = 1, \
218 .mode = MHI_DB_BRST_DISABLE, \
219 .data_type = MHI_ER_DATA, \
220 .hardware_event = true, \
221 .client_managed = false, \
222 .offload_channel = false, \
223 .channel = ch_num, \
224 }
225
226 static const struct mhi_channel_config modem_qcom_v1_mhi_channels[] = {
227 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 16, 1),
228 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 16, 1),
229 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 4, 0),
230 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 4, 0),
231 MHI_CHANNEL_CONFIG_UL(14, "QMI", 4, 0),
232 MHI_CHANNEL_CONFIG_DL(15, "QMI", 4, 0),
233 MHI_CHANNEL_CONFIG_UL(20, "IPCR", 8, 0),
234 MHI_CHANNEL_CONFIG_DL_AUTOQUEUE(21, "IPCR", 8, 0),
235 MHI_CHANNEL_CONFIG_UL_FP(34, "FIREHOSE", 32, 0),
236 MHI_CHANNEL_CONFIG_DL_FP(35, "FIREHOSE", 32, 0),
237 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0", 128, 2),
238 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0", 128, 3),
239 };
240
241 static struct mhi_event_config modem_qcom_v1_mhi_events[] = {
242 /* first ring is control+data ring */
243 MHI_EVENT_CONFIG_CTRL(0, 64),
244 /* DIAG dedicated event ring */
245 MHI_EVENT_CONFIG_DATA(1, 128),
246 /* Hardware channels request dedicated hardware event rings */
247 MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100),
248 MHI_EVENT_CONFIG_HW_DATA(3, 2048, 101)
249 };
250
251 static const struct mhi_controller_config modem_qcom_v1_mhiv_config = {
252 .max_channels = 128,
253 .timeout_ms = 8000,
254 .num_channels = ARRAY_SIZE(modem_qcom_v1_mhi_channels),
255 .ch_cfg = modem_qcom_v1_mhi_channels,
256 .num_events = ARRAY_SIZE(modem_qcom_v1_mhi_events),
257 .event_cfg = modem_qcom_v1_mhi_events,
258 };
259
260 static const struct mhi_pci_dev_info mhi_qcom_sdx65_info = {
261 .name = "qcom-sdx65m",
262 .fw = "qcom/sdx65m/xbl.elf",
263 .edl = "qcom/sdx65m/edl.mbn",
264 .config = &modem_qcom_v1_mhiv_config,
265 .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
266 .dma_data_width = 32,
267 .sideband_wake = false,
268 };
269
270 static const struct mhi_pci_dev_info mhi_qcom_sdx55_info = {
271 .name = "qcom-sdx55m",
272 .fw = "qcom/sdx55m/sbl1.mbn",
273 .edl = "qcom/sdx55m/edl.mbn",
274 .config = &modem_qcom_v1_mhiv_config,
275 .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
276 .dma_data_width = 32,
277 .mru_default = 32768,
278 .sideband_wake = false,
279 };
280
281 static const struct mhi_pci_dev_info mhi_qcom_sdx24_info = {
282 .name = "qcom-sdx24",
283 .edl = "qcom/prog_firehose_sdx24.mbn",
284 .config = &modem_qcom_v1_mhiv_config,
285 .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
286 .dma_data_width = 32,
287 .sideband_wake = true,
288 };
289
290 static const struct mhi_channel_config mhi_quectel_em1xx_channels[] = {
291 MHI_CHANNEL_CONFIG_UL(0, "NMEA", 32, 0),
292 MHI_CHANNEL_CONFIG_DL(1, "NMEA", 32, 0),
293 MHI_CHANNEL_CONFIG_UL_SBL(2, "SAHARA", 32, 0),
294 MHI_CHANNEL_CONFIG_DL_SBL(3, "SAHARA", 32, 0),
295 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 32, 1),
296 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 32, 1),
297 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 32, 0),
298 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 32, 0),
299 MHI_CHANNEL_CONFIG_UL(32, "DUN", 32, 0),
300 MHI_CHANNEL_CONFIG_DL(33, "DUN", 32, 0),
301 /* The EDL firmware is a flash-programmer exposing firehose protocol */
302 MHI_CHANNEL_CONFIG_UL_FP(34, "FIREHOSE", 32, 0),
303 MHI_CHANNEL_CONFIG_DL_FP(35, "FIREHOSE", 32, 0),
304 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 128, 2),
305 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 128, 3),
306 };
307
308 static struct mhi_event_config mhi_quectel_em1xx_events[] = {
309 MHI_EVENT_CONFIG_CTRL(0, 128),
310 MHI_EVENT_CONFIG_DATA(1, 128),
311 MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100),
312 MHI_EVENT_CONFIG_HW_DATA(3, 1024, 101)
313 };
314
315 static const struct mhi_controller_config modem_quectel_em1xx_config = {
316 .max_channels = 128,
317 .timeout_ms = 20000,
318 .num_channels = ARRAY_SIZE(mhi_quectel_em1xx_channels),
319 .ch_cfg = mhi_quectel_em1xx_channels,
320 .num_events = ARRAY_SIZE(mhi_quectel_em1xx_events),
321 .event_cfg = mhi_quectel_em1xx_events,
322 };
323
324 static const struct mhi_pci_dev_info mhi_quectel_em1xx_info = {
325 .name = "quectel-em1xx",
326 .edl = "qcom/prog_firehose_sdx24.mbn",
327 .config = &modem_quectel_em1xx_config,
328 .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
329 .dma_data_width = 32,
330 .sideband_wake = true,
331 };
332
333 static const struct mhi_channel_config mhi_foxconn_sdx55_channels[] = {
334 MHI_CHANNEL_CONFIG_UL(0, "LOOPBACK", 32, 0),
335 MHI_CHANNEL_CONFIG_DL(1, "LOOPBACK", 32, 0),
336 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 32, 1),
337 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 32, 1),
338 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 32, 0),
339 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 32, 0),
340 MHI_CHANNEL_CONFIG_UL(32, "DUN", 32, 0),
341 MHI_CHANNEL_CONFIG_DL(33, "DUN", 32, 0),
342 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 128, 2),
343 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 128, 3),
344 };
345
346 static struct mhi_event_config mhi_foxconn_sdx55_events[] = {
347 MHI_EVENT_CONFIG_CTRL(0, 128),
348 MHI_EVENT_CONFIG_DATA(1, 128),
349 MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100),
350 MHI_EVENT_CONFIG_HW_DATA(3, 1024, 101)
351 };
352
353 static const struct mhi_controller_config modem_foxconn_sdx55_config = {
354 .max_channels = 128,
355 .timeout_ms = 20000,
356 .num_channels = ARRAY_SIZE(mhi_foxconn_sdx55_channels),
357 .ch_cfg = mhi_foxconn_sdx55_channels,
358 .num_events = ARRAY_SIZE(mhi_foxconn_sdx55_events),
359 .event_cfg = mhi_foxconn_sdx55_events,
360 };
361
362 static const struct mhi_pci_dev_info mhi_foxconn_sdx55_info = {
363 .name = "foxconn-sdx55",
364 .fw = "qcom/sdx55m/sbl1.mbn",
365 .edl = "qcom/sdx55m/edl.mbn",
366 .config = &modem_foxconn_sdx55_config,
367 .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
368 .dma_data_width = 32,
369 .sideband_wake = false,
370 };
371
372 static const struct mhi_channel_config mhi_mv31_channels[] = {
373 MHI_CHANNEL_CONFIG_UL(0, "LOOPBACK", 64, 0),
374 MHI_CHANNEL_CONFIG_DL(1, "LOOPBACK", 64, 0),
375 /* MBIM Control Channel */
376 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 64, 0),
377 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 64, 0),
378 /* MBIM Data Channel */
379 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 512, 2),
380 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 512, 3),
381 };
382
383 static struct mhi_event_config mhi_mv31_events[] = {
384 MHI_EVENT_CONFIG_CTRL(0, 256),
385 MHI_EVENT_CONFIG_DATA(1, 256),
386 MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100),
387 MHI_EVENT_CONFIG_HW_DATA(3, 1024, 101),
388 };
389
390 static const struct mhi_controller_config modem_mv31_config = {
391 .max_channels = 128,
392 .timeout_ms = 20000,
393 .num_channels = ARRAY_SIZE(mhi_mv31_channels),
394 .ch_cfg = mhi_mv31_channels,
395 .num_events = ARRAY_SIZE(mhi_mv31_events),
396 .event_cfg = mhi_mv31_events,
397 };
398
399 static const struct mhi_pci_dev_info mhi_mv31_info = {
400 .name = "cinterion-mv31",
401 .config = &modem_mv31_config,
402 .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
403 .dma_data_width = 32,
404 };
405
406 static const struct pci_device_id mhi_pci_id_table[] = {
407 { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0306),
408 .driver_data = (kernel_ulong_t) &mhi_qcom_sdx55_info },
409 { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0304),
410 .driver_data = (kernel_ulong_t) &mhi_qcom_sdx24_info },
411 { PCI_DEVICE(0x1eac, 0x1001), /* EM120R-GL (sdx24) */
412 .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info },
413 { PCI_DEVICE(0x1eac, 0x1002), /* EM160R-GL (sdx24) */
414 .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info },
415 { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0308),
416 .driver_data = (kernel_ulong_t) &mhi_qcom_sdx65_info },
417 /* T99W175 (sdx55), Both for eSIM and Non-eSIM */
418 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0ab),
419 .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx55_info },
420 /* DW5930e (sdx55), With eSIM, It's also T99W175 */
421 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0b0),
422 .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx55_info },
423 /* DW5930e (sdx55), Non-eSIM, It's also T99W175 */
424 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0b1),
425 .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx55_info },
426 /* MV31-W (Cinterion) */
427 { PCI_DEVICE(0x1269, 0x00b3),
428 .driver_data = (kernel_ulong_t) &mhi_mv31_info },
429 { }
430 };
431 MODULE_DEVICE_TABLE(pci, mhi_pci_id_table);
432
433 enum mhi_pci_device_status {
434 MHI_PCI_DEV_STARTED,
435 MHI_PCI_DEV_SUSPENDED,
436 };
437
438 struct mhi_pci_device {
439 struct mhi_controller mhi_cntrl;
440 struct pci_saved_state *pci_state;
441 struct work_struct recovery_work;
442 struct timer_list health_check_timer;
443 unsigned long status;
444 };
445
mhi_pci_read_reg(struct mhi_controller * mhi_cntrl,void __iomem * addr,u32 * out)446 static int mhi_pci_read_reg(struct mhi_controller *mhi_cntrl,
447 void __iomem *addr, u32 *out)
448 {
449 *out = readl(addr);
450 return 0;
451 }
452
mhi_pci_write_reg(struct mhi_controller * mhi_cntrl,void __iomem * addr,u32 val)453 static void mhi_pci_write_reg(struct mhi_controller *mhi_cntrl,
454 void __iomem *addr, u32 val)
455 {
456 writel(val, addr);
457 }
458
mhi_pci_status_cb(struct mhi_controller * mhi_cntrl,enum mhi_callback cb)459 static void mhi_pci_status_cb(struct mhi_controller *mhi_cntrl,
460 enum mhi_callback cb)
461 {
462 struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev);
463
464 /* Nothing to do for now */
465 switch (cb) {
466 case MHI_CB_FATAL_ERROR:
467 case MHI_CB_SYS_ERROR:
468 dev_warn(&pdev->dev, "firmware crashed (%u)\n", cb);
469 pm_runtime_forbid(&pdev->dev);
470 break;
471 case MHI_CB_EE_MISSION_MODE:
472 pm_runtime_allow(&pdev->dev);
473 break;
474 default:
475 break;
476 }
477 }
478
mhi_pci_wake_get_nop(struct mhi_controller * mhi_cntrl,bool force)479 static void mhi_pci_wake_get_nop(struct mhi_controller *mhi_cntrl, bool force)
480 {
481 /* no-op */
482 }
483
mhi_pci_wake_put_nop(struct mhi_controller * mhi_cntrl,bool override)484 static void mhi_pci_wake_put_nop(struct mhi_controller *mhi_cntrl, bool override)
485 {
486 /* no-op */
487 }
488
mhi_pci_wake_toggle_nop(struct mhi_controller * mhi_cntrl)489 static void mhi_pci_wake_toggle_nop(struct mhi_controller *mhi_cntrl)
490 {
491 /* no-op */
492 }
493
mhi_pci_is_alive(struct mhi_controller * mhi_cntrl)494 static bool mhi_pci_is_alive(struct mhi_controller *mhi_cntrl)
495 {
496 struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev);
497 u16 vendor = 0;
498
499 if (pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor))
500 return false;
501
502 if (vendor == (u16) ~0 || vendor == 0)
503 return false;
504
505 return true;
506 }
507
mhi_pci_claim(struct mhi_controller * mhi_cntrl,unsigned int bar_num,u64 dma_mask)508 static int mhi_pci_claim(struct mhi_controller *mhi_cntrl,
509 unsigned int bar_num, u64 dma_mask)
510 {
511 struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev);
512 int err;
513
514 err = pci_assign_resource(pdev, bar_num);
515 if (err)
516 return err;
517
518 err = pcim_enable_device(pdev);
519 if (err) {
520 dev_err(&pdev->dev, "failed to enable pci device: %d\n", err);
521 return err;
522 }
523
524 err = pcim_iomap_regions(pdev, 1 << bar_num, pci_name(pdev));
525 if (err) {
526 dev_err(&pdev->dev, "failed to map pci region: %d\n", err);
527 return err;
528 }
529 mhi_cntrl->regs = pcim_iomap_table(pdev)[bar_num];
530 mhi_cntrl->reg_len = pci_resource_len(pdev, bar_num);
531
532 err = pci_set_dma_mask(pdev, dma_mask);
533 if (err) {
534 dev_err(&pdev->dev, "Cannot set proper DMA mask\n");
535 return err;
536 }
537
538 err = pci_set_consistent_dma_mask(pdev, dma_mask);
539 if (err) {
540 dev_err(&pdev->dev, "set consistent dma mask failed\n");
541 return err;
542 }
543
544 pci_set_master(pdev);
545
546 return 0;
547 }
548
mhi_pci_get_irqs(struct mhi_controller * mhi_cntrl,const struct mhi_controller_config * mhi_cntrl_config)549 static int mhi_pci_get_irqs(struct mhi_controller *mhi_cntrl,
550 const struct mhi_controller_config *mhi_cntrl_config)
551 {
552 struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev);
553 int nr_vectors, i;
554 int *irq;
555
556 /*
557 * Alloc one MSI vector for BHI + one vector per event ring, ideally...
558 * No explicit pci_free_irq_vectors required, done by pcim_release.
559 */
560 mhi_cntrl->nr_irqs = 1 + mhi_cntrl_config->num_events;
561
562 nr_vectors = pci_alloc_irq_vectors(pdev, 1, mhi_cntrl->nr_irqs, PCI_IRQ_MSI);
563 if (nr_vectors < 0) {
564 dev_err(&pdev->dev, "Error allocating MSI vectors %d\n",
565 nr_vectors);
566 return nr_vectors;
567 }
568
569 if (nr_vectors < mhi_cntrl->nr_irqs) {
570 dev_warn(&pdev->dev, "using shared MSI\n");
571
572 /* Patch msi vectors, use only one (shared) */
573 for (i = 0; i < mhi_cntrl_config->num_events; i++)
574 mhi_cntrl_config->event_cfg[i].irq = 0;
575 mhi_cntrl->nr_irqs = 1;
576 }
577
578 irq = devm_kcalloc(&pdev->dev, mhi_cntrl->nr_irqs, sizeof(int), GFP_KERNEL);
579 if (!irq)
580 return -ENOMEM;
581
582 for (i = 0; i < mhi_cntrl->nr_irqs; i++) {
583 int vector = i >= nr_vectors ? (nr_vectors - 1) : i;
584
585 irq[i] = pci_irq_vector(pdev, vector);
586 }
587
588 mhi_cntrl->irq = irq;
589
590 return 0;
591 }
592
mhi_pci_runtime_get(struct mhi_controller * mhi_cntrl)593 static int mhi_pci_runtime_get(struct mhi_controller *mhi_cntrl)
594 {
595 /* The runtime_get() MHI callback means:
596 * Do whatever is requested to leave M3.
597 */
598 return pm_runtime_get(mhi_cntrl->cntrl_dev);
599 }
600
mhi_pci_runtime_put(struct mhi_controller * mhi_cntrl)601 static void mhi_pci_runtime_put(struct mhi_controller *mhi_cntrl)
602 {
603 /* The runtime_put() MHI callback means:
604 * Device can be moved in M3 state.
605 */
606 pm_runtime_mark_last_busy(mhi_cntrl->cntrl_dev);
607 pm_runtime_put(mhi_cntrl->cntrl_dev);
608 }
609
mhi_pci_recovery_work(struct work_struct * work)610 static void mhi_pci_recovery_work(struct work_struct *work)
611 {
612 struct mhi_pci_device *mhi_pdev = container_of(work, struct mhi_pci_device,
613 recovery_work);
614 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl;
615 struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev);
616 int err;
617
618 dev_warn(&pdev->dev, "device recovery started\n");
619
620 del_timer(&mhi_pdev->health_check_timer);
621 pm_runtime_forbid(&pdev->dev);
622
623 /* Clean up MHI state */
624 if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) {
625 mhi_power_down(mhi_cntrl, false);
626 mhi_unprepare_after_power_down(mhi_cntrl);
627 }
628
629 pci_set_power_state(pdev, PCI_D0);
630 pci_load_saved_state(pdev, mhi_pdev->pci_state);
631 pci_restore_state(pdev);
632
633 if (!mhi_pci_is_alive(mhi_cntrl))
634 goto err_try_reset;
635
636 err = mhi_prepare_for_power_up(mhi_cntrl);
637 if (err)
638 goto err_try_reset;
639
640 err = mhi_sync_power_up(mhi_cntrl);
641 if (err)
642 goto err_unprepare;
643
644 dev_dbg(&pdev->dev, "Recovery completed\n");
645
646 set_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status);
647 mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD);
648 return;
649
650 err_unprepare:
651 mhi_unprepare_after_power_down(mhi_cntrl);
652 err_try_reset:
653 if (pci_reset_function(pdev))
654 dev_err(&pdev->dev, "Recovery failed\n");
655 }
656
health_check(struct timer_list * t)657 static void health_check(struct timer_list *t)
658 {
659 struct mhi_pci_device *mhi_pdev = from_timer(mhi_pdev, t, health_check_timer);
660 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl;
661
662 if (!test_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status) ||
663 test_bit(MHI_PCI_DEV_SUSPENDED, &mhi_pdev->status))
664 return;
665
666 if (!mhi_pci_is_alive(mhi_cntrl)) {
667 dev_err(mhi_cntrl->cntrl_dev, "Device died\n");
668 queue_work(system_long_wq, &mhi_pdev->recovery_work);
669 return;
670 }
671
672 /* reschedule in two seconds */
673 mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD);
674 }
675
mhi_pci_probe(struct pci_dev * pdev,const struct pci_device_id * id)676 static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
677 {
678 const struct mhi_pci_dev_info *info = (struct mhi_pci_dev_info *) id->driver_data;
679 const struct mhi_controller_config *mhi_cntrl_config;
680 struct mhi_pci_device *mhi_pdev;
681 struct mhi_controller *mhi_cntrl;
682 int err;
683
684 dev_dbg(&pdev->dev, "MHI PCI device found: %s\n", info->name);
685
686 /* mhi_pdev.mhi_cntrl must be zero-initialized */
687 mhi_pdev = devm_kzalloc(&pdev->dev, sizeof(*mhi_pdev), GFP_KERNEL);
688 if (!mhi_pdev)
689 return -ENOMEM;
690
691 INIT_WORK(&mhi_pdev->recovery_work, mhi_pci_recovery_work);
692 timer_setup(&mhi_pdev->health_check_timer, health_check, 0);
693
694 mhi_cntrl_config = info->config;
695 mhi_cntrl = &mhi_pdev->mhi_cntrl;
696
697 mhi_cntrl->cntrl_dev = &pdev->dev;
698 mhi_cntrl->iova_start = 0;
699 mhi_cntrl->iova_stop = (dma_addr_t)DMA_BIT_MASK(info->dma_data_width);
700 mhi_cntrl->fw_image = info->fw;
701 mhi_cntrl->edl_image = info->edl;
702
703 mhi_cntrl->read_reg = mhi_pci_read_reg;
704 mhi_cntrl->write_reg = mhi_pci_write_reg;
705 mhi_cntrl->status_cb = mhi_pci_status_cb;
706 mhi_cntrl->runtime_get = mhi_pci_runtime_get;
707 mhi_cntrl->runtime_put = mhi_pci_runtime_put;
708 mhi_cntrl->mru = info->mru_default;
709
710 if (info->sideband_wake) {
711 mhi_cntrl->wake_get = mhi_pci_wake_get_nop;
712 mhi_cntrl->wake_put = mhi_pci_wake_put_nop;
713 mhi_cntrl->wake_toggle = mhi_pci_wake_toggle_nop;
714 }
715
716 err = mhi_pci_claim(mhi_cntrl, info->bar_num, DMA_BIT_MASK(info->dma_data_width));
717 if (err)
718 return err;
719
720 err = mhi_pci_get_irqs(mhi_cntrl, mhi_cntrl_config);
721 if (err)
722 return err;
723
724 pci_set_drvdata(pdev, mhi_pdev);
725
726 /* Have stored pci confspace at hand for restore in sudden PCI error.
727 * cache the state locally and discard the PCI core one.
728 */
729 pci_save_state(pdev);
730 mhi_pdev->pci_state = pci_store_saved_state(pdev);
731 pci_load_saved_state(pdev, NULL);
732
733 pci_enable_pcie_error_reporting(pdev);
734
735 err = mhi_register_controller(mhi_cntrl, mhi_cntrl_config);
736 if (err)
737 goto err_disable_reporting;
738
739 /* MHI bus does not power up the controller by default */
740 err = mhi_prepare_for_power_up(mhi_cntrl);
741 if (err) {
742 dev_err(&pdev->dev, "failed to prepare MHI controller\n");
743 goto err_unregister;
744 }
745
746 err = mhi_sync_power_up(mhi_cntrl);
747 if (err) {
748 dev_err(&pdev->dev, "failed to power up MHI controller\n");
749 goto err_unprepare;
750 }
751
752 set_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status);
753
754 /* start health check */
755 mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD);
756
757 /* Only allow runtime-suspend if PME capable (for wakeup) */
758 if (pci_pme_capable(pdev, PCI_D3hot)) {
759 pm_runtime_set_autosuspend_delay(&pdev->dev, 2000);
760 pm_runtime_use_autosuspend(&pdev->dev);
761 pm_runtime_mark_last_busy(&pdev->dev);
762 pm_runtime_put_noidle(&pdev->dev);
763 }
764
765 return 0;
766
767 err_unprepare:
768 mhi_unprepare_after_power_down(mhi_cntrl);
769 err_unregister:
770 mhi_unregister_controller(mhi_cntrl);
771 err_disable_reporting:
772 pci_disable_pcie_error_reporting(pdev);
773
774 return err;
775 }
776
mhi_pci_remove(struct pci_dev * pdev)777 static void mhi_pci_remove(struct pci_dev *pdev)
778 {
779 struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev);
780 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl;
781
782 del_timer_sync(&mhi_pdev->health_check_timer);
783 cancel_work_sync(&mhi_pdev->recovery_work);
784
785 if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) {
786 mhi_power_down(mhi_cntrl, true);
787 mhi_unprepare_after_power_down(mhi_cntrl);
788 }
789
790 /* balancing probe put_noidle */
791 if (pci_pme_capable(pdev, PCI_D3hot))
792 pm_runtime_get_noresume(&pdev->dev);
793
794 mhi_unregister_controller(mhi_cntrl);
795 pci_disable_pcie_error_reporting(pdev);
796 }
797
mhi_pci_shutdown(struct pci_dev * pdev)798 static void mhi_pci_shutdown(struct pci_dev *pdev)
799 {
800 mhi_pci_remove(pdev);
801 pci_set_power_state(pdev, PCI_D3hot);
802 }
803
mhi_pci_reset_prepare(struct pci_dev * pdev)804 static void mhi_pci_reset_prepare(struct pci_dev *pdev)
805 {
806 struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev);
807 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl;
808
809 dev_info(&pdev->dev, "reset\n");
810
811 del_timer(&mhi_pdev->health_check_timer);
812
813 /* Clean up MHI state */
814 if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) {
815 mhi_power_down(mhi_cntrl, false);
816 mhi_unprepare_after_power_down(mhi_cntrl);
817 }
818
819 /* cause internal device reset */
820 mhi_soc_reset(mhi_cntrl);
821
822 /* Be sure device reset has been executed */
823 msleep(MHI_POST_RESET_DELAY_MS);
824 }
825
mhi_pci_reset_done(struct pci_dev * pdev)826 static void mhi_pci_reset_done(struct pci_dev *pdev)
827 {
828 struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev);
829 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl;
830 int err;
831
832 /* Restore initial known working PCI state */
833 pci_load_saved_state(pdev, mhi_pdev->pci_state);
834 pci_restore_state(pdev);
835
836 /* Is device status available ? */
837 if (!mhi_pci_is_alive(mhi_cntrl)) {
838 dev_err(&pdev->dev, "reset failed\n");
839 return;
840 }
841
842 err = mhi_prepare_for_power_up(mhi_cntrl);
843 if (err) {
844 dev_err(&pdev->dev, "failed to prepare MHI controller\n");
845 return;
846 }
847
848 err = mhi_sync_power_up(mhi_cntrl);
849 if (err) {
850 dev_err(&pdev->dev, "failed to power up MHI controller\n");
851 mhi_unprepare_after_power_down(mhi_cntrl);
852 return;
853 }
854
855 set_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status);
856 mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD);
857 }
858
mhi_pci_error_detected(struct pci_dev * pdev,pci_channel_state_t state)859 static pci_ers_result_t mhi_pci_error_detected(struct pci_dev *pdev,
860 pci_channel_state_t state)
861 {
862 struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev);
863 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl;
864
865 dev_err(&pdev->dev, "PCI error detected, state = %u\n", state);
866
867 if (state == pci_channel_io_perm_failure)
868 return PCI_ERS_RESULT_DISCONNECT;
869
870 /* Clean up MHI state */
871 if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) {
872 mhi_power_down(mhi_cntrl, false);
873 mhi_unprepare_after_power_down(mhi_cntrl);
874 } else {
875 /* Nothing to do */
876 return PCI_ERS_RESULT_RECOVERED;
877 }
878
879 pci_disable_device(pdev);
880
881 return PCI_ERS_RESULT_NEED_RESET;
882 }
883
mhi_pci_slot_reset(struct pci_dev * pdev)884 static pci_ers_result_t mhi_pci_slot_reset(struct pci_dev *pdev)
885 {
886 if (pci_enable_device(pdev)) {
887 dev_err(&pdev->dev, "Cannot re-enable PCI device after reset.\n");
888 return PCI_ERS_RESULT_DISCONNECT;
889 }
890
891 return PCI_ERS_RESULT_RECOVERED;
892 }
893
mhi_pci_io_resume(struct pci_dev * pdev)894 static void mhi_pci_io_resume(struct pci_dev *pdev)
895 {
896 struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev);
897
898 dev_err(&pdev->dev, "PCI slot reset done\n");
899
900 queue_work(system_long_wq, &mhi_pdev->recovery_work);
901 }
902
903 static const struct pci_error_handlers mhi_pci_err_handler = {
904 .error_detected = mhi_pci_error_detected,
905 .slot_reset = mhi_pci_slot_reset,
906 .resume = mhi_pci_io_resume,
907 .reset_prepare = mhi_pci_reset_prepare,
908 .reset_done = mhi_pci_reset_done,
909 };
910
mhi_pci_runtime_suspend(struct device * dev)911 static int __maybe_unused mhi_pci_runtime_suspend(struct device *dev)
912 {
913 struct pci_dev *pdev = to_pci_dev(dev);
914 struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev);
915 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl;
916 int err;
917
918 if (test_and_set_bit(MHI_PCI_DEV_SUSPENDED, &mhi_pdev->status))
919 return 0;
920
921 del_timer(&mhi_pdev->health_check_timer);
922 cancel_work_sync(&mhi_pdev->recovery_work);
923
924 if (!test_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status) ||
925 mhi_cntrl->ee != MHI_EE_AMSS)
926 goto pci_suspend; /* Nothing to do at MHI level */
927
928 /* Transition to M3 state */
929 err = mhi_pm_suspend(mhi_cntrl);
930 if (err) {
931 dev_err(&pdev->dev, "failed to suspend device: %d\n", err);
932 clear_bit(MHI_PCI_DEV_SUSPENDED, &mhi_pdev->status);
933 return -EBUSY;
934 }
935
936 pci_suspend:
937 pci_disable_device(pdev);
938 pci_wake_from_d3(pdev, true);
939
940 return 0;
941 }
942
mhi_pci_runtime_resume(struct device * dev)943 static int __maybe_unused mhi_pci_runtime_resume(struct device *dev)
944 {
945 struct pci_dev *pdev = to_pci_dev(dev);
946 struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev);
947 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl;
948 int err;
949
950 if (!test_and_clear_bit(MHI_PCI_DEV_SUSPENDED, &mhi_pdev->status))
951 return 0;
952
953 err = pci_enable_device(pdev);
954 if (err)
955 goto err_recovery;
956
957 pci_set_master(pdev);
958 pci_wake_from_d3(pdev, false);
959
960 if (!test_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status) ||
961 mhi_cntrl->ee != MHI_EE_AMSS)
962 return 0; /* Nothing to do at MHI level */
963
964 /* Exit M3, transition to M0 state */
965 err = mhi_pm_resume(mhi_cntrl);
966 if (err) {
967 dev_err(&pdev->dev, "failed to resume device: %d\n", err);
968 goto err_recovery;
969 }
970
971 /* Resume health check */
972 mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD);
973
974 /* It can be a remote wakeup (no mhi runtime_get), update access time */
975 pm_runtime_mark_last_busy(dev);
976
977 return 0;
978
979 err_recovery:
980 /* Do not fail to not mess up our PCI device state, the device likely
981 * lost power (d3cold) and we simply need to reset it from the recovery
982 * procedure, trigger the recovery asynchronously to prevent system
983 * suspend exit delaying.
984 */
985 queue_work(system_long_wq, &mhi_pdev->recovery_work);
986 pm_runtime_mark_last_busy(dev);
987
988 return 0;
989 }
990
mhi_pci_suspend(struct device * dev)991 static int __maybe_unused mhi_pci_suspend(struct device *dev)
992 {
993 pm_runtime_disable(dev);
994 return mhi_pci_runtime_suspend(dev);
995 }
996
mhi_pci_resume(struct device * dev)997 static int __maybe_unused mhi_pci_resume(struct device *dev)
998 {
999 int ret;
1000
1001 /* Depending the platform, device may have lost power (d3cold), we need
1002 * to resume it now to check its state and recover when necessary.
1003 */
1004 ret = mhi_pci_runtime_resume(dev);
1005 pm_runtime_enable(dev);
1006
1007 return ret;
1008 }
1009
mhi_pci_freeze(struct device * dev)1010 static int __maybe_unused mhi_pci_freeze(struct device *dev)
1011 {
1012 struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev);
1013 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl;
1014
1015 /* We want to stop all operations, hibernation does not guarantee that
1016 * device will be in the same state as before freezing, especially if
1017 * the intermediate restore kernel reinitializes MHI device with new
1018 * context.
1019 */
1020 if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) {
1021 mhi_power_down(mhi_cntrl, false);
1022 mhi_unprepare_after_power_down(mhi_cntrl);
1023 }
1024
1025 return 0;
1026 }
1027
mhi_pci_restore(struct device * dev)1028 static int __maybe_unused mhi_pci_restore(struct device *dev)
1029 {
1030 struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev);
1031
1032 /* Reinitialize the device */
1033 queue_work(system_long_wq, &mhi_pdev->recovery_work);
1034
1035 return 0;
1036 }
1037
1038 static const struct dev_pm_ops mhi_pci_pm_ops = {
1039 SET_RUNTIME_PM_OPS(mhi_pci_runtime_suspend, mhi_pci_runtime_resume, NULL)
1040 #ifdef CONFIG_PM_SLEEP
1041 .suspend = mhi_pci_suspend,
1042 .resume = mhi_pci_resume,
1043 .freeze = mhi_pci_freeze,
1044 .thaw = mhi_pci_restore,
1045 .restore = mhi_pci_restore,
1046 #endif
1047 };
1048
1049 static struct pci_driver mhi_pci_driver = {
1050 .name = "mhi-pci-generic",
1051 .id_table = mhi_pci_id_table,
1052 .probe = mhi_pci_probe,
1053 .remove = mhi_pci_remove,
1054 .shutdown = mhi_pci_shutdown,
1055 .err_handler = &mhi_pci_err_handler,
1056 .driver.pm = &mhi_pci_pm_ops
1057 };
1058 module_pci_driver(mhi_pci_driver);
1059
1060 MODULE_AUTHOR("Loic Poulain <loic.poulain@linaro.org>");
1061 MODULE_DESCRIPTION("Modem Host Interface (MHI) PCI controller driver");
1062 MODULE_LICENSE("GPL");
1063