1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Clock definitions for u8500 platform.
4 *
5 * Copyright (C) 2012 ST-Ericsson SA
6 * Author: Ulf Hansson <ulf.hansson@linaro.org>
7 */
8
9 #include <linux/of.h>
10 #include <linux/of_address.h>
11 #include <linux/clk-provider.h>
12 #include <linux/mfd/dbx500-prcmu.h>
13
14 #include "clk.h"
15 #include "prcc.h"
16 #include "reset-prcc.h"
17
18 static struct clk *prcmu_clk[PRCMU_NUM_CLKS];
19 static struct clk *prcc_pclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_CLUSTER];
20 static struct clk *prcc_kclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_CLUSTER];
21
22 #define PRCC_SHOW(clk, base, bit) \
23 clk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit]
24 #define PRCC_PCLK_STORE(clk, base, bit) \
25 prcc_pclk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit] = clk
26 #define PRCC_KCLK_STORE(clk, base, bit) \
27 prcc_kclk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit] = clk
28
ux500_twocell_get(struct of_phandle_args * clkspec,void * data)29 static struct clk *ux500_twocell_get(struct of_phandle_args *clkspec,
30 void *data)
31 {
32 struct clk **clk_data = data;
33 unsigned int base, bit;
34
35 if (clkspec->args_count != 2)
36 return ERR_PTR(-EINVAL);
37
38 base = clkspec->args[0];
39 bit = clkspec->args[1];
40
41 if (base != 1 && base != 2 && base != 3 && base != 5 && base != 6) {
42 pr_err("%s: invalid PRCC base %d\n", __func__, base);
43 return ERR_PTR(-EINVAL);
44 }
45
46 return PRCC_SHOW(clk_data, base, bit);
47 }
48
u8500_clk_init(struct device_node * np)49 static void u8500_clk_init(struct device_node *np)
50 {
51 struct prcmu_fw_version *fw_version;
52 struct device_node *child = NULL;
53 const char *sgaclk_parent = NULL;
54 struct clk *clk, *rtc_clk, *twd_clk;
55 u32 bases[CLKRST_MAX];
56 struct u8500_prcc_reset *rstc;
57 int i;
58
59 /*
60 * We allocate the reset controller here so that we can fill in the
61 * base addresses properly and pass to the reset controller init
62 * function later on.
63 */
64 rstc = kzalloc(sizeof(*rstc), GFP_KERNEL);
65 if (!rstc)
66 return;
67
68 for (i = 0; i < ARRAY_SIZE(bases); i++) {
69 struct resource r;
70
71 if (of_address_to_resource(np, i, &r))
72 /* Not much choice but to continue */
73 pr_err("failed to get CLKRST %d base address\n",
74 i + 1);
75 bases[i] = r.start;
76 rstc->phy_base[i] = r.start;
77 }
78
79 /* Clock sources */
80 clk = clk_reg_prcmu_gate("soc0_pll", NULL, PRCMU_PLLSOC0,
81 CLK_IGNORE_UNUSED);
82 prcmu_clk[PRCMU_PLLSOC0] = clk;
83
84 clk = clk_reg_prcmu_gate("soc1_pll", NULL, PRCMU_PLLSOC1,
85 CLK_IGNORE_UNUSED);
86 prcmu_clk[PRCMU_PLLSOC1] = clk;
87
88 clk = clk_reg_prcmu_gate("ddr_pll", NULL, PRCMU_PLLDDR,
89 CLK_IGNORE_UNUSED);
90 prcmu_clk[PRCMU_PLLDDR] = clk;
91
92 /* FIXME: Add sys, ulp and int clocks here. */
93
94 rtc_clk = clk_register_fixed_rate(NULL, "rtc32k", "NULL",
95 CLK_IGNORE_UNUSED,
96 32768);
97
98 /* PRCMU clocks */
99 fw_version = prcmu_get_fw_version();
100 if (fw_version != NULL) {
101 switch (fw_version->project) {
102 case PRCMU_FW_PROJECT_U8500_C2:
103 case PRCMU_FW_PROJECT_U8500_SSG1:
104 case PRCMU_FW_PROJECT_U8520:
105 case PRCMU_FW_PROJECT_U8420:
106 case PRCMU_FW_PROJECT_U8420_SYSCLK:
107 case PRCMU_FW_PROJECT_U8500_SSG2:
108 sgaclk_parent = "soc0_pll";
109 break;
110 default:
111 break;
112 }
113 }
114
115 if (sgaclk_parent)
116 clk = clk_reg_prcmu_gate("sgclk", sgaclk_parent,
117 PRCMU_SGACLK, 0);
118 else
119 clk = clk_reg_prcmu_gate("sgclk", NULL, PRCMU_SGACLK, 0);
120 prcmu_clk[PRCMU_SGACLK] = clk;
121
122 clk = clk_reg_prcmu_gate("uartclk", NULL, PRCMU_UARTCLK, 0);
123 prcmu_clk[PRCMU_UARTCLK] = clk;
124
125 clk = clk_reg_prcmu_gate("msp02clk", NULL, PRCMU_MSP02CLK, 0);
126 prcmu_clk[PRCMU_MSP02CLK] = clk;
127
128 clk = clk_reg_prcmu_gate("msp1clk", NULL, PRCMU_MSP1CLK, 0);
129 prcmu_clk[PRCMU_MSP1CLK] = clk;
130
131 clk = clk_reg_prcmu_gate("i2cclk", NULL, PRCMU_I2CCLK, 0);
132 prcmu_clk[PRCMU_I2CCLK] = clk;
133
134 clk = clk_reg_prcmu_gate("slimclk", NULL, PRCMU_SLIMCLK, 0);
135 prcmu_clk[PRCMU_SLIMCLK] = clk;
136
137 clk = clk_reg_prcmu_gate("per1clk", NULL, PRCMU_PER1CLK, 0);
138 prcmu_clk[PRCMU_PER1CLK] = clk;
139
140 clk = clk_reg_prcmu_gate("per2clk", NULL, PRCMU_PER2CLK, 0);
141 prcmu_clk[PRCMU_PER2CLK] = clk;
142
143 clk = clk_reg_prcmu_gate("per3clk", NULL, PRCMU_PER3CLK, 0);
144 prcmu_clk[PRCMU_PER3CLK] = clk;
145
146 clk = clk_reg_prcmu_gate("per5clk", NULL, PRCMU_PER5CLK, 0);
147 prcmu_clk[PRCMU_PER5CLK] = clk;
148
149 clk = clk_reg_prcmu_gate("per6clk", NULL, PRCMU_PER6CLK, 0);
150 prcmu_clk[PRCMU_PER6CLK] = clk;
151
152 clk = clk_reg_prcmu_gate("per7clk", NULL, PRCMU_PER7CLK, 0);
153 prcmu_clk[PRCMU_PER7CLK] = clk;
154
155 clk = clk_reg_prcmu_scalable("lcdclk", NULL, PRCMU_LCDCLK, 0,
156 CLK_SET_RATE_GATE);
157 prcmu_clk[PRCMU_LCDCLK] = clk;
158
159 clk = clk_reg_prcmu_opp_gate("bmlclk", NULL, PRCMU_BMLCLK, 0);
160 prcmu_clk[PRCMU_BMLCLK] = clk;
161
162 clk = clk_reg_prcmu_scalable("hsitxclk", NULL, PRCMU_HSITXCLK, 0,
163 CLK_SET_RATE_GATE);
164 prcmu_clk[PRCMU_HSITXCLK] = clk;
165
166 clk = clk_reg_prcmu_scalable("hsirxclk", NULL, PRCMU_HSIRXCLK, 0,
167 CLK_SET_RATE_GATE);
168 prcmu_clk[PRCMU_HSIRXCLK] = clk;
169
170 clk = clk_reg_prcmu_scalable("hdmiclk", NULL, PRCMU_HDMICLK, 0,
171 CLK_SET_RATE_GATE);
172 prcmu_clk[PRCMU_HDMICLK] = clk;
173
174 clk = clk_reg_prcmu_gate("apeatclk", NULL, PRCMU_APEATCLK, 0);
175 prcmu_clk[PRCMU_APEATCLK] = clk;
176
177 clk = clk_reg_prcmu_scalable("apetraceclk", NULL, PRCMU_APETRACECLK, 0,
178 CLK_SET_RATE_GATE);
179 prcmu_clk[PRCMU_APETRACECLK] = clk;
180
181 clk = clk_reg_prcmu_gate("mcdeclk", NULL, PRCMU_MCDECLK, 0);
182 prcmu_clk[PRCMU_MCDECLK] = clk;
183
184 clk = clk_reg_prcmu_opp_gate("ipi2cclk", NULL, PRCMU_IPI2CCLK, 0);
185 prcmu_clk[PRCMU_IPI2CCLK] = clk;
186
187 clk = clk_reg_prcmu_gate("dsialtclk", NULL, PRCMU_DSIALTCLK, 0);
188 prcmu_clk[PRCMU_DSIALTCLK] = clk;
189
190 clk = clk_reg_prcmu_gate("dmaclk", NULL, PRCMU_DMACLK, 0);
191 prcmu_clk[PRCMU_DMACLK] = clk;
192
193 clk = clk_reg_prcmu_gate("b2r2clk", NULL, PRCMU_B2R2CLK, 0);
194 prcmu_clk[PRCMU_B2R2CLK] = clk;
195
196 clk = clk_reg_prcmu_scalable("tvclk", NULL, PRCMU_TVCLK, 0,
197 CLK_SET_RATE_GATE);
198 prcmu_clk[PRCMU_TVCLK] = clk;
199
200 clk = clk_reg_prcmu_gate("sspclk", NULL, PRCMU_SSPCLK, 0);
201 prcmu_clk[PRCMU_SSPCLK] = clk;
202
203 clk = clk_reg_prcmu_gate("rngclk", NULL, PRCMU_RNGCLK, 0);
204 prcmu_clk[PRCMU_RNGCLK] = clk;
205
206 clk = clk_reg_prcmu_gate("uiccclk", NULL, PRCMU_UICCCLK, 0);
207 prcmu_clk[PRCMU_UICCCLK] = clk;
208
209 clk = clk_reg_prcmu_gate("timclk", NULL, PRCMU_TIMCLK, 0);
210 prcmu_clk[PRCMU_TIMCLK] = clk;
211
212 clk = clk_reg_prcmu_gate("ab8500_sysclk", NULL, PRCMU_SYSCLK, 0);
213 prcmu_clk[PRCMU_SYSCLK] = clk;
214
215 clk = clk_reg_prcmu_opp_volt_scalable("sdmmcclk", NULL, PRCMU_SDMMCCLK,
216 100000000, CLK_SET_RATE_GATE);
217 prcmu_clk[PRCMU_SDMMCCLK] = clk;
218
219 clk = clk_reg_prcmu_scalable("dsi_pll", "hdmiclk",
220 PRCMU_PLLDSI, 0, CLK_SET_RATE_GATE);
221 prcmu_clk[PRCMU_PLLDSI] = clk;
222
223 clk = clk_reg_prcmu_scalable("dsi0clk", "dsi_pll",
224 PRCMU_DSI0CLK, 0, CLK_SET_RATE_GATE);
225 prcmu_clk[PRCMU_DSI0CLK] = clk;
226
227 clk = clk_reg_prcmu_scalable("dsi1clk", "dsi_pll",
228 PRCMU_DSI1CLK, 0, CLK_SET_RATE_GATE);
229 prcmu_clk[PRCMU_DSI1CLK] = clk;
230
231 clk = clk_reg_prcmu_scalable("dsi0escclk", "tvclk",
232 PRCMU_DSI0ESCCLK, 0, CLK_SET_RATE_GATE);
233 prcmu_clk[PRCMU_DSI0ESCCLK] = clk;
234
235 clk = clk_reg_prcmu_scalable("dsi1escclk", "tvclk",
236 PRCMU_DSI1ESCCLK, 0, CLK_SET_RATE_GATE);
237 prcmu_clk[PRCMU_DSI1ESCCLK] = clk;
238
239 clk = clk_reg_prcmu_scalable("dsi2escclk", "tvclk",
240 PRCMU_DSI2ESCCLK, 0, CLK_SET_RATE_GATE);
241 prcmu_clk[PRCMU_DSI2ESCCLK] = clk;
242
243 clk = clk_reg_prcmu_scalable_rate("armss", NULL,
244 PRCMU_ARMSS, 0, CLK_IGNORE_UNUSED);
245 prcmu_clk[PRCMU_ARMSS] = clk;
246
247 twd_clk = clk_register_fixed_factor(NULL, "smp_twd", "armss",
248 CLK_IGNORE_UNUSED, 1, 2);
249
250 /*
251 * FIXME: Add special handled PRCMU clocks here:
252 * 1. clkout0yuv, use PRCMU as parent + need regulator + pinctrl.
253 * 2. ab9540_clkout1yuv, see clkout0yuv
254 */
255
256 /* PRCC P-clocks */
257 clk = clk_reg_prcc_pclk("p1_pclk0", "per1clk", bases[CLKRST1_INDEX],
258 BIT(0), 0);
259 PRCC_PCLK_STORE(clk, 1, 0);
260
261 clk = clk_reg_prcc_pclk("p1_pclk1", "per1clk", bases[CLKRST1_INDEX],
262 BIT(1), 0);
263 PRCC_PCLK_STORE(clk, 1, 1);
264
265 clk = clk_reg_prcc_pclk("p1_pclk2", "per1clk", bases[CLKRST1_INDEX],
266 BIT(2), 0);
267 PRCC_PCLK_STORE(clk, 1, 2);
268
269 clk = clk_reg_prcc_pclk("p1_pclk3", "per1clk", bases[CLKRST1_INDEX],
270 BIT(3), 0);
271 PRCC_PCLK_STORE(clk, 1, 3);
272
273 clk = clk_reg_prcc_pclk("p1_pclk4", "per1clk", bases[CLKRST1_INDEX],
274 BIT(4), 0);
275 PRCC_PCLK_STORE(clk, 1, 4);
276
277 clk = clk_reg_prcc_pclk("p1_pclk5", "per1clk", bases[CLKRST1_INDEX],
278 BIT(5), 0);
279 PRCC_PCLK_STORE(clk, 1, 5);
280
281 clk = clk_reg_prcc_pclk("p1_pclk6", "per1clk", bases[CLKRST1_INDEX],
282 BIT(6), 0);
283 PRCC_PCLK_STORE(clk, 1, 6);
284
285 clk = clk_reg_prcc_pclk("p1_pclk7", "per1clk", bases[CLKRST1_INDEX],
286 BIT(7), 0);
287 PRCC_PCLK_STORE(clk, 1, 7);
288
289 clk = clk_reg_prcc_pclk("p1_pclk8", "per1clk", bases[CLKRST1_INDEX],
290 BIT(8), 0);
291 PRCC_PCLK_STORE(clk, 1, 8);
292
293 clk = clk_reg_prcc_pclk("p1_pclk9", "per1clk", bases[CLKRST1_INDEX],
294 BIT(9), 0);
295 PRCC_PCLK_STORE(clk, 1, 9);
296
297 clk = clk_reg_prcc_pclk("p1_pclk10", "per1clk", bases[CLKRST1_INDEX],
298 BIT(10), 0);
299 PRCC_PCLK_STORE(clk, 1, 10);
300
301 clk = clk_reg_prcc_pclk("p1_pclk11", "per1clk", bases[CLKRST1_INDEX],
302 BIT(11), 0);
303 PRCC_PCLK_STORE(clk, 1, 11);
304
305 clk = clk_reg_prcc_pclk("p2_pclk0", "per2clk", bases[CLKRST2_INDEX],
306 BIT(0), 0);
307 PRCC_PCLK_STORE(clk, 2, 0);
308
309 clk = clk_reg_prcc_pclk("p2_pclk1", "per2clk", bases[CLKRST2_INDEX],
310 BIT(1), 0);
311 PRCC_PCLK_STORE(clk, 2, 1);
312
313 clk = clk_reg_prcc_pclk("p2_pclk2", "per2clk", bases[CLKRST2_INDEX],
314 BIT(2), 0);
315 PRCC_PCLK_STORE(clk, 2, 2);
316
317 clk = clk_reg_prcc_pclk("p2_pclk3", "per2clk", bases[CLKRST2_INDEX],
318 BIT(3), 0);
319 PRCC_PCLK_STORE(clk, 2, 3);
320
321 clk = clk_reg_prcc_pclk("p2_pclk4", "per2clk", bases[CLKRST2_INDEX],
322 BIT(4), 0);
323 PRCC_PCLK_STORE(clk, 2, 4);
324
325 clk = clk_reg_prcc_pclk("p2_pclk5", "per2clk", bases[CLKRST2_INDEX],
326 BIT(5), 0);
327 PRCC_PCLK_STORE(clk, 2, 5);
328
329 clk = clk_reg_prcc_pclk("p2_pclk6", "per2clk", bases[CLKRST2_INDEX],
330 BIT(6), 0);
331 PRCC_PCLK_STORE(clk, 2, 6);
332
333 clk = clk_reg_prcc_pclk("p2_pclk7", "per2clk", bases[CLKRST2_INDEX],
334 BIT(7), 0);
335 PRCC_PCLK_STORE(clk, 2, 7);
336
337 clk = clk_reg_prcc_pclk("p2_pclk8", "per2clk", bases[CLKRST2_INDEX],
338 BIT(8), 0);
339 PRCC_PCLK_STORE(clk, 2, 8);
340
341 clk = clk_reg_prcc_pclk("p2_pclk9", "per2clk", bases[CLKRST2_INDEX],
342 BIT(9), 0);
343 PRCC_PCLK_STORE(clk, 2, 9);
344
345 clk = clk_reg_prcc_pclk("p2_pclk10", "per2clk", bases[CLKRST2_INDEX],
346 BIT(10), 0);
347 PRCC_PCLK_STORE(clk, 2, 10);
348
349 clk = clk_reg_prcc_pclk("p2_pclk11", "per2clk", bases[CLKRST2_INDEX],
350 BIT(11), 0);
351 PRCC_PCLK_STORE(clk, 2, 11);
352
353 clk = clk_reg_prcc_pclk("p2_pclk12", "per2clk", bases[CLKRST2_INDEX],
354 BIT(12), 0);
355 PRCC_PCLK_STORE(clk, 2, 12);
356
357 clk = clk_reg_prcc_pclk("p3_pclk0", "per3clk", bases[CLKRST3_INDEX],
358 BIT(0), 0);
359 PRCC_PCLK_STORE(clk, 3, 0);
360
361 clk = clk_reg_prcc_pclk("p3_pclk1", "per3clk", bases[CLKRST3_INDEX],
362 BIT(1), 0);
363 PRCC_PCLK_STORE(clk, 3, 1);
364
365 clk = clk_reg_prcc_pclk("p3_pclk2", "per3clk", bases[CLKRST3_INDEX],
366 BIT(2), 0);
367 PRCC_PCLK_STORE(clk, 3, 2);
368
369 clk = clk_reg_prcc_pclk("p3_pclk3", "per3clk", bases[CLKRST3_INDEX],
370 BIT(3), 0);
371 PRCC_PCLK_STORE(clk, 3, 3);
372
373 clk = clk_reg_prcc_pclk("p3_pclk4", "per3clk", bases[CLKRST3_INDEX],
374 BIT(4), 0);
375 PRCC_PCLK_STORE(clk, 3, 4);
376
377 clk = clk_reg_prcc_pclk("p3_pclk5", "per3clk", bases[CLKRST3_INDEX],
378 BIT(5), 0);
379 PRCC_PCLK_STORE(clk, 3, 5);
380
381 clk = clk_reg_prcc_pclk("p3_pclk6", "per3clk", bases[CLKRST3_INDEX],
382 BIT(6), 0);
383 PRCC_PCLK_STORE(clk, 3, 6);
384
385 clk = clk_reg_prcc_pclk("p3_pclk7", "per3clk", bases[CLKRST3_INDEX],
386 BIT(7), 0);
387 PRCC_PCLK_STORE(clk, 3, 7);
388
389 clk = clk_reg_prcc_pclk("p3_pclk8", "per3clk", bases[CLKRST3_INDEX],
390 BIT(8), 0);
391 PRCC_PCLK_STORE(clk, 3, 8);
392
393 clk = clk_reg_prcc_pclk("p5_pclk0", "per5clk", bases[CLKRST5_INDEX],
394 BIT(0), 0);
395 PRCC_PCLK_STORE(clk, 5, 0);
396
397 clk = clk_reg_prcc_pclk("p5_pclk1", "per5clk", bases[CLKRST5_INDEX],
398 BIT(1), 0);
399 PRCC_PCLK_STORE(clk, 5, 1);
400
401 clk = clk_reg_prcc_pclk("p6_pclk0", "per6clk", bases[CLKRST6_INDEX],
402 BIT(0), 0);
403 PRCC_PCLK_STORE(clk, 6, 0);
404
405 clk = clk_reg_prcc_pclk("p6_pclk1", "per6clk", bases[CLKRST6_INDEX],
406 BIT(1), 0);
407 PRCC_PCLK_STORE(clk, 6, 1);
408
409 clk = clk_reg_prcc_pclk("p6_pclk2", "per6clk", bases[CLKRST6_INDEX],
410 BIT(2), 0);
411 PRCC_PCLK_STORE(clk, 6, 2);
412
413 clk = clk_reg_prcc_pclk("p6_pclk3", "per6clk", bases[CLKRST6_INDEX],
414 BIT(3), 0);
415 PRCC_PCLK_STORE(clk, 6, 3);
416
417 clk = clk_reg_prcc_pclk("p6_pclk4", "per6clk", bases[CLKRST6_INDEX],
418 BIT(4), 0);
419 PRCC_PCLK_STORE(clk, 6, 4);
420
421 clk = clk_reg_prcc_pclk("p6_pclk5", "per6clk", bases[CLKRST6_INDEX],
422 BIT(5), 0);
423 PRCC_PCLK_STORE(clk, 6, 5);
424
425 clk = clk_reg_prcc_pclk("p6_pclk6", "per6clk", bases[CLKRST6_INDEX],
426 BIT(6), 0);
427 PRCC_PCLK_STORE(clk, 6, 6);
428
429 clk = clk_reg_prcc_pclk("p6_pclk7", "per6clk", bases[CLKRST6_INDEX],
430 BIT(7), 0);
431 PRCC_PCLK_STORE(clk, 6, 7);
432
433 /* PRCC K-clocks
434 *
435 * FIXME: Some drivers requires PERPIH[n| to be automatically enabled
436 * by enabling just the K-clock, even if it is not a valid parent to
437 * the K-clock. Until drivers get fixed we might need some kind of
438 * "parent muxed join".
439 */
440
441 /* Periph1 */
442 clk = clk_reg_prcc_kclk("p1_uart0_kclk", "uartclk",
443 bases[CLKRST1_INDEX], BIT(0), CLK_SET_RATE_GATE);
444 PRCC_KCLK_STORE(clk, 1, 0);
445
446 clk = clk_reg_prcc_kclk("p1_uart1_kclk", "uartclk",
447 bases[CLKRST1_INDEX], BIT(1), CLK_SET_RATE_GATE);
448 PRCC_KCLK_STORE(clk, 1, 1);
449
450 clk = clk_reg_prcc_kclk("p1_i2c1_kclk", "i2cclk",
451 bases[CLKRST1_INDEX], BIT(2), CLK_SET_RATE_GATE);
452 PRCC_KCLK_STORE(clk, 1, 2);
453
454 clk = clk_reg_prcc_kclk("p1_msp0_kclk", "msp02clk",
455 bases[CLKRST1_INDEX], BIT(3), CLK_SET_RATE_GATE);
456 PRCC_KCLK_STORE(clk, 1, 3);
457
458 clk = clk_reg_prcc_kclk("p1_msp1_kclk", "msp1clk",
459 bases[CLKRST1_INDEX], BIT(4), CLK_SET_RATE_GATE);
460 PRCC_KCLK_STORE(clk, 1, 4);
461
462 clk = clk_reg_prcc_kclk("p1_sdi0_kclk", "sdmmcclk",
463 bases[CLKRST1_INDEX], BIT(5), CLK_SET_RATE_GATE);
464 PRCC_KCLK_STORE(clk, 1, 5);
465
466 clk = clk_reg_prcc_kclk("p1_i2c2_kclk", "i2cclk",
467 bases[CLKRST1_INDEX], BIT(6), CLK_SET_RATE_GATE);
468 PRCC_KCLK_STORE(clk, 1, 6);
469
470 clk = clk_reg_prcc_kclk("p1_slimbus0_kclk", "slimclk",
471 bases[CLKRST1_INDEX], BIT(8), CLK_SET_RATE_GATE);
472 PRCC_KCLK_STORE(clk, 1, 8);
473
474 clk = clk_reg_prcc_kclk("p1_i2c4_kclk", "i2cclk",
475 bases[CLKRST1_INDEX], BIT(9), CLK_SET_RATE_GATE);
476 PRCC_KCLK_STORE(clk, 1, 9);
477
478 clk = clk_reg_prcc_kclk("p1_msp3_kclk", "msp1clk",
479 bases[CLKRST1_INDEX], BIT(10), CLK_SET_RATE_GATE);
480 PRCC_KCLK_STORE(clk, 1, 10);
481
482 /* Periph2 */
483 clk = clk_reg_prcc_kclk("p2_i2c3_kclk", "i2cclk",
484 bases[CLKRST2_INDEX], BIT(0), CLK_SET_RATE_GATE);
485 PRCC_KCLK_STORE(clk, 2, 0);
486
487 clk = clk_reg_prcc_kclk("p2_sdi4_kclk", "sdmmcclk",
488 bases[CLKRST2_INDEX], BIT(2), CLK_SET_RATE_GATE);
489 PRCC_KCLK_STORE(clk, 2, 2);
490
491 clk = clk_reg_prcc_kclk("p2_msp2_kclk", "msp02clk",
492 bases[CLKRST2_INDEX], BIT(3), CLK_SET_RATE_GATE);
493 PRCC_KCLK_STORE(clk, 2, 3);
494
495 clk = clk_reg_prcc_kclk("p2_sdi1_kclk", "sdmmcclk",
496 bases[CLKRST2_INDEX], BIT(4), CLK_SET_RATE_GATE);
497 PRCC_KCLK_STORE(clk, 2, 4);
498
499 clk = clk_reg_prcc_kclk("p2_sdi3_kclk", "sdmmcclk",
500 bases[CLKRST2_INDEX], BIT(5), CLK_SET_RATE_GATE);
501 PRCC_KCLK_STORE(clk, 2, 5);
502
503 /* Note that rate is received from parent. */
504 clk = clk_reg_prcc_kclk("p2_ssirx_kclk", "hsirxclk",
505 bases[CLKRST2_INDEX], BIT(6),
506 CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT);
507 PRCC_KCLK_STORE(clk, 2, 6);
508
509 clk = clk_reg_prcc_kclk("p2_ssitx_kclk", "hsitxclk",
510 bases[CLKRST2_INDEX], BIT(7),
511 CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT);
512 PRCC_KCLK_STORE(clk, 2, 7);
513
514 /* Periph3 */
515 clk = clk_reg_prcc_kclk("p3_ssp0_kclk", "sspclk",
516 bases[CLKRST3_INDEX], BIT(1), CLK_SET_RATE_GATE);
517 PRCC_KCLK_STORE(clk, 3, 1);
518
519 clk = clk_reg_prcc_kclk("p3_ssp1_kclk", "sspclk",
520 bases[CLKRST3_INDEX], BIT(2), CLK_SET_RATE_GATE);
521 PRCC_KCLK_STORE(clk, 3, 2);
522
523 clk = clk_reg_prcc_kclk("p3_i2c0_kclk", "i2cclk",
524 bases[CLKRST3_INDEX], BIT(3), CLK_SET_RATE_GATE);
525 PRCC_KCLK_STORE(clk, 3, 3);
526
527 clk = clk_reg_prcc_kclk("p3_sdi2_kclk", "sdmmcclk",
528 bases[CLKRST3_INDEX], BIT(4), CLK_SET_RATE_GATE);
529 PRCC_KCLK_STORE(clk, 3, 4);
530
531 clk = clk_reg_prcc_kclk("p3_ske_kclk", "rtc32k",
532 bases[CLKRST3_INDEX], BIT(5), CLK_SET_RATE_GATE);
533 PRCC_KCLK_STORE(clk, 3, 5);
534
535 clk = clk_reg_prcc_kclk("p3_uart2_kclk", "uartclk",
536 bases[CLKRST3_INDEX], BIT(6), CLK_SET_RATE_GATE);
537 PRCC_KCLK_STORE(clk, 3, 6);
538
539 clk = clk_reg_prcc_kclk("p3_sdi5_kclk", "sdmmcclk",
540 bases[CLKRST3_INDEX], BIT(7), CLK_SET_RATE_GATE);
541 PRCC_KCLK_STORE(clk, 3, 7);
542
543 /* Periph6 */
544 clk = clk_reg_prcc_kclk("p3_rng_kclk", "rngclk",
545 bases[CLKRST6_INDEX], BIT(0), CLK_SET_RATE_GATE);
546 PRCC_KCLK_STORE(clk, 6, 0);
547
548 for_each_child_of_node(np, child) {
549 static struct clk_onecell_data clk_data;
550
551 if (of_node_name_eq(child, "prcmu-clock")) {
552 clk_data.clks = prcmu_clk;
553 clk_data.clk_num = ARRAY_SIZE(prcmu_clk);
554 of_clk_add_provider(child, of_clk_src_onecell_get, &clk_data);
555 }
556 if (of_node_name_eq(child, "prcc-periph-clock"))
557 of_clk_add_provider(child, ux500_twocell_get, prcc_pclk);
558
559 if (of_node_name_eq(child, "prcc-kernel-clock"))
560 of_clk_add_provider(child, ux500_twocell_get, prcc_kclk);
561
562 if (of_node_name_eq(child, "rtc32k-clock"))
563 of_clk_add_provider(child, of_clk_src_simple_get, rtc_clk);
564
565 if (of_node_name_eq(child, "smp-twd-clock"))
566 of_clk_add_provider(child, of_clk_src_simple_get, twd_clk);
567
568 if (of_node_name_eq(child, "prcc-reset-controller"))
569 u8500_prcc_reset_init(child, rstc);
570 }
571 }
572 CLK_OF_DECLARE(u8500_clks, "stericsson,u8500-clks", u8500_clk_init);
573