1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only) */ 2 /* Copyright(c) 2020 Intel Corporation */ 3 #ifndef ADF_GEN4_HW_CSR_DATA_H_ 4 #define ADF_GEN4_HW_CSR_DATA_H_ 5 6 #include "adf_accel_devices.h" 7 8 /* Transport access */ 9 #define ADF_BANK_INT_SRC_SEL_MASK 0x44UL 10 #define ADF_RING_CSR_RING_CONFIG 0x1000 11 #define ADF_RING_CSR_RING_LBASE 0x1040 12 #define ADF_RING_CSR_RING_UBASE 0x1080 13 #define ADF_RING_CSR_RING_HEAD 0x0C0 14 #define ADF_RING_CSR_RING_TAIL 0x100 15 #define ADF_RING_CSR_E_STAT 0x14C 16 #define ADF_RING_CSR_INT_FLAG 0x170 17 #define ADF_RING_CSR_INT_SRCSEL 0x174 18 #define ADF_RING_CSR_INT_COL_CTL 0x180 19 #define ADF_RING_CSR_INT_FLAG_AND_COL 0x184 20 #define ADF_RING_CSR_INT_COL_CTL_ENABLE 0x80000000 21 #define ADF_RING_CSR_INT_COL_EN 0x17C 22 #define ADF_RING_CSR_ADDR_OFFSET 0x100000 23 #define ADF_RING_BUNDLE_SIZE 0x2000 24 25 #define BUILD_RING_BASE_ADDR(addr, size) \ 26 ((((addr) >> 6) & (GENMASK_ULL(63, 0) << (size))) << 6) 27 #define READ_CSR_RING_HEAD(csr_base_addr, bank, ring) \ 28 ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \ 29 ADF_RING_BUNDLE_SIZE * (bank) + \ 30 ADF_RING_CSR_RING_HEAD + ((ring) << 2)) 31 #define READ_CSR_RING_TAIL(csr_base_addr, bank, ring) \ 32 ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \ 33 ADF_RING_BUNDLE_SIZE * (bank) + \ 34 ADF_RING_CSR_RING_TAIL + ((ring) << 2)) 35 #define READ_CSR_E_STAT(csr_base_addr, bank) \ 36 ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \ 37 ADF_RING_BUNDLE_SIZE * (bank) + ADF_RING_CSR_E_STAT) 38 #define WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value) \ 39 ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \ 40 ADF_RING_BUNDLE_SIZE * (bank) + \ 41 ADF_RING_CSR_RING_CONFIG + ((ring) << 2), value) 42 #define WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, value) \ 43 do { \ 44 void __iomem *_csr_base_addr = csr_base_addr; \ 45 u32 _bank = bank; \ 46 u32 _ring = ring; \ 47 dma_addr_t _value = value; \ 48 u32 l_base = 0, u_base = 0; \ 49 l_base = lower_32_bits(_value); \ 50 u_base = upper_32_bits(_value); \ 51 ADF_CSR_WR((_csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \ 52 ADF_RING_BUNDLE_SIZE * (_bank) + \ 53 ADF_RING_CSR_RING_LBASE + ((_ring) << 2), l_base); \ 54 ADF_CSR_WR((_csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \ 55 ADF_RING_BUNDLE_SIZE * (_bank) + \ 56 ADF_RING_CSR_RING_UBASE + ((_ring) << 2), u_base); \ 57 } while (0) 58 59 #define WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value) \ 60 ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \ 61 ADF_RING_BUNDLE_SIZE * (bank) + \ 62 ADF_RING_CSR_RING_HEAD + ((ring) << 2), value) 63 #define WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value) \ 64 ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \ 65 ADF_RING_BUNDLE_SIZE * (bank) + \ 66 ADF_RING_CSR_RING_TAIL + ((ring) << 2), value) 67 #define WRITE_CSR_INT_FLAG(csr_base_addr, bank, value) \ 68 ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \ 69 ADF_RING_BUNDLE_SIZE * (bank) + \ 70 ADF_RING_CSR_INT_FLAG, (value)) 71 #define WRITE_CSR_INT_SRCSEL(csr_base_addr, bank) \ 72 ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \ 73 ADF_RING_BUNDLE_SIZE * (bank) + \ 74 ADF_RING_CSR_INT_SRCSEL, ADF_BANK_INT_SRC_SEL_MASK) 75 #define WRITE_CSR_INT_COL_EN(csr_base_addr, bank, value) \ 76 ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \ 77 ADF_RING_BUNDLE_SIZE * (bank) + \ 78 ADF_RING_CSR_INT_COL_EN, (value)) 79 #define WRITE_CSR_INT_COL_CTL(csr_base_addr, bank, value) \ 80 ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \ 81 ADF_RING_BUNDLE_SIZE * (bank) + \ 82 ADF_RING_CSR_INT_COL_CTL, \ 83 ADF_RING_CSR_INT_COL_CTL_ENABLE | (value)) 84 #define WRITE_CSR_INT_FLAG_AND_COL(csr_base_addr, bank, value) \ 85 ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \ 86 ADF_RING_BUNDLE_SIZE * (bank) + \ 87 ADF_RING_CSR_INT_FLAG_AND_COL, (value)) 88 89 /* Arbiter configuration */ 90 #define ADF_RING_CSR_RING_SRV_ARB_EN 0x19C 91 92 #define WRITE_CSR_RING_SRV_ARB_EN(csr_base_addr, bank, value) \ 93 ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \ 94 ADF_RING_BUNDLE_SIZE * (bank) + \ 95 ADF_RING_CSR_RING_SRV_ARB_EN, (value)) 96 97 /* WDT timers 98 * 99 * Timeout is in cycles. Clock speed may vary across products but this 100 * value should be a few milli-seconds. 101 */ 102 #define ADF_SSM_WDT_DEFAULT_VALUE 0x200000 103 #define ADF_SSM_WDT_PKE_DEFAULT_VALUE 0x8000000 104 #define ADF_SSMWDTL_OFFSET 0x54 105 #define ADF_SSMWDTH_OFFSET 0x5C 106 #define ADF_SSMWDTPKEL_OFFSET 0x58 107 #define ADF_SSMWDTPKEH_OFFSET 0x60 108 109 void adf_gen4_set_ssm_wdtimer(struct adf_accel_dev *accel_dev); 110 void adf_gen4_init_hw_csr_ops(struct adf_hw_csr_ops *csr_ops); 111 #endif 112