1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2016-2017 NVIDIA Corporation
4 *
5 * Author: Thierry Reding <treding@nvidia.com>
6 */
7
8 #include <linux/gpio/driver.h>
9 #include <linux/interrupt.h>
10 #include <linux/irq.h>
11 #include <linux/module.h>
12 #include <linux/of_device.h>
13 #include <linux/platform_device.h>
14
15 #include <dt-bindings/gpio/tegra186-gpio.h>
16 #include <dt-bindings/gpio/tegra194-gpio.h>
17
18 /* security registers */
19 #define TEGRA186_GPIO_CTL_SCR 0x0c
20 #define TEGRA186_GPIO_CTL_SCR_SEC_WEN BIT(28)
21 #define TEGRA186_GPIO_CTL_SCR_SEC_REN BIT(27)
22
23 #define TEGRA186_GPIO_INT_ROUTE_MAPPING(p, x) (0x14 + (p) * 0x20 + (x) * 4)
24
25 /* control registers */
26 #define TEGRA186_GPIO_ENABLE_CONFIG 0x00
27 #define TEGRA186_GPIO_ENABLE_CONFIG_ENABLE BIT(0)
28 #define TEGRA186_GPIO_ENABLE_CONFIG_OUT BIT(1)
29 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_NONE (0x0 << 2)
30 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL (0x1 << 2)
31 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE (0x2 << 2)
32 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE (0x3 << 2)
33 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK (0x3 << 2)
34 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL BIT(4)
35 #define TEGRA186_GPIO_ENABLE_CONFIG_DEBOUNCE BIT(5)
36 #define TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT BIT(6)
37
38 #define TEGRA186_GPIO_DEBOUNCE_CONTROL 0x04
39 #define TEGRA186_GPIO_DEBOUNCE_CONTROL_THRESHOLD(x) ((x) & 0xff)
40
41 #define TEGRA186_GPIO_INPUT 0x08
42 #define TEGRA186_GPIO_INPUT_HIGH BIT(0)
43
44 #define TEGRA186_GPIO_OUTPUT_CONTROL 0x0c
45 #define TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED BIT(0)
46
47 #define TEGRA186_GPIO_OUTPUT_VALUE 0x10
48 #define TEGRA186_GPIO_OUTPUT_VALUE_HIGH BIT(0)
49
50 #define TEGRA186_GPIO_INTERRUPT_CLEAR 0x14
51
52 #define TEGRA186_GPIO_INTERRUPT_STATUS(x) (0x100 + (x) * 4)
53
54 struct tegra_gpio_port {
55 const char *name;
56 unsigned int bank;
57 unsigned int port;
58 unsigned int pins;
59 };
60
61 struct tegra186_pin_range {
62 unsigned int offset;
63 const char *group;
64 };
65
66 struct tegra_gpio_soc {
67 const struct tegra_gpio_port *ports;
68 unsigned int num_ports;
69 const char *name;
70 unsigned int instance;
71
72 unsigned int num_irqs_per_bank;
73
74 const struct tegra186_pin_range *pin_ranges;
75 unsigned int num_pin_ranges;
76 const char *pinmux;
77 };
78
79 struct tegra_gpio {
80 struct gpio_chip gpio;
81 struct irq_chip intc;
82 unsigned int num_irq;
83 unsigned int *irq;
84
85 const struct tegra_gpio_soc *soc;
86 unsigned int num_irqs_per_bank;
87 unsigned int num_banks;
88
89 void __iomem *secure;
90 void __iomem *base;
91 };
92
93 static const struct tegra_gpio_port *
tegra186_gpio_get_port(struct tegra_gpio * gpio,unsigned int * pin)94 tegra186_gpio_get_port(struct tegra_gpio *gpio, unsigned int *pin)
95 {
96 unsigned int start = 0, i;
97
98 for (i = 0; i < gpio->soc->num_ports; i++) {
99 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
100
101 if (*pin >= start && *pin < start + port->pins) {
102 *pin -= start;
103 return port;
104 }
105
106 start += port->pins;
107 }
108
109 return NULL;
110 }
111
tegra186_gpio_get_base(struct tegra_gpio * gpio,unsigned int pin)112 static void __iomem *tegra186_gpio_get_base(struct tegra_gpio *gpio,
113 unsigned int pin)
114 {
115 const struct tegra_gpio_port *port;
116 unsigned int offset;
117
118 port = tegra186_gpio_get_port(gpio, &pin);
119 if (!port)
120 return NULL;
121
122 offset = port->bank * 0x1000 + port->port * 0x200;
123
124 return gpio->base + offset + pin * 0x20;
125 }
126
tegra186_gpio_get_direction(struct gpio_chip * chip,unsigned int offset)127 static int tegra186_gpio_get_direction(struct gpio_chip *chip,
128 unsigned int offset)
129 {
130 struct tegra_gpio *gpio = gpiochip_get_data(chip);
131 void __iomem *base;
132 u32 value;
133
134 base = tegra186_gpio_get_base(gpio, offset);
135 if (WARN_ON(base == NULL))
136 return -ENODEV;
137
138 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
139 if (value & TEGRA186_GPIO_ENABLE_CONFIG_OUT)
140 return GPIO_LINE_DIRECTION_OUT;
141
142 return GPIO_LINE_DIRECTION_IN;
143 }
144
tegra186_gpio_direction_input(struct gpio_chip * chip,unsigned int offset)145 static int tegra186_gpio_direction_input(struct gpio_chip *chip,
146 unsigned int offset)
147 {
148 struct tegra_gpio *gpio = gpiochip_get_data(chip);
149 void __iomem *base;
150 u32 value;
151
152 base = tegra186_gpio_get_base(gpio, offset);
153 if (WARN_ON(base == NULL))
154 return -ENODEV;
155
156 value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL);
157 value |= TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED;
158 writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL);
159
160 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
161 value |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE;
162 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_OUT;
163 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
164
165 return 0;
166 }
167
tegra186_gpio_direction_output(struct gpio_chip * chip,unsigned int offset,int level)168 static int tegra186_gpio_direction_output(struct gpio_chip *chip,
169 unsigned int offset, int level)
170 {
171 struct tegra_gpio *gpio = gpiochip_get_data(chip);
172 void __iomem *base;
173 u32 value;
174
175 /* configure output level first */
176 chip->set(chip, offset, level);
177
178 base = tegra186_gpio_get_base(gpio, offset);
179 if (WARN_ON(base == NULL))
180 return -EINVAL;
181
182 /* set the direction */
183 value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL);
184 value &= ~TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED;
185 writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL);
186
187 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
188 value |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE;
189 value |= TEGRA186_GPIO_ENABLE_CONFIG_OUT;
190 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
191
192 return 0;
193 }
194
tegra186_gpio_get(struct gpio_chip * chip,unsigned int offset)195 static int tegra186_gpio_get(struct gpio_chip *chip, unsigned int offset)
196 {
197 struct tegra_gpio *gpio = gpiochip_get_data(chip);
198 void __iomem *base;
199 u32 value;
200
201 base = tegra186_gpio_get_base(gpio, offset);
202 if (WARN_ON(base == NULL))
203 return -ENODEV;
204
205 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
206 if (value & TEGRA186_GPIO_ENABLE_CONFIG_OUT)
207 value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE);
208 else
209 value = readl(base + TEGRA186_GPIO_INPUT);
210
211 return value & BIT(0);
212 }
213
tegra186_gpio_set(struct gpio_chip * chip,unsigned int offset,int level)214 static void tegra186_gpio_set(struct gpio_chip *chip, unsigned int offset,
215 int level)
216 {
217 struct tegra_gpio *gpio = gpiochip_get_data(chip);
218 void __iomem *base;
219 u32 value;
220
221 base = tegra186_gpio_get_base(gpio, offset);
222 if (WARN_ON(base == NULL))
223 return;
224
225 value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE);
226 if (level == 0)
227 value &= ~TEGRA186_GPIO_OUTPUT_VALUE_HIGH;
228 else
229 value |= TEGRA186_GPIO_OUTPUT_VALUE_HIGH;
230
231 writel(value, base + TEGRA186_GPIO_OUTPUT_VALUE);
232 }
233
tegra186_gpio_set_config(struct gpio_chip * chip,unsigned int offset,unsigned long config)234 static int tegra186_gpio_set_config(struct gpio_chip *chip,
235 unsigned int offset,
236 unsigned long config)
237 {
238 struct tegra_gpio *gpio = gpiochip_get_data(chip);
239 u32 debounce, value;
240 void __iomem *base;
241
242 base = tegra186_gpio_get_base(gpio, offset);
243 if (base == NULL)
244 return -ENXIO;
245
246 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
247 return -ENOTSUPP;
248
249 debounce = pinconf_to_config_argument(config);
250
251 /*
252 * The Tegra186 GPIO controller supports a maximum of 255 ms debounce
253 * time.
254 */
255 if (debounce > 255000)
256 return -EINVAL;
257
258 debounce = DIV_ROUND_UP(debounce, USEC_PER_MSEC);
259
260 value = TEGRA186_GPIO_DEBOUNCE_CONTROL_THRESHOLD(debounce);
261 writel(value, base + TEGRA186_GPIO_DEBOUNCE_CONTROL);
262
263 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
264 value |= TEGRA186_GPIO_ENABLE_CONFIG_DEBOUNCE;
265 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
266
267 return 0;
268 }
269
tegra186_gpio_add_pin_ranges(struct gpio_chip * chip)270 static int tegra186_gpio_add_pin_ranges(struct gpio_chip *chip)
271 {
272 struct tegra_gpio *gpio = gpiochip_get_data(chip);
273 struct pinctrl_dev *pctldev;
274 struct device_node *np;
275 unsigned int i, j;
276 int err;
277
278 if (!gpio->soc->pinmux || gpio->soc->num_pin_ranges == 0)
279 return 0;
280
281 np = of_find_compatible_node(NULL, NULL, gpio->soc->pinmux);
282 if (!np)
283 return -ENODEV;
284
285 pctldev = of_pinctrl_get(np);
286 of_node_put(np);
287 if (!pctldev)
288 return -EPROBE_DEFER;
289
290 for (i = 0; i < gpio->soc->num_pin_ranges; i++) {
291 unsigned int pin = gpio->soc->pin_ranges[i].offset, port;
292 const char *group = gpio->soc->pin_ranges[i].group;
293
294 port = pin / 8;
295 pin = pin % 8;
296
297 if (port >= gpio->soc->num_ports) {
298 dev_warn(chip->parent, "invalid port %u for %s\n",
299 port, group);
300 continue;
301 }
302
303 for (j = 0; j < port; j++)
304 pin += gpio->soc->ports[j].pins;
305
306 err = gpiochip_add_pingroup_range(chip, pctldev, pin, group);
307 if (err < 0)
308 return err;
309 }
310
311 return 0;
312 }
313
tegra186_gpio_of_xlate(struct gpio_chip * chip,const struct of_phandle_args * spec,u32 * flags)314 static int tegra186_gpio_of_xlate(struct gpio_chip *chip,
315 const struct of_phandle_args *spec,
316 u32 *flags)
317 {
318 struct tegra_gpio *gpio = gpiochip_get_data(chip);
319 unsigned int port, pin, i, offset = 0;
320
321 if (WARN_ON(chip->of_gpio_n_cells < 2))
322 return -EINVAL;
323
324 if (WARN_ON(spec->args_count < chip->of_gpio_n_cells))
325 return -EINVAL;
326
327 port = spec->args[0] / 8;
328 pin = spec->args[0] % 8;
329
330 if (port >= gpio->soc->num_ports) {
331 dev_err(chip->parent, "invalid port number: %u\n", port);
332 return -EINVAL;
333 }
334
335 for (i = 0; i < port; i++)
336 offset += gpio->soc->ports[i].pins;
337
338 if (flags)
339 *flags = spec->args[1];
340
341 return offset + pin;
342 }
343
tegra186_irq_ack(struct irq_data * data)344 static void tegra186_irq_ack(struct irq_data *data)
345 {
346 struct tegra_gpio *gpio = irq_data_get_irq_chip_data(data);
347 void __iomem *base;
348
349 base = tegra186_gpio_get_base(gpio, data->hwirq);
350 if (WARN_ON(base == NULL))
351 return;
352
353 writel(1, base + TEGRA186_GPIO_INTERRUPT_CLEAR);
354 }
355
tegra186_irq_mask(struct irq_data * data)356 static void tegra186_irq_mask(struct irq_data *data)
357 {
358 struct tegra_gpio *gpio = irq_data_get_irq_chip_data(data);
359 void __iomem *base;
360 u32 value;
361
362 base = tegra186_gpio_get_base(gpio, data->hwirq);
363 if (WARN_ON(base == NULL))
364 return;
365
366 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
367 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT;
368 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
369 }
370
tegra186_irq_unmask(struct irq_data * data)371 static void tegra186_irq_unmask(struct irq_data *data)
372 {
373 struct tegra_gpio *gpio = irq_data_get_irq_chip_data(data);
374 void __iomem *base;
375 u32 value;
376
377 base = tegra186_gpio_get_base(gpio, data->hwirq);
378 if (WARN_ON(base == NULL))
379 return;
380
381 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
382 value |= TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT;
383 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
384 }
385
tegra186_irq_set_type(struct irq_data * data,unsigned int type)386 static int tegra186_irq_set_type(struct irq_data *data, unsigned int type)
387 {
388 struct tegra_gpio *gpio = irq_data_get_irq_chip_data(data);
389 void __iomem *base;
390 u32 value;
391
392 base = tegra186_gpio_get_base(gpio, data->hwirq);
393 if (WARN_ON(base == NULL))
394 return -ENODEV;
395
396 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
397 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK;
398 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
399
400 switch (type & IRQ_TYPE_SENSE_MASK) {
401 case IRQ_TYPE_NONE:
402 break;
403
404 case IRQ_TYPE_EDGE_RISING:
405 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
406 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
407 break;
408
409 case IRQ_TYPE_EDGE_FALLING:
410 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
411 break;
412
413 case IRQ_TYPE_EDGE_BOTH:
414 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE;
415 break;
416
417 case IRQ_TYPE_LEVEL_HIGH:
418 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL;
419 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
420 break;
421
422 case IRQ_TYPE_LEVEL_LOW:
423 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL;
424 break;
425
426 default:
427 return -EINVAL;
428 }
429
430 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
431
432 if ((type & IRQ_TYPE_EDGE_BOTH) == 0)
433 irq_set_handler_locked(data, handle_level_irq);
434 else
435 irq_set_handler_locked(data, handle_edge_irq);
436
437 if (data->parent_data)
438 return irq_chip_set_type_parent(data, type);
439
440 return 0;
441 }
442
tegra186_irq_set_wake(struct irq_data * data,unsigned int on)443 static int tegra186_irq_set_wake(struct irq_data *data, unsigned int on)
444 {
445 if (data->parent_data)
446 return irq_chip_set_wake_parent(data, on);
447
448 return 0;
449 }
450
tegra186_gpio_irq(struct irq_desc * desc)451 static void tegra186_gpio_irq(struct irq_desc *desc)
452 {
453 struct tegra_gpio *gpio = irq_desc_get_handler_data(desc);
454 struct irq_domain *domain = gpio->gpio.irq.domain;
455 struct irq_chip *chip = irq_desc_get_chip(desc);
456 unsigned int parent = irq_desc_get_irq(desc);
457 unsigned int i, j, offset = 0;
458
459 chained_irq_enter(chip, desc);
460
461 for (i = 0; i < gpio->soc->num_ports; i++) {
462 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
463 unsigned int pin;
464 unsigned long value;
465 void __iomem *base;
466
467 base = gpio->base + port->bank * 0x1000 + port->port * 0x200;
468
469 /* skip ports that are not associated with this bank */
470 for (j = 0; j < gpio->num_irqs_per_bank; j++) {
471 if (parent == gpio->irq[port->bank * gpio->num_irqs_per_bank + j])
472 break;
473 }
474
475 if (j == gpio->num_irqs_per_bank)
476 goto skip;
477
478 value = readl(base + TEGRA186_GPIO_INTERRUPT_STATUS(1));
479
480 for_each_set_bit(pin, &value, port->pins) {
481 int ret = generic_handle_domain_irq(domain, offset + pin);
482 WARN_RATELIMIT(ret, "hwirq = %d", offset + pin);
483 }
484
485 skip:
486 offset += port->pins;
487 }
488
489 chained_irq_exit(chip, desc);
490 }
491
tegra186_gpio_irq_domain_translate(struct irq_domain * domain,struct irq_fwspec * fwspec,unsigned long * hwirq,unsigned int * type)492 static int tegra186_gpio_irq_domain_translate(struct irq_domain *domain,
493 struct irq_fwspec *fwspec,
494 unsigned long *hwirq,
495 unsigned int *type)
496 {
497 struct tegra_gpio *gpio = gpiochip_get_data(domain->host_data);
498 unsigned int port, pin, i, offset = 0;
499
500 if (WARN_ON(gpio->gpio.of_gpio_n_cells < 2))
501 return -EINVAL;
502
503 if (WARN_ON(fwspec->param_count < gpio->gpio.of_gpio_n_cells))
504 return -EINVAL;
505
506 port = fwspec->param[0] / 8;
507 pin = fwspec->param[0] % 8;
508
509 if (port >= gpio->soc->num_ports)
510 return -EINVAL;
511
512 for (i = 0; i < port; i++)
513 offset += gpio->soc->ports[i].pins;
514
515 *type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK;
516 *hwirq = offset + pin;
517
518 return 0;
519 }
520
tegra186_gpio_populate_parent_fwspec(struct gpio_chip * chip,unsigned int parent_hwirq,unsigned int parent_type)521 static void *tegra186_gpio_populate_parent_fwspec(struct gpio_chip *chip,
522 unsigned int parent_hwirq,
523 unsigned int parent_type)
524 {
525 struct tegra_gpio *gpio = gpiochip_get_data(chip);
526 struct irq_fwspec *fwspec;
527
528 fwspec = kmalloc(sizeof(*fwspec), GFP_KERNEL);
529 if (!fwspec)
530 return NULL;
531
532 fwspec->fwnode = chip->irq.parent_domain->fwnode;
533 fwspec->param_count = 3;
534 fwspec->param[0] = gpio->soc->instance;
535 fwspec->param[1] = parent_hwirq;
536 fwspec->param[2] = parent_type;
537
538 return fwspec;
539 }
540
tegra186_gpio_child_to_parent_hwirq(struct gpio_chip * chip,unsigned int hwirq,unsigned int type,unsigned int * parent_hwirq,unsigned int * parent_type)541 static int tegra186_gpio_child_to_parent_hwirq(struct gpio_chip *chip,
542 unsigned int hwirq,
543 unsigned int type,
544 unsigned int *parent_hwirq,
545 unsigned int *parent_type)
546 {
547 *parent_hwirq = chip->irq.child_offset_to_irq(chip, hwirq);
548 *parent_type = type;
549
550 return 0;
551 }
552
tegra186_gpio_child_offset_to_irq(struct gpio_chip * chip,unsigned int offset)553 static unsigned int tegra186_gpio_child_offset_to_irq(struct gpio_chip *chip,
554 unsigned int offset)
555 {
556 struct tegra_gpio *gpio = gpiochip_get_data(chip);
557 unsigned int i;
558
559 for (i = 0; i < gpio->soc->num_ports; i++) {
560 if (offset < gpio->soc->ports[i].pins)
561 break;
562
563 offset -= gpio->soc->ports[i].pins;
564 }
565
566 return offset + i * 8;
567 }
568
569 static const struct of_device_id tegra186_pmc_of_match[] = {
570 { .compatible = "nvidia,tegra186-pmc" },
571 { .compatible = "nvidia,tegra194-pmc" },
572 { /* sentinel */ }
573 };
574
tegra186_gpio_init_route_mapping(struct tegra_gpio * gpio)575 static void tegra186_gpio_init_route_mapping(struct tegra_gpio *gpio)
576 {
577 struct device *dev = gpio->gpio.parent;
578 unsigned int i, j;
579 u32 value;
580
581 for (i = 0; i < gpio->soc->num_ports; i++) {
582 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
583 unsigned int offset, p = port->port;
584 void __iomem *base;
585
586 base = gpio->secure + port->bank * 0x1000 + 0x800;
587
588 value = readl(base + TEGRA186_GPIO_CTL_SCR);
589
590 /*
591 * For controllers that haven't been locked down yet, make
592 * sure to program the default interrupt route mapping.
593 */
594 if ((value & TEGRA186_GPIO_CTL_SCR_SEC_REN) == 0 &&
595 (value & TEGRA186_GPIO_CTL_SCR_SEC_WEN) == 0) {
596 /*
597 * On Tegra194 and later, each pin can be routed to one or more
598 * interrupts.
599 */
600 for (j = 0; j < gpio->num_irqs_per_bank; j++) {
601 dev_dbg(dev, "programming default interrupt routing for port %s\n",
602 port->name);
603
604 offset = TEGRA186_GPIO_INT_ROUTE_MAPPING(p, j);
605
606 /*
607 * By default we only want to route GPIO pins to IRQ 0. This works
608 * only under the assumption that we're running as the host kernel
609 * and hence all GPIO pins are owned by Linux.
610 *
611 * For cases where Linux is the guest OS, the hypervisor will have
612 * to configure the interrupt routing and pass only the valid
613 * interrupts via device tree.
614 */
615 if (j == 0) {
616 value = readl(base + offset);
617 value = BIT(port->pins) - 1;
618 writel(value, base + offset);
619 }
620 }
621 }
622 }
623 }
624
tegra186_gpio_irqs_per_bank(struct tegra_gpio * gpio)625 static unsigned int tegra186_gpio_irqs_per_bank(struct tegra_gpio *gpio)
626 {
627 struct device *dev = gpio->gpio.parent;
628
629 if (gpio->num_irq > gpio->num_banks) {
630 if (gpio->num_irq % gpio->num_banks != 0)
631 goto error;
632 }
633
634 if (gpio->num_irq < gpio->num_banks)
635 goto error;
636
637 gpio->num_irqs_per_bank = gpio->num_irq / gpio->num_banks;
638
639 if (gpio->num_irqs_per_bank > gpio->soc->num_irqs_per_bank)
640 goto error;
641
642 return 0;
643
644 error:
645 dev_err(dev, "invalid number of interrupts (%u) for %u banks\n",
646 gpio->num_irq, gpio->num_banks);
647 return -EINVAL;
648 }
649
tegra186_gpio_probe(struct platform_device * pdev)650 static int tegra186_gpio_probe(struct platform_device *pdev)
651 {
652 unsigned int i, j, offset;
653 struct gpio_irq_chip *irq;
654 struct tegra_gpio *gpio;
655 struct device_node *np;
656 char **names;
657 int err;
658
659 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
660 if (!gpio)
661 return -ENOMEM;
662
663 gpio->soc = device_get_match_data(&pdev->dev);
664 gpio->gpio.label = gpio->soc->name;
665 gpio->gpio.parent = &pdev->dev;
666
667 /* count the number of banks in the controller */
668 for (i = 0; i < gpio->soc->num_ports; i++)
669 if (gpio->soc->ports[i].bank > gpio->num_banks)
670 gpio->num_banks = gpio->soc->ports[i].bank;
671
672 gpio->num_banks++;
673
674 /* get register apertures */
675 gpio->secure = devm_platform_ioremap_resource_byname(pdev, "security");
676 if (IS_ERR(gpio->secure)) {
677 gpio->secure = devm_platform_ioremap_resource(pdev, 0);
678 if (IS_ERR(gpio->secure))
679 return PTR_ERR(gpio->secure);
680 }
681
682 gpio->base = devm_platform_ioremap_resource_byname(pdev, "gpio");
683 if (IS_ERR(gpio->base)) {
684 gpio->base = devm_platform_ioremap_resource(pdev, 1);
685 if (IS_ERR(gpio->base))
686 return PTR_ERR(gpio->base);
687 }
688
689 err = platform_irq_count(pdev);
690 if (err < 0)
691 return err;
692
693 gpio->num_irq = err;
694
695 err = tegra186_gpio_irqs_per_bank(gpio);
696 if (err < 0)
697 return err;
698
699 gpio->irq = devm_kcalloc(&pdev->dev, gpio->num_irq, sizeof(*gpio->irq),
700 GFP_KERNEL);
701 if (!gpio->irq)
702 return -ENOMEM;
703
704 for (i = 0; i < gpio->num_irq; i++) {
705 err = platform_get_irq(pdev, i);
706 if (err < 0)
707 return err;
708
709 gpio->irq[i] = err;
710 }
711
712 gpio->gpio.request = gpiochip_generic_request;
713 gpio->gpio.free = gpiochip_generic_free;
714 gpio->gpio.get_direction = tegra186_gpio_get_direction;
715 gpio->gpio.direction_input = tegra186_gpio_direction_input;
716 gpio->gpio.direction_output = tegra186_gpio_direction_output;
717 gpio->gpio.get = tegra186_gpio_get;
718 gpio->gpio.set = tegra186_gpio_set;
719 gpio->gpio.set_config = tegra186_gpio_set_config;
720 gpio->gpio.add_pin_ranges = tegra186_gpio_add_pin_ranges;
721
722 gpio->gpio.base = -1;
723
724 for (i = 0; i < gpio->soc->num_ports; i++)
725 gpio->gpio.ngpio += gpio->soc->ports[i].pins;
726
727 names = devm_kcalloc(gpio->gpio.parent, gpio->gpio.ngpio,
728 sizeof(*names), GFP_KERNEL);
729 if (!names)
730 return -ENOMEM;
731
732 for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) {
733 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
734 char *name;
735
736 for (j = 0; j < port->pins; j++) {
737 name = devm_kasprintf(gpio->gpio.parent, GFP_KERNEL,
738 "P%s.%02x", port->name, j);
739 if (!name)
740 return -ENOMEM;
741
742 names[offset + j] = name;
743 }
744
745 offset += port->pins;
746 }
747
748 gpio->gpio.names = (const char * const *)names;
749
750 #if defined(CONFIG_OF_GPIO)
751 gpio->gpio.of_node = pdev->dev.of_node;
752 gpio->gpio.of_gpio_n_cells = 2;
753 gpio->gpio.of_xlate = tegra186_gpio_of_xlate;
754 #endif /* CONFIG_OF_GPIO */
755
756 gpio->intc.name = dev_name(&pdev->dev);
757 gpio->intc.irq_ack = tegra186_irq_ack;
758 gpio->intc.irq_mask = tegra186_irq_mask;
759 gpio->intc.irq_unmask = tegra186_irq_unmask;
760 gpio->intc.irq_set_type = tegra186_irq_set_type;
761 gpio->intc.irq_set_wake = tegra186_irq_set_wake;
762
763 irq = &gpio->gpio.irq;
764 irq->chip = &gpio->intc;
765 irq->fwnode = of_node_to_fwnode(pdev->dev.of_node);
766 irq->child_to_parent_hwirq = tegra186_gpio_child_to_parent_hwirq;
767 irq->populate_parent_alloc_arg = tegra186_gpio_populate_parent_fwspec;
768 irq->child_offset_to_irq = tegra186_gpio_child_offset_to_irq;
769 irq->child_irq_domain_ops.translate = tegra186_gpio_irq_domain_translate;
770 irq->handler = handle_simple_irq;
771 irq->default_type = IRQ_TYPE_NONE;
772 irq->parent_handler = tegra186_gpio_irq;
773 irq->parent_handler_data = gpio;
774 irq->num_parents = gpio->num_irq;
775
776 /*
777 * To simplify things, use a single interrupt per bank for now. Some
778 * chips support up to 8 interrupts per bank, which can be useful to
779 * distribute the load and decrease the processing latency for GPIOs
780 * but it also requires a more complicated interrupt routing than we
781 * currently program.
782 */
783 if (gpio->num_irqs_per_bank > 1) {
784 irq->parents = devm_kcalloc(&pdev->dev, gpio->num_banks,
785 sizeof(*irq->parents), GFP_KERNEL);
786 if (!irq->parents)
787 return -ENOMEM;
788
789 for (i = 0; i < gpio->num_banks; i++)
790 irq->parents[i] = gpio->irq[i * gpio->num_irqs_per_bank];
791
792 irq->num_parents = gpio->num_banks;
793 } else {
794 irq->num_parents = gpio->num_irq;
795 irq->parents = gpio->irq;
796 }
797
798 if (gpio->soc->num_irqs_per_bank > 1)
799 tegra186_gpio_init_route_mapping(gpio);
800
801 np = of_find_matching_node(NULL, tegra186_pmc_of_match);
802 if (np) {
803 irq->parent_domain = irq_find_host(np);
804 of_node_put(np);
805
806 if (!irq->parent_domain)
807 return -EPROBE_DEFER;
808 }
809
810 irq->map = devm_kcalloc(&pdev->dev, gpio->gpio.ngpio,
811 sizeof(*irq->map), GFP_KERNEL);
812 if (!irq->map)
813 return -ENOMEM;
814
815 for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) {
816 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
817
818 for (j = 0; j < port->pins; j++)
819 irq->map[offset + j] = irq->parents[port->bank];
820
821 offset += port->pins;
822 }
823
824 return devm_gpiochip_add_data(&pdev->dev, &gpio->gpio, gpio);
825 }
826
827 #define TEGRA186_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
828 [TEGRA186_MAIN_GPIO_PORT_##_name] = { \
829 .name = #_name, \
830 .bank = _bank, \
831 .port = _port, \
832 .pins = _pins, \
833 }
834
835 static const struct tegra_gpio_port tegra186_main_ports[] = {
836 TEGRA186_MAIN_GPIO_PORT( A, 2, 0, 7),
837 TEGRA186_MAIN_GPIO_PORT( B, 3, 0, 7),
838 TEGRA186_MAIN_GPIO_PORT( C, 3, 1, 7),
839 TEGRA186_MAIN_GPIO_PORT( D, 3, 2, 6),
840 TEGRA186_MAIN_GPIO_PORT( E, 2, 1, 8),
841 TEGRA186_MAIN_GPIO_PORT( F, 2, 2, 6),
842 TEGRA186_MAIN_GPIO_PORT( G, 4, 1, 6),
843 TEGRA186_MAIN_GPIO_PORT( H, 1, 0, 7),
844 TEGRA186_MAIN_GPIO_PORT( I, 0, 4, 8),
845 TEGRA186_MAIN_GPIO_PORT( J, 5, 0, 8),
846 TEGRA186_MAIN_GPIO_PORT( K, 5, 1, 1),
847 TEGRA186_MAIN_GPIO_PORT( L, 1, 1, 8),
848 TEGRA186_MAIN_GPIO_PORT( M, 5, 3, 6),
849 TEGRA186_MAIN_GPIO_PORT( N, 0, 0, 7),
850 TEGRA186_MAIN_GPIO_PORT( O, 0, 1, 4),
851 TEGRA186_MAIN_GPIO_PORT( P, 4, 0, 7),
852 TEGRA186_MAIN_GPIO_PORT( Q, 0, 2, 6),
853 TEGRA186_MAIN_GPIO_PORT( R, 0, 5, 6),
854 TEGRA186_MAIN_GPIO_PORT( T, 0, 3, 4),
855 TEGRA186_MAIN_GPIO_PORT( X, 1, 2, 8),
856 TEGRA186_MAIN_GPIO_PORT( Y, 1, 3, 7),
857 TEGRA186_MAIN_GPIO_PORT(BB, 2, 3, 2),
858 TEGRA186_MAIN_GPIO_PORT(CC, 5, 2, 4),
859 };
860
861 static const struct tegra_gpio_soc tegra186_main_soc = {
862 .num_ports = ARRAY_SIZE(tegra186_main_ports),
863 .ports = tegra186_main_ports,
864 .name = "tegra186-gpio",
865 .instance = 0,
866 .num_irqs_per_bank = 1,
867 };
868
869 #define TEGRA186_AON_GPIO_PORT(_name, _bank, _port, _pins) \
870 [TEGRA186_AON_GPIO_PORT_##_name] = { \
871 .name = #_name, \
872 .bank = _bank, \
873 .port = _port, \
874 .pins = _pins, \
875 }
876
877 static const struct tegra_gpio_port tegra186_aon_ports[] = {
878 TEGRA186_AON_GPIO_PORT( S, 0, 1, 5),
879 TEGRA186_AON_GPIO_PORT( U, 0, 2, 6),
880 TEGRA186_AON_GPIO_PORT( V, 0, 4, 8),
881 TEGRA186_AON_GPIO_PORT( W, 0, 5, 8),
882 TEGRA186_AON_GPIO_PORT( Z, 0, 7, 4),
883 TEGRA186_AON_GPIO_PORT(AA, 0, 6, 8),
884 TEGRA186_AON_GPIO_PORT(EE, 0, 3, 3),
885 TEGRA186_AON_GPIO_PORT(FF, 0, 0, 5),
886 };
887
888 static const struct tegra_gpio_soc tegra186_aon_soc = {
889 .num_ports = ARRAY_SIZE(tegra186_aon_ports),
890 .ports = tegra186_aon_ports,
891 .name = "tegra186-gpio-aon",
892 .instance = 1,
893 .num_irqs_per_bank = 1,
894 };
895
896 #define TEGRA194_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
897 [TEGRA194_MAIN_GPIO_PORT_##_name] = { \
898 .name = #_name, \
899 .bank = _bank, \
900 .port = _port, \
901 .pins = _pins, \
902 }
903
904 static const struct tegra_gpio_port tegra194_main_ports[] = {
905 TEGRA194_MAIN_GPIO_PORT( A, 1, 2, 8),
906 TEGRA194_MAIN_GPIO_PORT( B, 4, 7, 2),
907 TEGRA194_MAIN_GPIO_PORT( C, 4, 3, 8),
908 TEGRA194_MAIN_GPIO_PORT( D, 4, 4, 4),
909 TEGRA194_MAIN_GPIO_PORT( E, 4, 5, 8),
910 TEGRA194_MAIN_GPIO_PORT( F, 4, 6, 6),
911 TEGRA194_MAIN_GPIO_PORT( G, 4, 0, 8),
912 TEGRA194_MAIN_GPIO_PORT( H, 4, 1, 8),
913 TEGRA194_MAIN_GPIO_PORT( I, 4, 2, 5),
914 TEGRA194_MAIN_GPIO_PORT( J, 5, 1, 6),
915 TEGRA194_MAIN_GPIO_PORT( K, 3, 0, 8),
916 TEGRA194_MAIN_GPIO_PORT( L, 3, 1, 4),
917 TEGRA194_MAIN_GPIO_PORT( M, 2, 3, 8),
918 TEGRA194_MAIN_GPIO_PORT( N, 2, 4, 3),
919 TEGRA194_MAIN_GPIO_PORT( O, 5, 0, 6),
920 TEGRA194_MAIN_GPIO_PORT( P, 2, 5, 8),
921 TEGRA194_MAIN_GPIO_PORT( Q, 2, 6, 8),
922 TEGRA194_MAIN_GPIO_PORT( R, 2, 7, 6),
923 TEGRA194_MAIN_GPIO_PORT( S, 3, 3, 8),
924 TEGRA194_MAIN_GPIO_PORT( T, 3, 4, 8),
925 TEGRA194_MAIN_GPIO_PORT( U, 3, 5, 1),
926 TEGRA194_MAIN_GPIO_PORT( V, 1, 0, 8),
927 TEGRA194_MAIN_GPIO_PORT( W, 1, 1, 2),
928 TEGRA194_MAIN_GPIO_PORT( X, 2, 0, 8),
929 TEGRA194_MAIN_GPIO_PORT( Y, 2, 1, 8),
930 TEGRA194_MAIN_GPIO_PORT( Z, 2, 2, 8),
931 TEGRA194_MAIN_GPIO_PORT(FF, 3, 2, 2),
932 TEGRA194_MAIN_GPIO_PORT(GG, 0, 0, 2)
933 };
934
935 static const struct tegra186_pin_range tegra194_main_pin_ranges[] = {
936 { TEGRA194_MAIN_GPIO(GG, 0), "pex_l5_clkreq_n_pgg0" },
937 { TEGRA194_MAIN_GPIO(GG, 1), "pex_l5_rst_n_pgg1" },
938 };
939
940 static const struct tegra_gpio_soc tegra194_main_soc = {
941 .num_ports = ARRAY_SIZE(tegra194_main_ports),
942 .ports = tegra194_main_ports,
943 .name = "tegra194-gpio",
944 .instance = 0,
945 .num_irqs_per_bank = 8,
946 .num_pin_ranges = ARRAY_SIZE(tegra194_main_pin_ranges),
947 .pin_ranges = tegra194_main_pin_ranges,
948 .pinmux = "nvidia,tegra194-pinmux",
949 };
950
951 #define TEGRA194_AON_GPIO_PORT(_name, _bank, _port, _pins) \
952 [TEGRA194_AON_GPIO_PORT_##_name] = { \
953 .name = #_name, \
954 .bank = _bank, \
955 .port = _port, \
956 .pins = _pins, \
957 }
958
959 static const struct tegra_gpio_port tegra194_aon_ports[] = {
960 TEGRA194_AON_GPIO_PORT(AA, 0, 3, 8),
961 TEGRA194_AON_GPIO_PORT(BB, 0, 4, 4),
962 TEGRA194_AON_GPIO_PORT(CC, 0, 1, 8),
963 TEGRA194_AON_GPIO_PORT(DD, 0, 2, 3),
964 TEGRA194_AON_GPIO_PORT(EE, 0, 0, 7)
965 };
966
967 static const struct tegra_gpio_soc tegra194_aon_soc = {
968 .num_ports = ARRAY_SIZE(tegra194_aon_ports),
969 .ports = tegra194_aon_ports,
970 .name = "tegra194-gpio-aon",
971 .instance = 1,
972 .num_irqs_per_bank = 8,
973 };
974
975 static const struct of_device_id tegra186_gpio_of_match[] = {
976 {
977 .compatible = "nvidia,tegra186-gpio",
978 .data = &tegra186_main_soc
979 }, {
980 .compatible = "nvidia,tegra186-gpio-aon",
981 .data = &tegra186_aon_soc
982 }, {
983 .compatible = "nvidia,tegra194-gpio",
984 .data = &tegra194_main_soc
985 }, {
986 .compatible = "nvidia,tegra194-gpio-aon",
987 .data = &tegra194_aon_soc
988 }, {
989 /* sentinel */
990 }
991 };
992 MODULE_DEVICE_TABLE(of, tegra186_gpio_of_match);
993
994 static const struct acpi_device_id tegra186_gpio_acpi_match[] = {
995 { .id = "NVDA0108", .driver_data = (kernel_ulong_t)&tegra186_main_soc },
996 { .id = "NVDA0208", .driver_data = (kernel_ulong_t)&tegra186_aon_soc },
997 { .id = "NVDA0308", .driver_data = (kernel_ulong_t)&tegra194_main_soc },
998 { .id = "NVDA0408", .driver_data = (kernel_ulong_t)&tegra194_aon_soc },
999 {}
1000 };
1001 MODULE_DEVICE_TABLE(acpi, tegra186_gpio_acpi_match);
1002
1003 static struct platform_driver tegra186_gpio_driver = {
1004 .driver = {
1005 .name = "tegra186-gpio",
1006 .of_match_table = tegra186_gpio_of_match,
1007 .acpi_match_table = tegra186_gpio_acpi_match,
1008 },
1009 .probe = tegra186_gpio_probe,
1010 };
1011 module_platform_driver(tegra186_gpio_driver);
1012
1013 MODULE_DESCRIPTION("NVIDIA Tegra186 GPIO controller driver");
1014 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
1015 MODULE_LICENSE("GPL v2");
1016