1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <linux/delay.h>
25 #include <linux/firmware.h>
26 #include <linux/module.h>
27 #include <linux/pci.h>
28
29 #include "amdgpu.h"
30 #include "amdgpu_ucode.h"
31 #include "amdgpu_trace.h"
32
33 #include "sdma0/sdma0_4_2_offset.h"
34 #include "sdma0/sdma0_4_2_sh_mask.h"
35 #include "sdma1/sdma1_4_2_offset.h"
36 #include "sdma1/sdma1_4_2_sh_mask.h"
37 #include "sdma2/sdma2_4_2_2_offset.h"
38 #include "sdma2/sdma2_4_2_2_sh_mask.h"
39 #include "sdma3/sdma3_4_2_2_offset.h"
40 #include "sdma3/sdma3_4_2_2_sh_mask.h"
41 #include "sdma4/sdma4_4_2_2_offset.h"
42 #include "sdma4/sdma4_4_2_2_sh_mask.h"
43 #include "sdma5/sdma5_4_2_2_offset.h"
44 #include "sdma5/sdma5_4_2_2_sh_mask.h"
45 #include "sdma6/sdma6_4_2_2_offset.h"
46 #include "sdma6/sdma6_4_2_2_sh_mask.h"
47 #include "sdma7/sdma7_4_2_2_offset.h"
48 #include "sdma7/sdma7_4_2_2_sh_mask.h"
49 #include "sdma0/sdma0_4_1_default.h"
50
51 #include "soc15_common.h"
52 #include "soc15.h"
53 #include "vega10_sdma_pkt_open.h"
54
55 #include "ivsrcid/sdma0/irqsrcs_sdma0_4_0.h"
56 #include "ivsrcid/sdma1/irqsrcs_sdma1_4_0.h"
57
58 #include "amdgpu_ras.h"
59 #include "sdma_v4_4.h"
60
61 MODULE_FIRMWARE("amdgpu/vega10_sdma.bin");
62 MODULE_FIRMWARE("amdgpu/vega10_sdma1.bin");
63 MODULE_FIRMWARE("amdgpu/vega12_sdma.bin");
64 MODULE_FIRMWARE("amdgpu/vega12_sdma1.bin");
65 MODULE_FIRMWARE("amdgpu/vega20_sdma.bin");
66 MODULE_FIRMWARE("amdgpu/vega20_sdma1.bin");
67 MODULE_FIRMWARE("amdgpu/raven_sdma.bin");
68 MODULE_FIRMWARE("amdgpu/picasso_sdma.bin");
69 MODULE_FIRMWARE("amdgpu/raven2_sdma.bin");
70 MODULE_FIRMWARE("amdgpu/arcturus_sdma.bin");
71 MODULE_FIRMWARE("amdgpu/renoir_sdma.bin");
72 MODULE_FIRMWARE("amdgpu/green_sardine_sdma.bin");
73 MODULE_FIRMWARE("amdgpu/aldebaran_sdma.bin");
74
75 #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L
76 #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L
77
78 #define WREG32_SDMA(instance, offset, value) \
79 WREG32(sdma_v4_0_get_reg_offset(adev, (instance), (offset)), value)
80 #define RREG32_SDMA(instance, offset) \
81 RREG32(sdma_v4_0_get_reg_offset(adev, (instance), (offset)))
82
83 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev);
84 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev);
85 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev);
86 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev);
87 static void sdma_v4_0_set_ras_funcs(struct amdgpu_device *adev);
88
89 static const struct soc15_reg_golden golden_settings_sdma_4[] = {
90 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
91 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xff000ff0, 0x3f000100),
92 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0100, 0x00000100),
93 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
94 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_IB_CNTL, 0x800f0100, 0x00000100),
95 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
96 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003ff006, 0x0003c000),
97 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0100, 0x00000100),
98 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
99 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0100, 0x00000100),
100 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
101 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0),
102 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000),
103 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100),
104 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_IB_CNTL, 0x800f0100, 0x00000100),
105 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
106 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_IB_CNTL, 0x800f0100, 0x00000100),
107 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
108 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_POWER_CNTL, 0x003ff000, 0x0003c000),
109 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_IB_CNTL, 0x800f0100, 0x00000100),
110 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
111 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_IB_CNTL, 0x800f0100, 0x00000100),
112 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
113 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0),
114 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_WATERMK, 0xfc000000, 0x00000000)
115 };
116
117 static const struct soc15_reg_golden golden_settings_sdma_vg10[] = {
118 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),
119 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002),
120 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
121 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
122 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),
123 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002),
124 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
125 };
126
127 static const struct soc15_reg_golden golden_settings_sdma_vg12[] = {
128 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104001),
129 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001),
130 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
131 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
132 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104001),
133 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001),
134 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
135 };
136
137 static const struct soc15_reg_golden golden_settings_sdma_4_1[] = {
138 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
139 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100),
140 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100),
141 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
142 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0xfc3fffff, 0x40000051),
143 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100),
144 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
145 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100),
146 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
147 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003e0),
148 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000)
149 };
150
151 static const struct soc15_reg_golden golden_settings_sdma0_4_2_init[] = {
152 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000),
153 };
154
155 static const struct soc15_reg_golden golden_settings_sdma0_4_2[] =
156 {
157 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
158 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100),
159 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
160 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
161 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
162 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
163 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
164 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
165 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RD_BURST_CNTL, 0x0000000f, 0x00000003),
166 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
167 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000),
168 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
169 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
170 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC2_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
171 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
172 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC3_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
173 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
174 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC4_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
175 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
176 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC5_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
177 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
178 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC6_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
179 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
180 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
181 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
182 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0),
183 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
184 };
185
186 static const struct soc15_reg_golden golden_settings_sdma1_4_2[] = {
187 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
188 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100),
189 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
190 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
191 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
192 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
193 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
194 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
195 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RD_BURST_CNTL, 0x0000000f, 0x00000003),
196 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
197 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000),
198 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
199 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
200 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC2_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
201 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
202 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC3_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
203 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
204 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC4_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
205 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
206 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC5_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
207 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
208 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC6_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
209 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
210 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
211 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
212 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0),
213 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
214 };
215
216 static const struct soc15_reg_golden golden_settings_sdma_rv1[] =
217 {
218 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00000002),
219 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00000002)
220 };
221
222 static const struct soc15_reg_golden golden_settings_sdma_rv2[] =
223 {
224 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00003001),
225 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00003001)
226 };
227
228 static const struct soc15_reg_golden golden_settings_sdma_arct[] =
229 {
230 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
231 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
232 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
233 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
234 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
235 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
236 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
237 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
238 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
239 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
240 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
241 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
242 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
243 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
244 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
245 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
246 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
247 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
248 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
249 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
250 SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
251 SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
252 SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
253 SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
254 SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
255 SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
256 SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
257 SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
258 SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
259 SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
260 SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
261 SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_UTCL1_TIMEOUT, 0xffffffff, 0x00010001)
262 };
263
264 static const struct soc15_reg_golden golden_settings_sdma_aldebaran[] = {
265 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),
266 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002),
267 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
268 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),
269 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002),
270 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
271 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),
272 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002),
273 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA2_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
274 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),
275 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002),
276 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
277 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),
278 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002),
279 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
280 };
281
282 static const struct soc15_reg_golden golden_settings_sdma_4_3[] = {
283 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
284 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100),
285 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00000002),
286 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00000002),
287 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
288 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003fff07, 0x40000051),
289 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
290 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
291 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003e0),
292 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x03fbe1fe)
293 };
294
295 static const struct soc15_ras_field_entry sdma_v4_0_ras_fields[] = {
296 { "SDMA_UCODE_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
297 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_UCODE_BUF_SED),
298 0, 0,
299 },
300 { "SDMA_RB_CMD_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
301 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_RB_CMD_BUF_SED),
302 0, 0,
303 },
304 { "SDMA_IB_CMD_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
305 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_IB_CMD_BUF_SED),
306 0, 0,
307 },
308 { "SDMA_UTCL1_RD_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
309 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_UTCL1_RD_FIFO_SED),
310 0, 0,
311 },
312 { "SDMA_UTCL1_RDBST_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
313 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_UTCL1_RDBST_FIFO_SED),
314 0, 0,
315 },
316 { "SDMA_DATA_LUT_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
317 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_DATA_LUT_FIFO_SED),
318 0, 0,
319 },
320 { "SDMA_MBANK_DATA_BUF0_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
321 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF0_SED),
322 0, 0,
323 },
324 { "SDMA_MBANK_DATA_BUF1_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
325 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF1_SED),
326 0, 0,
327 },
328 { "SDMA_MBANK_DATA_BUF2_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
329 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF2_SED),
330 0, 0,
331 },
332 { "SDMA_MBANK_DATA_BUF3_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
333 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF3_SED),
334 0, 0,
335 },
336 { "SDMA_MBANK_DATA_BUF4_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
337 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF4_SED),
338 0, 0,
339 },
340 { "SDMA_MBANK_DATA_BUF5_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
341 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF5_SED),
342 0, 0,
343 },
344 { "SDMA_MBANK_DATA_BUF6_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
345 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF6_SED),
346 0, 0,
347 },
348 { "SDMA_MBANK_DATA_BUF7_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
349 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF7_SED),
350 0, 0,
351 },
352 { "SDMA_MBANK_DATA_BUF8_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
353 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF8_SED),
354 0, 0,
355 },
356 { "SDMA_MBANK_DATA_BUF9_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
357 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF9_SED),
358 0, 0,
359 },
360 { "SDMA_MBANK_DATA_BUF10_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
361 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF10_SED),
362 0, 0,
363 },
364 { "SDMA_MBANK_DATA_BUF11_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
365 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF11_SED),
366 0, 0,
367 },
368 { "SDMA_MBANK_DATA_BUF12_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
369 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF12_SED),
370 0, 0,
371 },
372 { "SDMA_MBANK_DATA_BUF13_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
373 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF13_SED),
374 0, 0,
375 },
376 { "SDMA_MBANK_DATA_BUF14_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
377 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF14_SED),
378 0, 0,
379 },
380 { "SDMA_MBANK_DATA_BUF15_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
381 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF15_SED),
382 0, 0,
383 },
384 { "SDMA_SPLIT_DAT_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
385 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_SPLIT_DAT_BUF_SED),
386 0, 0,
387 },
388 { "SDMA_MC_WR_ADDR_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
389 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MC_WR_ADDR_FIFO_SED),
390 0, 0,
391 },
392 };
393
sdma_v4_0_get_reg_offset(struct amdgpu_device * adev,u32 instance,u32 offset)394 static u32 sdma_v4_0_get_reg_offset(struct amdgpu_device *adev,
395 u32 instance, u32 offset)
396 {
397 switch (instance) {
398 case 0:
399 return (adev->reg_offset[SDMA0_HWIP][0][0] + offset);
400 case 1:
401 return (adev->reg_offset[SDMA1_HWIP][0][0] + offset);
402 case 2:
403 return (adev->reg_offset[SDMA2_HWIP][0][1] + offset);
404 case 3:
405 return (adev->reg_offset[SDMA3_HWIP][0][1] + offset);
406 case 4:
407 return (adev->reg_offset[SDMA4_HWIP][0][1] + offset);
408 case 5:
409 return (adev->reg_offset[SDMA5_HWIP][0][1] + offset);
410 case 6:
411 return (adev->reg_offset[SDMA6_HWIP][0][1] + offset);
412 case 7:
413 return (adev->reg_offset[SDMA7_HWIP][0][1] + offset);
414 default:
415 break;
416 }
417 return 0;
418 }
419
sdma_v4_0_seq_to_irq_id(int seq_num)420 static unsigned sdma_v4_0_seq_to_irq_id(int seq_num)
421 {
422 switch (seq_num) {
423 case 0:
424 return SOC15_IH_CLIENTID_SDMA0;
425 case 1:
426 return SOC15_IH_CLIENTID_SDMA1;
427 case 2:
428 return SOC15_IH_CLIENTID_SDMA2;
429 case 3:
430 return SOC15_IH_CLIENTID_SDMA3;
431 case 4:
432 return SOC15_IH_CLIENTID_SDMA4;
433 case 5:
434 return SOC15_IH_CLIENTID_SDMA5;
435 case 6:
436 return SOC15_IH_CLIENTID_SDMA6;
437 case 7:
438 return SOC15_IH_CLIENTID_SDMA7;
439 default:
440 break;
441 }
442 return -EINVAL;
443 }
444
sdma_v4_0_irq_id_to_seq(unsigned client_id)445 static int sdma_v4_0_irq_id_to_seq(unsigned client_id)
446 {
447 switch (client_id) {
448 case SOC15_IH_CLIENTID_SDMA0:
449 return 0;
450 case SOC15_IH_CLIENTID_SDMA1:
451 return 1;
452 case SOC15_IH_CLIENTID_SDMA2:
453 return 2;
454 case SOC15_IH_CLIENTID_SDMA3:
455 return 3;
456 case SOC15_IH_CLIENTID_SDMA4:
457 return 4;
458 case SOC15_IH_CLIENTID_SDMA5:
459 return 5;
460 case SOC15_IH_CLIENTID_SDMA6:
461 return 6;
462 case SOC15_IH_CLIENTID_SDMA7:
463 return 7;
464 default:
465 break;
466 }
467 return -EINVAL;
468 }
469
sdma_v4_0_init_golden_registers(struct amdgpu_device * adev)470 static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev)
471 {
472 switch (adev->ip_versions[SDMA0_HWIP][0]) {
473 case IP_VERSION(4, 0, 0):
474 soc15_program_register_sequence(adev,
475 golden_settings_sdma_4,
476 ARRAY_SIZE(golden_settings_sdma_4));
477 soc15_program_register_sequence(adev,
478 golden_settings_sdma_vg10,
479 ARRAY_SIZE(golden_settings_sdma_vg10));
480 break;
481 case IP_VERSION(4, 0, 1):
482 soc15_program_register_sequence(adev,
483 golden_settings_sdma_4,
484 ARRAY_SIZE(golden_settings_sdma_4));
485 soc15_program_register_sequence(adev,
486 golden_settings_sdma_vg12,
487 ARRAY_SIZE(golden_settings_sdma_vg12));
488 break;
489 case IP_VERSION(4, 2, 0):
490 soc15_program_register_sequence(adev,
491 golden_settings_sdma0_4_2_init,
492 ARRAY_SIZE(golden_settings_sdma0_4_2_init));
493 soc15_program_register_sequence(adev,
494 golden_settings_sdma0_4_2,
495 ARRAY_SIZE(golden_settings_sdma0_4_2));
496 soc15_program_register_sequence(adev,
497 golden_settings_sdma1_4_2,
498 ARRAY_SIZE(golden_settings_sdma1_4_2));
499 break;
500 case IP_VERSION(4, 2, 2):
501 soc15_program_register_sequence(adev,
502 golden_settings_sdma_arct,
503 ARRAY_SIZE(golden_settings_sdma_arct));
504 break;
505 case IP_VERSION(4, 4, 0):
506 soc15_program_register_sequence(adev,
507 golden_settings_sdma_aldebaran,
508 ARRAY_SIZE(golden_settings_sdma_aldebaran));
509 break;
510 case IP_VERSION(4, 1, 0):
511 case IP_VERSION(4, 1, 1):
512 soc15_program_register_sequence(adev,
513 golden_settings_sdma_4_1,
514 ARRAY_SIZE(golden_settings_sdma_4_1));
515 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
516 soc15_program_register_sequence(adev,
517 golden_settings_sdma_rv2,
518 ARRAY_SIZE(golden_settings_sdma_rv2));
519 else
520 soc15_program_register_sequence(adev,
521 golden_settings_sdma_rv1,
522 ARRAY_SIZE(golden_settings_sdma_rv1));
523 break;
524 case IP_VERSION(4, 1, 2):
525 soc15_program_register_sequence(adev,
526 golden_settings_sdma_4_3,
527 ARRAY_SIZE(golden_settings_sdma_4_3));
528 break;
529 default:
530 break;
531 }
532 }
533
sdma_v4_0_setup_ulv(struct amdgpu_device * adev)534 static void sdma_v4_0_setup_ulv(struct amdgpu_device *adev)
535 {
536 int i;
537
538 /*
539 * The only chips with SDMAv4 and ULV are VG10 and VG20.
540 * Server SKUs take a different hysteresis setting from other SKUs.
541 */
542 switch (adev->ip_versions[SDMA0_HWIP][0]) {
543 case IP_VERSION(4, 0, 0):
544 if (adev->pdev->device == 0x6860)
545 break;
546 return;
547 case IP_VERSION(4, 2, 0):
548 if (adev->pdev->device == 0x66a1)
549 break;
550 return;
551 default:
552 return;
553 }
554
555 for (i = 0; i < adev->sdma.num_instances; i++) {
556 uint32_t temp;
557
558 temp = RREG32_SDMA(i, mmSDMA0_ULV_CNTL);
559 temp = REG_SET_FIELD(temp, SDMA0_ULV_CNTL, HYSTERESIS, 0x0);
560 WREG32_SDMA(i, mmSDMA0_ULV_CNTL, temp);
561 }
562 }
563
sdma_v4_0_init_inst_ctx(struct amdgpu_sdma_instance * sdma_inst)564 static int sdma_v4_0_init_inst_ctx(struct amdgpu_sdma_instance *sdma_inst)
565 {
566 int err = 0;
567 const struct sdma_firmware_header_v1_0 *hdr;
568
569 err = amdgpu_ucode_validate(sdma_inst->fw);
570 if (err)
571 return err;
572
573 hdr = (const struct sdma_firmware_header_v1_0 *)sdma_inst->fw->data;
574 sdma_inst->fw_version = le32_to_cpu(hdr->header.ucode_version);
575 sdma_inst->feature_version = le32_to_cpu(hdr->ucode_feature_version);
576
577 if (sdma_inst->feature_version >= 20)
578 sdma_inst->burst_nop = true;
579
580 return 0;
581 }
582
sdma_v4_0_destroy_inst_ctx(struct amdgpu_device * adev)583 static void sdma_v4_0_destroy_inst_ctx(struct amdgpu_device *adev)
584 {
585 int i;
586
587 for (i = 0; i < adev->sdma.num_instances; i++) {
588 release_firmware(adev->sdma.instance[i].fw);
589 adev->sdma.instance[i].fw = NULL;
590
591 /* arcturus shares the same FW memory across
592 all SDMA isntances */
593 if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) ||
594 adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 4, 0))
595 break;
596 }
597
598 memset((void *)adev->sdma.instance, 0,
599 sizeof(struct amdgpu_sdma_instance) * AMDGPU_MAX_SDMA_INSTANCES);
600 }
601
602 /**
603 * sdma_v4_0_init_microcode - load ucode images from disk
604 *
605 * @adev: amdgpu_device pointer
606 *
607 * Use the firmware interface to load the ucode images into
608 * the driver (not loaded into hw).
609 * Returns 0 on success, error on failure.
610 */
611
612 // emulation only, won't work on real chip
613 // vega10 real chip need to use PSP to load firmware
sdma_v4_0_init_microcode(struct amdgpu_device * adev)614 static int sdma_v4_0_init_microcode(struct amdgpu_device *adev)
615 {
616 const char *chip_name;
617 char fw_name[30];
618 int err = 0, i;
619 struct amdgpu_firmware_info *info = NULL;
620 const struct common_firmware_header *header = NULL;
621
622 DRM_DEBUG("\n");
623
624 switch (adev->ip_versions[SDMA0_HWIP][0]) {
625 case IP_VERSION(4, 0, 0):
626 chip_name = "vega10";
627 break;
628 case IP_VERSION(4, 0, 1):
629 chip_name = "vega12";
630 break;
631 case IP_VERSION(4, 2, 0):
632 chip_name = "vega20";
633 break;
634 case IP_VERSION(4, 1, 0):
635 case IP_VERSION(4, 1, 1):
636 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
637 chip_name = "raven2";
638 else if (adev->apu_flags & AMD_APU_IS_PICASSO)
639 chip_name = "picasso";
640 else
641 chip_name = "raven";
642 break;
643 case IP_VERSION(4, 2, 2):
644 chip_name = "arcturus";
645 break;
646 case IP_VERSION(4, 1, 2):
647 if (adev->apu_flags & AMD_APU_IS_RENOIR)
648 chip_name = "renoir";
649 else
650 chip_name = "green_sardine";
651 break;
652 case IP_VERSION(4, 4, 0):
653 chip_name = "aldebaran";
654 break;
655 default:
656 BUG();
657 }
658
659 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
660
661 err = request_firmware(&adev->sdma.instance[0].fw, fw_name, adev->dev);
662 if (err)
663 goto out;
664
665 err = sdma_v4_0_init_inst_ctx(&adev->sdma.instance[0]);
666 if (err)
667 goto out;
668
669 for (i = 1; i < adev->sdma.num_instances; i++) {
670 if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) ||
671 adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 4, 0)) {
672 /* Acturus & Aldebaran will leverage the same FW memory
673 for every SDMA instance */
674 memcpy((void *)&adev->sdma.instance[i],
675 (void *)&adev->sdma.instance[0],
676 sizeof(struct amdgpu_sdma_instance));
677 }
678 else {
679 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma%d.bin", chip_name, i);
680
681 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
682 if (err)
683 goto out;
684
685 err = sdma_v4_0_init_inst_ctx(&adev->sdma.instance[i]);
686 if (err)
687 goto out;
688 }
689 }
690
691 DRM_DEBUG("psp_load == '%s'\n",
692 adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false");
693
694 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
695 for (i = 0; i < adev->sdma.num_instances; i++) {
696 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
697 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
698 info->fw = adev->sdma.instance[i].fw;
699 header = (const struct common_firmware_header *)info->fw->data;
700 adev->firmware.fw_size +=
701 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
702 }
703 }
704
705 out:
706 if (err) {
707 DRM_ERROR("sdma_v4_0: Failed to load firmware \"%s\"\n", fw_name);
708 sdma_v4_0_destroy_inst_ctx(adev);
709 }
710 return err;
711 }
712
713 /**
714 * sdma_v4_0_ring_get_rptr - get the current read pointer
715 *
716 * @ring: amdgpu ring pointer
717 *
718 * Get the current rptr from the hardware (VEGA10+).
719 */
sdma_v4_0_ring_get_rptr(struct amdgpu_ring * ring)720 static uint64_t sdma_v4_0_ring_get_rptr(struct amdgpu_ring *ring)
721 {
722 u64 *rptr;
723
724 /* XXX check if swapping is necessary on BE */
725 rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]);
726
727 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
728 return ((*rptr) >> 2);
729 }
730
731 /**
732 * sdma_v4_0_ring_get_wptr - get the current write pointer
733 *
734 * @ring: amdgpu ring pointer
735 *
736 * Get the current wptr from the hardware (VEGA10+).
737 */
sdma_v4_0_ring_get_wptr(struct amdgpu_ring * ring)738 static uint64_t sdma_v4_0_ring_get_wptr(struct amdgpu_ring *ring)
739 {
740 struct amdgpu_device *adev = ring->adev;
741 u64 wptr;
742
743 if (ring->use_doorbell) {
744 /* XXX check if swapping is necessary on BE */
745 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
746 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
747 } else {
748 wptr = RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI);
749 wptr = wptr << 32;
750 wptr |= RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR);
751 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n",
752 ring->me, wptr);
753 }
754
755 return wptr >> 2;
756 }
757
758 /**
759 * sdma_v4_0_ring_set_wptr - commit the write pointer
760 *
761 * @ring: amdgpu ring pointer
762 *
763 * Write the wptr back to the hardware (VEGA10+).
764 */
sdma_v4_0_ring_set_wptr(struct amdgpu_ring * ring)765 static void sdma_v4_0_ring_set_wptr(struct amdgpu_ring *ring)
766 {
767 struct amdgpu_device *adev = ring->adev;
768
769 DRM_DEBUG("Setting write pointer\n");
770 if (ring->use_doorbell) {
771 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs];
772
773 DRM_DEBUG("Using doorbell -- "
774 "wptr_offs == 0x%08x "
775 "lower_32_bits(ring->wptr) << 2 == 0x%08x "
776 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
777 ring->wptr_offs,
778 lower_32_bits(ring->wptr << 2),
779 upper_32_bits(ring->wptr << 2));
780 /* XXX check if swapping is necessary on BE */
781 WRITE_ONCE(*wb, (ring->wptr << 2));
782 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
783 ring->doorbell_index, ring->wptr << 2);
784 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
785 } else {
786 DRM_DEBUG("Not using doorbell -- "
787 "mmSDMA%i_GFX_RB_WPTR == 0x%08x "
788 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
789 ring->me,
790 lower_32_bits(ring->wptr << 2),
791 ring->me,
792 upper_32_bits(ring->wptr << 2));
793 WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR,
794 lower_32_bits(ring->wptr << 2));
795 WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI,
796 upper_32_bits(ring->wptr << 2));
797 }
798 }
799
800 /**
801 * sdma_v4_0_page_ring_get_wptr - get the current write pointer
802 *
803 * @ring: amdgpu ring pointer
804 *
805 * Get the current wptr from the hardware (VEGA10+).
806 */
sdma_v4_0_page_ring_get_wptr(struct amdgpu_ring * ring)807 static uint64_t sdma_v4_0_page_ring_get_wptr(struct amdgpu_ring *ring)
808 {
809 struct amdgpu_device *adev = ring->adev;
810 u64 wptr;
811
812 if (ring->use_doorbell) {
813 /* XXX check if swapping is necessary on BE */
814 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
815 } else {
816 wptr = RREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR_HI);
817 wptr = wptr << 32;
818 wptr |= RREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR);
819 }
820
821 return wptr >> 2;
822 }
823
824 /**
825 * sdma_v4_0_page_ring_set_wptr - commit the write pointer
826 *
827 * @ring: amdgpu ring pointer
828 *
829 * Write the wptr back to the hardware (VEGA10+).
830 */
sdma_v4_0_page_ring_set_wptr(struct amdgpu_ring * ring)831 static void sdma_v4_0_page_ring_set_wptr(struct amdgpu_ring *ring)
832 {
833 struct amdgpu_device *adev = ring->adev;
834
835 if (ring->use_doorbell) {
836 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs];
837
838 /* XXX check if swapping is necessary on BE */
839 WRITE_ONCE(*wb, (ring->wptr << 2));
840 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
841 } else {
842 uint64_t wptr = ring->wptr << 2;
843
844 WREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR,
845 lower_32_bits(wptr));
846 WREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR_HI,
847 upper_32_bits(wptr));
848 }
849 }
850
sdma_v4_0_ring_insert_nop(struct amdgpu_ring * ring,uint32_t count)851 static void sdma_v4_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
852 {
853 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
854 int i;
855
856 for (i = 0; i < count; i++)
857 if (sdma && sdma->burst_nop && (i == 0))
858 amdgpu_ring_write(ring, ring->funcs->nop |
859 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
860 else
861 amdgpu_ring_write(ring, ring->funcs->nop);
862 }
863
864 /**
865 * sdma_v4_0_ring_emit_ib - Schedule an IB on the DMA engine
866 *
867 * @ring: amdgpu ring pointer
868 * @job: job to retrieve vmid from
869 * @ib: IB object to schedule
870 * @flags: unused
871 *
872 * Schedule an IB in the DMA ring (VEGA10).
873 */
sdma_v4_0_ring_emit_ib(struct amdgpu_ring * ring,struct amdgpu_job * job,struct amdgpu_ib * ib,uint32_t flags)874 static void sdma_v4_0_ring_emit_ib(struct amdgpu_ring *ring,
875 struct amdgpu_job *job,
876 struct amdgpu_ib *ib,
877 uint32_t flags)
878 {
879 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
880
881 /* IB packet must end on a 8 DW boundary */
882 sdma_v4_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
883
884 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
885 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
886 /* base must be 32 byte aligned */
887 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
888 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
889 amdgpu_ring_write(ring, ib->length_dw);
890 amdgpu_ring_write(ring, 0);
891 amdgpu_ring_write(ring, 0);
892
893 }
894
sdma_v4_0_wait_reg_mem(struct amdgpu_ring * ring,int mem_space,int hdp,uint32_t addr0,uint32_t addr1,uint32_t ref,uint32_t mask,uint32_t inv)895 static void sdma_v4_0_wait_reg_mem(struct amdgpu_ring *ring,
896 int mem_space, int hdp,
897 uint32_t addr0, uint32_t addr1,
898 uint32_t ref, uint32_t mask,
899 uint32_t inv)
900 {
901 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
902 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(hdp) |
903 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(mem_space) |
904 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
905 if (mem_space) {
906 /* memory */
907 amdgpu_ring_write(ring, addr0);
908 amdgpu_ring_write(ring, addr1);
909 } else {
910 /* registers */
911 amdgpu_ring_write(ring, addr0 << 2);
912 amdgpu_ring_write(ring, addr1 << 2);
913 }
914 amdgpu_ring_write(ring, ref); /* reference */
915 amdgpu_ring_write(ring, mask); /* mask */
916 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
917 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(inv)); /* retry count, poll interval */
918 }
919
920 /**
921 * sdma_v4_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
922 *
923 * @ring: amdgpu ring pointer
924 *
925 * Emit an hdp flush packet on the requested DMA ring.
926 */
sdma_v4_0_ring_emit_hdp_flush(struct amdgpu_ring * ring)927 static void sdma_v4_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
928 {
929 struct amdgpu_device *adev = ring->adev;
930 u32 ref_and_mask = 0;
931 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
932
933 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me;
934
935 sdma_v4_0_wait_reg_mem(ring, 0, 1,
936 adev->nbio.funcs->get_hdp_flush_done_offset(adev),
937 adev->nbio.funcs->get_hdp_flush_req_offset(adev),
938 ref_and_mask, ref_and_mask, 10);
939 }
940
941 /**
942 * sdma_v4_0_ring_emit_fence - emit a fence on the DMA ring
943 *
944 * @ring: amdgpu ring pointer
945 * @addr: address
946 * @seq: sequence number
947 * @flags: fence related flags
948 *
949 * Add a DMA fence packet to the ring to write
950 * the fence seq number and DMA trap packet to generate
951 * an interrupt if needed (VEGA10).
952 */
sdma_v4_0_ring_emit_fence(struct amdgpu_ring * ring,u64 addr,u64 seq,unsigned flags)953 static void sdma_v4_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
954 unsigned flags)
955 {
956 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
957 /* write the fence */
958 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
959 /* zero in first two bits */
960 BUG_ON(addr & 0x3);
961 amdgpu_ring_write(ring, lower_32_bits(addr));
962 amdgpu_ring_write(ring, upper_32_bits(addr));
963 amdgpu_ring_write(ring, lower_32_bits(seq));
964
965 /* optionally write high bits as well */
966 if (write64bit) {
967 addr += 4;
968 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
969 /* zero in first two bits */
970 BUG_ON(addr & 0x3);
971 amdgpu_ring_write(ring, lower_32_bits(addr));
972 amdgpu_ring_write(ring, upper_32_bits(addr));
973 amdgpu_ring_write(ring, upper_32_bits(seq));
974 }
975
976 /* generate an interrupt */
977 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
978 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
979 }
980
981
982 /**
983 * sdma_v4_0_gfx_stop - stop the gfx async dma engines
984 *
985 * @adev: amdgpu_device pointer
986 *
987 * Stop the gfx async dma ring buffers (VEGA10).
988 */
sdma_v4_0_gfx_stop(struct amdgpu_device * adev)989 static void sdma_v4_0_gfx_stop(struct amdgpu_device *adev)
990 {
991 struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES];
992 u32 rb_cntl, ib_cntl;
993 int i, unset = 0;
994
995 for (i = 0; i < adev->sdma.num_instances; i++) {
996 sdma[i] = &adev->sdma.instance[i].ring;
997
998 if ((adev->mman.buffer_funcs_ring == sdma[i]) && unset != 1) {
999 amdgpu_ttm_set_buffer_funcs_status(adev, false);
1000 unset = 1;
1001 }
1002
1003 rb_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL);
1004 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
1005 WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl);
1006 ib_cntl = RREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL);
1007 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
1008 WREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL, ib_cntl);
1009 }
1010 }
1011
1012 /**
1013 * sdma_v4_0_rlc_stop - stop the compute async dma engines
1014 *
1015 * @adev: amdgpu_device pointer
1016 *
1017 * Stop the compute async dma queues (VEGA10).
1018 */
sdma_v4_0_rlc_stop(struct amdgpu_device * adev)1019 static void sdma_v4_0_rlc_stop(struct amdgpu_device *adev)
1020 {
1021 /* XXX todo */
1022 }
1023
1024 /**
1025 * sdma_v4_0_page_stop - stop the page async dma engines
1026 *
1027 * @adev: amdgpu_device pointer
1028 *
1029 * Stop the page async dma ring buffers (VEGA10).
1030 */
sdma_v4_0_page_stop(struct amdgpu_device * adev)1031 static void sdma_v4_0_page_stop(struct amdgpu_device *adev)
1032 {
1033 struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES];
1034 u32 rb_cntl, ib_cntl;
1035 int i;
1036 bool unset = false;
1037
1038 for (i = 0; i < adev->sdma.num_instances; i++) {
1039 sdma[i] = &adev->sdma.instance[i].page;
1040
1041 if ((adev->mman.buffer_funcs_ring == sdma[i]) &&
1042 (!unset)) {
1043 amdgpu_ttm_set_buffer_funcs_status(adev, false);
1044 unset = true;
1045 }
1046
1047 rb_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL);
1048 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL,
1049 RB_ENABLE, 0);
1050 WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl);
1051 ib_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL);
1052 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL,
1053 IB_ENABLE, 0);
1054 WREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL, ib_cntl);
1055 }
1056 }
1057
1058 /**
1059 * sdma_v4_0_ctx_switch_enable - stop the async dma engines context switch
1060 *
1061 * @adev: amdgpu_device pointer
1062 * @enable: enable/disable the DMA MEs context switch.
1063 *
1064 * Halt or unhalt the async dma engines context switch (VEGA10).
1065 */
sdma_v4_0_ctx_switch_enable(struct amdgpu_device * adev,bool enable)1066 static void sdma_v4_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
1067 {
1068 u32 f32_cntl, phase_quantum = 0;
1069 int i;
1070
1071 if (amdgpu_sdma_phase_quantum) {
1072 unsigned value = amdgpu_sdma_phase_quantum;
1073 unsigned unit = 0;
1074
1075 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
1076 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
1077 value = (value + 1) >> 1;
1078 unit++;
1079 }
1080 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
1081 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
1082 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
1083 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
1084 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
1085 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
1086 WARN_ONCE(1,
1087 "clamping sdma_phase_quantum to %uK clock cycles\n",
1088 value << unit);
1089 }
1090 phase_quantum =
1091 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
1092 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
1093 }
1094
1095 for (i = 0; i < adev->sdma.num_instances; i++) {
1096 f32_cntl = RREG32_SDMA(i, mmSDMA0_CNTL);
1097 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
1098 AUTO_CTXSW_ENABLE, enable ? 1 : 0);
1099 if (enable && amdgpu_sdma_phase_quantum) {
1100 WREG32_SDMA(i, mmSDMA0_PHASE0_QUANTUM, phase_quantum);
1101 WREG32_SDMA(i, mmSDMA0_PHASE1_QUANTUM, phase_quantum);
1102 WREG32_SDMA(i, mmSDMA0_PHASE2_QUANTUM, phase_quantum);
1103 }
1104 WREG32_SDMA(i, mmSDMA0_CNTL, f32_cntl);
1105
1106 /*
1107 * Enable SDMA utilization. Its only supported on
1108 * Arcturus for the moment and firmware version 14
1109 * and above.
1110 */
1111 if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) &&
1112 adev->sdma.instance[i].fw_version >= 14)
1113 WREG32_SDMA(i, mmSDMA0_PUB_DUMMY_REG2, enable);
1114 /* Extend page fault timeout to avoid interrupt storm */
1115 WREG32_SDMA(i, mmSDMA0_UTCL1_TIMEOUT, 0x00800080);
1116 }
1117
1118 }
1119
1120 /**
1121 * sdma_v4_0_enable - stop the async dma engines
1122 *
1123 * @adev: amdgpu_device pointer
1124 * @enable: enable/disable the DMA MEs.
1125 *
1126 * Halt or unhalt the async dma engines (VEGA10).
1127 */
sdma_v4_0_enable(struct amdgpu_device * adev,bool enable)1128 static void sdma_v4_0_enable(struct amdgpu_device *adev, bool enable)
1129 {
1130 u32 f32_cntl;
1131 int i;
1132
1133 if (!enable) {
1134 sdma_v4_0_gfx_stop(adev);
1135 sdma_v4_0_rlc_stop(adev);
1136 if (adev->sdma.has_page_queue)
1137 sdma_v4_0_page_stop(adev);
1138 }
1139
1140 for (i = 0; i < adev->sdma.num_instances; i++) {
1141 f32_cntl = RREG32_SDMA(i, mmSDMA0_F32_CNTL);
1142 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
1143 WREG32_SDMA(i, mmSDMA0_F32_CNTL, f32_cntl);
1144 }
1145 }
1146
1147 /*
1148 * sdma_v4_0_rb_cntl - get parameters for rb_cntl
1149 */
sdma_v4_0_rb_cntl(struct amdgpu_ring * ring,uint32_t rb_cntl)1150 static uint32_t sdma_v4_0_rb_cntl(struct amdgpu_ring *ring, uint32_t rb_cntl)
1151 {
1152 /* Set ring buffer size in dwords */
1153 uint32_t rb_bufsz = order_base_2(ring->ring_size / 4);
1154
1155 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
1156 #ifdef __BIG_ENDIAN
1157 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
1158 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
1159 RPTR_WRITEBACK_SWAP_ENABLE, 1);
1160 #endif
1161 return rb_cntl;
1162 }
1163
1164 /**
1165 * sdma_v4_0_gfx_resume - setup and start the async dma engines
1166 *
1167 * @adev: amdgpu_device pointer
1168 * @i: instance to resume
1169 *
1170 * Set up the gfx DMA ring buffers and enable them (VEGA10).
1171 * Returns 0 for success, error for failure.
1172 */
sdma_v4_0_gfx_resume(struct amdgpu_device * adev,unsigned int i)1173 static void sdma_v4_0_gfx_resume(struct amdgpu_device *adev, unsigned int i)
1174 {
1175 struct amdgpu_ring *ring = &adev->sdma.instance[i].ring;
1176 u32 rb_cntl, ib_cntl, wptr_poll_cntl;
1177 u32 wb_offset;
1178 u32 doorbell;
1179 u32 doorbell_offset;
1180 u64 wptr_gpu_addr;
1181
1182 wb_offset = (ring->rptr_offs * 4);
1183
1184 rb_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL);
1185 rb_cntl = sdma_v4_0_rb_cntl(ring, rb_cntl);
1186 WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl);
1187
1188 /* Initialize the ring buffer's read and write pointers */
1189 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR, 0);
1190 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_HI, 0);
1191 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR, 0);
1192 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_HI, 0);
1193
1194 /* set the wb address whether it's enabled or not */
1195 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_ADDR_HI,
1196 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
1197 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_ADDR_LO,
1198 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
1199
1200 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
1201 RPTR_WRITEBACK_ENABLE, 1);
1202
1203 WREG32_SDMA(i, mmSDMA0_GFX_RB_BASE, ring->gpu_addr >> 8);
1204 WREG32_SDMA(i, mmSDMA0_GFX_RB_BASE_HI, ring->gpu_addr >> 40);
1205
1206 ring->wptr = 0;
1207
1208 /* before programing wptr to a less value, need set minor_ptr_update first */
1209 WREG32_SDMA(i, mmSDMA0_GFX_MINOR_PTR_UPDATE, 1);
1210
1211 doorbell = RREG32_SDMA(i, mmSDMA0_GFX_DOORBELL);
1212 doorbell_offset = RREG32_SDMA(i, mmSDMA0_GFX_DOORBELL_OFFSET);
1213
1214 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE,
1215 ring->use_doorbell);
1216 doorbell_offset = REG_SET_FIELD(doorbell_offset,
1217 SDMA0_GFX_DOORBELL_OFFSET,
1218 OFFSET, ring->doorbell_index);
1219 WREG32_SDMA(i, mmSDMA0_GFX_DOORBELL, doorbell);
1220 WREG32_SDMA(i, mmSDMA0_GFX_DOORBELL_OFFSET, doorbell_offset);
1221
1222 sdma_v4_0_ring_set_wptr(ring);
1223
1224 /* set minor_ptr_update to 0 after wptr programed */
1225 WREG32_SDMA(i, mmSDMA0_GFX_MINOR_PTR_UPDATE, 0);
1226
1227 /* setup the wptr shadow polling */
1228 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
1229 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO,
1230 lower_32_bits(wptr_gpu_addr));
1231 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI,
1232 upper_32_bits(wptr_gpu_addr));
1233 wptr_poll_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL);
1234 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
1235 SDMA0_GFX_RB_WPTR_POLL_CNTL,
1236 F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0);
1237 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, wptr_poll_cntl);
1238
1239 /* enable DMA RB */
1240 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
1241 WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl);
1242
1243 ib_cntl = RREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL);
1244 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
1245 #ifdef __BIG_ENDIAN
1246 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
1247 #endif
1248 /* enable DMA IBs */
1249 WREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL, ib_cntl);
1250
1251 ring->sched.ready = true;
1252 }
1253
1254 /**
1255 * sdma_v4_0_page_resume - setup and start the async dma engines
1256 *
1257 * @adev: amdgpu_device pointer
1258 * @i: instance to resume
1259 *
1260 * Set up the page DMA ring buffers and enable them (VEGA10).
1261 * Returns 0 for success, error for failure.
1262 */
sdma_v4_0_page_resume(struct amdgpu_device * adev,unsigned int i)1263 static void sdma_v4_0_page_resume(struct amdgpu_device *adev, unsigned int i)
1264 {
1265 struct amdgpu_ring *ring = &adev->sdma.instance[i].page;
1266 u32 rb_cntl, ib_cntl, wptr_poll_cntl;
1267 u32 wb_offset;
1268 u32 doorbell;
1269 u32 doorbell_offset;
1270 u64 wptr_gpu_addr;
1271
1272 wb_offset = (ring->rptr_offs * 4);
1273
1274 rb_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL);
1275 rb_cntl = sdma_v4_0_rb_cntl(ring, rb_cntl);
1276 WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl);
1277
1278 /* Initialize the ring buffer's read and write pointers */
1279 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR, 0);
1280 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_HI, 0);
1281 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR, 0);
1282 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_HI, 0);
1283
1284 /* set the wb address whether it's enabled or not */
1285 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_ADDR_HI,
1286 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
1287 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_ADDR_LO,
1288 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
1289
1290 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL,
1291 RPTR_WRITEBACK_ENABLE, 1);
1292
1293 WREG32_SDMA(i, mmSDMA0_PAGE_RB_BASE, ring->gpu_addr >> 8);
1294 WREG32_SDMA(i, mmSDMA0_PAGE_RB_BASE_HI, ring->gpu_addr >> 40);
1295
1296 ring->wptr = 0;
1297
1298 /* before programing wptr to a less value, need set minor_ptr_update first */
1299 WREG32_SDMA(i, mmSDMA0_PAGE_MINOR_PTR_UPDATE, 1);
1300
1301 doorbell = RREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL);
1302 doorbell_offset = RREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL_OFFSET);
1303
1304 doorbell = REG_SET_FIELD(doorbell, SDMA0_PAGE_DOORBELL, ENABLE,
1305 ring->use_doorbell);
1306 doorbell_offset = REG_SET_FIELD(doorbell_offset,
1307 SDMA0_PAGE_DOORBELL_OFFSET,
1308 OFFSET, ring->doorbell_index);
1309 WREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL, doorbell);
1310 WREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL_OFFSET, doorbell_offset);
1311
1312 /* paging queue doorbell range is setup at sdma_v4_0_gfx_resume */
1313 sdma_v4_0_page_ring_set_wptr(ring);
1314
1315 /* set minor_ptr_update to 0 after wptr programed */
1316 WREG32_SDMA(i, mmSDMA0_PAGE_MINOR_PTR_UPDATE, 0);
1317
1318 /* setup the wptr shadow polling */
1319 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
1320 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO,
1321 lower_32_bits(wptr_gpu_addr));
1322 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI,
1323 upper_32_bits(wptr_gpu_addr));
1324 wptr_poll_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL);
1325 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
1326 SDMA0_PAGE_RB_WPTR_POLL_CNTL,
1327 F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0);
1328 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, wptr_poll_cntl);
1329
1330 /* enable DMA RB */
1331 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL, RB_ENABLE, 1);
1332 WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl);
1333
1334 ib_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL);
1335 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, IB_ENABLE, 1);
1336 #ifdef __BIG_ENDIAN
1337 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, IB_SWAP_ENABLE, 1);
1338 #endif
1339 /* enable DMA IBs */
1340 WREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL, ib_cntl);
1341
1342 ring->sched.ready = true;
1343 }
1344
1345 static void
sdma_v4_1_update_power_gating(struct amdgpu_device * adev,bool enable)1346 sdma_v4_1_update_power_gating(struct amdgpu_device *adev, bool enable)
1347 {
1348 uint32_t def, data;
1349
1350 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_SDMA)) {
1351 /* enable idle interrupt */
1352 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
1353 data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK;
1354
1355 if (data != def)
1356 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
1357 } else {
1358 /* disable idle interrupt */
1359 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
1360 data &= ~SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK;
1361 if (data != def)
1362 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
1363 }
1364 }
1365
sdma_v4_1_init_power_gating(struct amdgpu_device * adev)1366 static void sdma_v4_1_init_power_gating(struct amdgpu_device *adev)
1367 {
1368 uint32_t def, data;
1369
1370 /* Enable HW based PG. */
1371 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
1372 data |= SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK;
1373 if (data != def)
1374 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
1375
1376 /* enable interrupt */
1377 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
1378 data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK;
1379 if (data != def)
1380 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
1381
1382 /* Configure hold time to filter in-valid power on/off request. Use default right now */
1383 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
1384 data &= ~SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK;
1385 data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK);
1386 /* Configure switch time for hysteresis purpose. Use default right now */
1387 data &= ~SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK;
1388 data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK);
1389 if(data != def)
1390 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
1391 }
1392
sdma_v4_0_init_pg(struct amdgpu_device * adev)1393 static void sdma_v4_0_init_pg(struct amdgpu_device *adev)
1394 {
1395 if (!(adev->pg_flags & AMD_PG_SUPPORT_SDMA))
1396 return;
1397
1398 switch (adev->ip_versions[SDMA0_HWIP][0]) {
1399 case IP_VERSION(4, 1, 0):
1400 case IP_VERSION(4, 1, 1):
1401 case IP_VERSION(4, 1, 2):
1402 sdma_v4_1_init_power_gating(adev);
1403 sdma_v4_1_update_power_gating(adev, true);
1404 break;
1405 default:
1406 break;
1407 }
1408 }
1409
1410 /**
1411 * sdma_v4_0_rlc_resume - setup and start the async dma engines
1412 *
1413 * @adev: amdgpu_device pointer
1414 *
1415 * Set up the compute DMA queues and enable them (VEGA10).
1416 * Returns 0 for success, error for failure.
1417 */
sdma_v4_0_rlc_resume(struct amdgpu_device * adev)1418 static int sdma_v4_0_rlc_resume(struct amdgpu_device *adev)
1419 {
1420 sdma_v4_0_init_pg(adev);
1421
1422 return 0;
1423 }
1424
1425 /**
1426 * sdma_v4_0_load_microcode - load the sDMA ME ucode
1427 *
1428 * @adev: amdgpu_device pointer
1429 *
1430 * Loads the sDMA0/1 ucode.
1431 * Returns 0 for success, -EINVAL if the ucode is not available.
1432 */
sdma_v4_0_load_microcode(struct amdgpu_device * adev)1433 static int sdma_v4_0_load_microcode(struct amdgpu_device *adev)
1434 {
1435 const struct sdma_firmware_header_v1_0 *hdr;
1436 const __le32 *fw_data;
1437 u32 fw_size;
1438 int i, j;
1439
1440 /* halt the MEs */
1441 sdma_v4_0_enable(adev, false);
1442
1443 for (i = 0; i < adev->sdma.num_instances; i++) {
1444 if (!adev->sdma.instance[i].fw)
1445 return -EINVAL;
1446
1447 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
1448 amdgpu_ucode_print_sdma_hdr(&hdr->header);
1449 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
1450
1451 fw_data = (const __le32 *)
1452 (adev->sdma.instance[i].fw->data +
1453 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1454
1455 WREG32_SDMA(i, mmSDMA0_UCODE_ADDR, 0);
1456
1457 for (j = 0; j < fw_size; j++)
1458 WREG32_SDMA(i, mmSDMA0_UCODE_DATA,
1459 le32_to_cpup(fw_data++));
1460
1461 WREG32_SDMA(i, mmSDMA0_UCODE_ADDR,
1462 adev->sdma.instance[i].fw_version);
1463 }
1464
1465 return 0;
1466 }
1467
1468 /**
1469 * sdma_v4_0_start - setup and start the async dma engines
1470 *
1471 * @adev: amdgpu_device pointer
1472 *
1473 * Set up the DMA engines and enable them (VEGA10).
1474 * Returns 0 for success, error for failure.
1475 */
sdma_v4_0_start(struct amdgpu_device * adev)1476 static int sdma_v4_0_start(struct amdgpu_device *adev)
1477 {
1478 struct amdgpu_ring *ring;
1479 int i, r = 0;
1480
1481 if (amdgpu_sriov_vf(adev)) {
1482 sdma_v4_0_ctx_switch_enable(adev, false);
1483 sdma_v4_0_enable(adev, false);
1484 } else {
1485
1486 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1487 r = sdma_v4_0_load_microcode(adev);
1488 if (r)
1489 return r;
1490 }
1491
1492 /* unhalt the MEs */
1493 sdma_v4_0_enable(adev, true);
1494 /* enable sdma ring preemption */
1495 sdma_v4_0_ctx_switch_enable(adev, true);
1496 }
1497
1498 /* start the gfx rings and rlc compute queues */
1499 for (i = 0; i < adev->sdma.num_instances; i++) {
1500 uint32_t temp;
1501
1502 WREG32_SDMA(i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL, 0);
1503 sdma_v4_0_gfx_resume(adev, i);
1504 if (adev->sdma.has_page_queue)
1505 sdma_v4_0_page_resume(adev, i);
1506
1507 /* set utc l1 enable flag always to 1 */
1508 temp = RREG32_SDMA(i, mmSDMA0_CNTL);
1509 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
1510 WREG32_SDMA(i, mmSDMA0_CNTL, temp);
1511
1512 if (!amdgpu_sriov_vf(adev)) {
1513 /* unhalt engine */
1514 temp = RREG32_SDMA(i, mmSDMA0_F32_CNTL);
1515 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
1516 WREG32_SDMA(i, mmSDMA0_F32_CNTL, temp);
1517 }
1518 }
1519
1520 if (amdgpu_sriov_vf(adev)) {
1521 sdma_v4_0_ctx_switch_enable(adev, true);
1522 sdma_v4_0_enable(adev, true);
1523 } else {
1524 r = sdma_v4_0_rlc_resume(adev);
1525 if (r)
1526 return r;
1527 }
1528
1529 for (i = 0; i < adev->sdma.num_instances; i++) {
1530 ring = &adev->sdma.instance[i].ring;
1531
1532 r = amdgpu_ring_test_helper(ring);
1533 if (r)
1534 return r;
1535
1536 if (adev->sdma.has_page_queue) {
1537 struct amdgpu_ring *page = &adev->sdma.instance[i].page;
1538
1539 r = amdgpu_ring_test_helper(page);
1540 if (r)
1541 return r;
1542
1543 if (adev->mman.buffer_funcs_ring == page)
1544 amdgpu_ttm_set_buffer_funcs_status(adev, true);
1545 }
1546
1547 if (adev->mman.buffer_funcs_ring == ring)
1548 amdgpu_ttm_set_buffer_funcs_status(adev, true);
1549 }
1550
1551 return r;
1552 }
1553
1554 /**
1555 * sdma_v4_0_ring_test_ring - simple async dma engine test
1556 *
1557 * @ring: amdgpu_ring structure holding ring information
1558 *
1559 * Test the DMA engine by writing using it to write an
1560 * value to memory. (VEGA10).
1561 * Returns 0 for success, error for failure.
1562 */
sdma_v4_0_ring_test_ring(struct amdgpu_ring * ring)1563 static int sdma_v4_0_ring_test_ring(struct amdgpu_ring *ring)
1564 {
1565 struct amdgpu_device *adev = ring->adev;
1566 unsigned i;
1567 unsigned index;
1568 int r;
1569 u32 tmp;
1570 u64 gpu_addr;
1571
1572 r = amdgpu_device_wb_get(adev, &index);
1573 if (r)
1574 return r;
1575
1576 gpu_addr = adev->wb.gpu_addr + (index * 4);
1577 tmp = 0xCAFEDEAD;
1578 adev->wb.wb[index] = cpu_to_le32(tmp);
1579
1580 r = amdgpu_ring_alloc(ring, 5);
1581 if (r)
1582 goto error_free_wb;
1583
1584 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1585 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
1586 amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
1587 amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
1588 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
1589 amdgpu_ring_write(ring, 0xDEADBEEF);
1590 amdgpu_ring_commit(ring);
1591
1592 for (i = 0; i < adev->usec_timeout; i++) {
1593 tmp = le32_to_cpu(adev->wb.wb[index]);
1594 if (tmp == 0xDEADBEEF)
1595 break;
1596 udelay(1);
1597 }
1598
1599 if (i >= adev->usec_timeout)
1600 r = -ETIMEDOUT;
1601
1602 error_free_wb:
1603 amdgpu_device_wb_free(adev, index);
1604 return r;
1605 }
1606
1607 /**
1608 * sdma_v4_0_ring_test_ib - test an IB on the DMA engine
1609 *
1610 * @ring: amdgpu_ring structure holding ring information
1611 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
1612 *
1613 * Test a simple IB in the DMA ring (VEGA10).
1614 * Returns 0 on success, error on failure.
1615 */
sdma_v4_0_ring_test_ib(struct amdgpu_ring * ring,long timeout)1616 static int sdma_v4_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1617 {
1618 struct amdgpu_device *adev = ring->adev;
1619 struct amdgpu_ib ib;
1620 struct dma_fence *f = NULL;
1621 unsigned index;
1622 long r;
1623 u32 tmp = 0;
1624 u64 gpu_addr;
1625
1626 r = amdgpu_device_wb_get(adev, &index);
1627 if (r)
1628 return r;
1629
1630 gpu_addr = adev->wb.gpu_addr + (index * 4);
1631 tmp = 0xCAFEDEAD;
1632 adev->wb.wb[index] = cpu_to_le32(tmp);
1633 memset(&ib, 0, sizeof(ib));
1634 r = amdgpu_ib_get(adev, NULL, 256,
1635 AMDGPU_IB_POOL_DIRECT, &ib);
1636 if (r)
1637 goto err0;
1638
1639 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1640 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1641 ib.ptr[1] = lower_32_bits(gpu_addr);
1642 ib.ptr[2] = upper_32_bits(gpu_addr);
1643 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
1644 ib.ptr[4] = 0xDEADBEEF;
1645 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1646 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1647 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1648 ib.length_dw = 8;
1649
1650 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1651 if (r)
1652 goto err1;
1653
1654 r = dma_fence_wait_timeout(f, false, timeout);
1655 if (r == 0) {
1656 r = -ETIMEDOUT;
1657 goto err1;
1658 } else if (r < 0) {
1659 goto err1;
1660 }
1661 tmp = le32_to_cpu(adev->wb.wb[index]);
1662 if (tmp == 0xDEADBEEF)
1663 r = 0;
1664 else
1665 r = -EINVAL;
1666
1667 err1:
1668 amdgpu_ib_free(adev, &ib, NULL);
1669 dma_fence_put(f);
1670 err0:
1671 amdgpu_device_wb_free(adev, index);
1672 return r;
1673 }
1674
1675
1676 /**
1677 * sdma_v4_0_vm_copy_pte - update PTEs by copying them from the GART
1678 *
1679 * @ib: indirect buffer to fill with commands
1680 * @pe: addr of the page entry
1681 * @src: src addr to copy from
1682 * @count: number of page entries to update
1683 *
1684 * Update PTEs by copying them from the GART using sDMA (VEGA10).
1685 */
sdma_v4_0_vm_copy_pte(struct amdgpu_ib * ib,uint64_t pe,uint64_t src,unsigned count)1686 static void sdma_v4_0_vm_copy_pte(struct amdgpu_ib *ib,
1687 uint64_t pe, uint64_t src,
1688 unsigned count)
1689 {
1690 unsigned bytes = count * 8;
1691
1692 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1693 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1694 ib->ptr[ib->length_dw++] = bytes - 1;
1695 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1696 ib->ptr[ib->length_dw++] = lower_32_bits(src);
1697 ib->ptr[ib->length_dw++] = upper_32_bits(src);
1698 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1699 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1700
1701 }
1702
1703 /**
1704 * sdma_v4_0_vm_write_pte - update PTEs by writing them manually
1705 *
1706 * @ib: indirect buffer to fill with commands
1707 * @pe: addr of the page entry
1708 * @value: dst addr to write into pe
1709 * @count: number of page entries to update
1710 * @incr: increase next addr by incr bytes
1711 *
1712 * Update PTEs by writing them manually using sDMA (VEGA10).
1713 */
sdma_v4_0_vm_write_pte(struct amdgpu_ib * ib,uint64_t pe,uint64_t value,unsigned count,uint32_t incr)1714 static void sdma_v4_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1715 uint64_t value, unsigned count,
1716 uint32_t incr)
1717 {
1718 unsigned ndw = count * 2;
1719
1720 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1721 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1722 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1723 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1724 ib->ptr[ib->length_dw++] = ndw - 1;
1725 for (; ndw > 0; ndw -= 2) {
1726 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1727 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1728 value += incr;
1729 }
1730 }
1731
1732 /**
1733 * sdma_v4_0_vm_set_pte_pde - update the page tables using sDMA
1734 *
1735 * @ib: indirect buffer to fill with commands
1736 * @pe: addr of the page entry
1737 * @addr: dst addr to write into pe
1738 * @count: number of page entries to update
1739 * @incr: increase next addr by incr bytes
1740 * @flags: access flags
1741 *
1742 * Update the page tables using sDMA (VEGA10).
1743 */
sdma_v4_0_vm_set_pte_pde(struct amdgpu_ib * ib,uint64_t pe,uint64_t addr,unsigned count,uint32_t incr,uint64_t flags)1744 static void sdma_v4_0_vm_set_pte_pde(struct amdgpu_ib *ib,
1745 uint64_t pe,
1746 uint64_t addr, unsigned count,
1747 uint32_t incr, uint64_t flags)
1748 {
1749 /* for physically contiguous pages (vram) */
1750 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);
1751 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1752 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1753 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1754 ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1755 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1756 ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1757 ib->ptr[ib->length_dw++] = incr; /* increment size */
1758 ib->ptr[ib->length_dw++] = 0;
1759 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1760 }
1761
1762 /**
1763 * sdma_v4_0_ring_pad_ib - pad the IB to the required number of dw
1764 *
1765 * @ring: amdgpu_ring structure holding ring information
1766 * @ib: indirect buffer to fill with padding
1767 */
sdma_v4_0_ring_pad_ib(struct amdgpu_ring * ring,struct amdgpu_ib * ib)1768 static void sdma_v4_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1769 {
1770 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1771 u32 pad_count;
1772 int i;
1773
1774 pad_count = (-ib->length_dw) & 7;
1775 for (i = 0; i < pad_count; i++)
1776 if (sdma && sdma->burst_nop && (i == 0))
1777 ib->ptr[ib->length_dw++] =
1778 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1779 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1780 else
1781 ib->ptr[ib->length_dw++] =
1782 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1783 }
1784
1785
1786 /**
1787 * sdma_v4_0_ring_emit_pipeline_sync - sync the pipeline
1788 *
1789 * @ring: amdgpu_ring pointer
1790 *
1791 * Make sure all previous operations are completed (CIK).
1792 */
sdma_v4_0_ring_emit_pipeline_sync(struct amdgpu_ring * ring)1793 static void sdma_v4_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1794 {
1795 uint32_t seq = ring->fence_drv.sync_seq;
1796 uint64_t addr = ring->fence_drv.gpu_addr;
1797
1798 /* wait for idle */
1799 sdma_v4_0_wait_reg_mem(ring, 1, 0,
1800 addr & 0xfffffffc,
1801 upper_32_bits(addr) & 0xffffffff,
1802 seq, 0xffffffff, 4);
1803 }
1804
1805
1806 /**
1807 * sdma_v4_0_ring_emit_vm_flush - vm flush using sDMA
1808 *
1809 * @ring: amdgpu_ring pointer
1810 * @vmid: vmid number to use
1811 * @pd_addr: address
1812 *
1813 * Update the page table base and flush the VM TLB
1814 * using sDMA (VEGA10).
1815 */
sdma_v4_0_ring_emit_vm_flush(struct amdgpu_ring * ring,unsigned vmid,uint64_t pd_addr)1816 static void sdma_v4_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1817 unsigned vmid, uint64_t pd_addr)
1818 {
1819 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1820 }
1821
sdma_v4_0_ring_emit_wreg(struct amdgpu_ring * ring,uint32_t reg,uint32_t val)1822 static void sdma_v4_0_ring_emit_wreg(struct amdgpu_ring *ring,
1823 uint32_t reg, uint32_t val)
1824 {
1825 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1826 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1827 amdgpu_ring_write(ring, reg);
1828 amdgpu_ring_write(ring, val);
1829 }
1830
sdma_v4_0_ring_emit_reg_wait(struct amdgpu_ring * ring,uint32_t reg,uint32_t val,uint32_t mask)1831 static void sdma_v4_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1832 uint32_t val, uint32_t mask)
1833 {
1834 sdma_v4_0_wait_reg_mem(ring, 0, 0, reg, 0, val, mask, 10);
1835 }
1836
sdma_v4_0_fw_support_paging_queue(struct amdgpu_device * adev)1837 static bool sdma_v4_0_fw_support_paging_queue(struct amdgpu_device *adev)
1838 {
1839 uint fw_version = adev->sdma.instance[0].fw_version;
1840
1841 switch (adev->ip_versions[SDMA0_HWIP][0]) {
1842 case IP_VERSION(4, 0, 0):
1843 return fw_version >= 430;
1844 case IP_VERSION(4, 0, 1):
1845 /*return fw_version >= 31;*/
1846 return false;
1847 case IP_VERSION(4, 2, 0):
1848 return fw_version >= 123;
1849 default:
1850 return false;
1851 }
1852 }
1853
sdma_v4_0_early_init(void * handle)1854 static int sdma_v4_0_early_init(void *handle)
1855 {
1856 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1857 int r;
1858
1859 r = sdma_v4_0_init_microcode(adev);
1860 if (r) {
1861 DRM_ERROR("Failed to load sdma firmware!\n");
1862 return r;
1863 }
1864
1865 /* TODO: Page queue breaks driver reload under SRIOV */
1866 if ((adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 0, 0)) &&
1867 amdgpu_sriov_vf((adev)))
1868 adev->sdma.has_page_queue = false;
1869 else if (sdma_v4_0_fw_support_paging_queue(adev))
1870 adev->sdma.has_page_queue = true;
1871
1872 sdma_v4_0_set_ring_funcs(adev);
1873 sdma_v4_0_set_buffer_funcs(adev);
1874 sdma_v4_0_set_vm_pte_funcs(adev);
1875 sdma_v4_0_set_irq_funcs(adev);
1876 sdma_v4_0_set_ras_funcs(adev);
1877
1878 return 0;
1879 }
1880
1881 static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev,
1882 void *err_data,
1883 struct amdgpu_iv_entry *entry);
1884
sdma_v4_0_late_init(void * handle)1885 static int sdma_v4_0_late_init(void *handle)
1886 {
1887 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1888 struct ras_ih_if ih_info = {
1889 .cb = sdma_v4_0_process_ras_data_cb,
1890 };
1891
1892 sdma_v4_0_setup_ulv(adev);
1893
1894 if (!amdgpu_persistent_edc_harvesting_supported(adev)) {
1895 if (adev->sdma.funcs &&
1896 adev->sdma.funcs->reset_ras_error_count)
1897 adev->sdma.funcs->reset_ras_error_count(adev);
1898 }
1899
1900 if (adev->sdma.funcs && adev->sdma.funcs->ras_late_init)
1901 return adev->sdma.funcs->ras_late_init(adev, &ih_info);
1902 else
1903 return 0;
1904 }
1905
sdma_v4_0_sw_init(void * handle)1906 static int sdma_v4_0_sw_init(void *handle)
1907 {
1908 struct amdgpu_ring *ring;
1909 int r, i;
1910 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1911
1912 /* SDMA trap event */
1913 for (i = 0; i < adev->sdma.num_instances; i++) {
1914 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i),
1915 SDMA0_4_0__SRCID__SDMA_TRAP,
1916 &adev->sdma.trap_irq);
1917 if (r)
1918 return r;
1919 }
1920
1921 /* SDMA SRAM ECC event */
1922 for (i = 0; i < adev->sdma.num_instances; i++) {
1923 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i),
1924 SDMA0_4_0__SRCID__SDMA_SRAM_ECC,
1925 &adev->sdma.ecc_irq);
1926 if (r)
1927 return r;
1928 }
1929
1930 /* SDMA VM_HOLE/DOORBELL_INV/POLL_TIMEOUT/SRBM_WRITE_PROTECTION event*/
1931 for (i = 0; i < adev->sdma.num_instances; i++) {
1932 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i),
1933 SDMA0_4_0__SRCID__SDMA_VM_HOLE,
1934 &adev->sdma.vm_hole_irq);
1935 if (r)
1936 return r;
1937
1938 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i),
1939 SDMA0_4_0__SRCID__SDMA_DOORBELL_INVALID,
1940 &adev->sdma.doorbell_invalid_irq);
1941 if (r)
1942 return r;
1943
1944 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i),
1945 SDMA0_4_0__SRCID__SDMA_POLL_TIMEOUT,
1946 &adev->sdma.pool_timeout_irq);
1947 if (r)
1948 return r;
1949
1950 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i),
1951 SDMA0_4_0__SRCID__SDMA_SRBMWRITE,
1952 &adev->sdma.srbm_write_irq);
1953 if (r)
1954 return r;
1955 }
1956
1957 for (i = 0; i < adev->sdma.num_instances; i++) {
1958 ring = &adev->sdma.instance[i].ring;
1959 ring->ring_obj = NULL;
1960 ring->use_doorbell = true;
1961
1962 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i,
1963 ring->use_doorbell?"true":"false");
1964
1965 /* doorbell size is 2 dwords, get DWORD offset */
1966 ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1;
1967
1968 sprintf(ring->name, "sdma%d", i);
1969 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq,
1970 AMDGPU_SDMA_IRQ_INSTANCE0 + i,
1971 AMDGPU_RING_PRIO_DEFAULT, NULL);
1972 if (r)
1973 return r;
1974
1975 if (adev->sdma.has_page_queue) {
1976 ring = &adev->sdma.instance[i].page;
1977 ring->ring_obj = NULL;
1978 ring->use_doorbell = true;
1979
1980 /* paging queue use same doorbell index/routing as gfx queue
1981 * with 0x400 (4096 dwords) offset on second doorbell page
1982 */
1983 ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1;
1984 ring->doorbell_index += 0x400;
1985
1986 sprintf(ring->name, "page%d", i);
1987 r = amdgpu_ring_init(adev, ring, 1024,
1988 &adev->sdma.trap_irq,
1989 AMDGPU_SDMA_IRQ_INSTANCE0 + i,
1990 AMDGPU_RING_PRIO_DEFAULT, NULL);
1991 if (r)
1992 return r;
1993 }
1994 }
1995
1996 return r;
1997 }
1998
sdma_v4_0_sw_fini(void * handle)1999 static int sdma_v4_0_sw_fini(void *handle)
2000 {
2001 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2002 int i;
2003
2004 if (adev->sdma.funcs && adev->sdma.funcs->ras_fini)
2005 adev->sdma.funcs->ras_fini(adev);
2006
2007 for (i = 0; i < adev->sdma.num_instances; i++) {
2008 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
2009 if (adev->sdma.has_page_queue)
2010 amdgpu_ring_fini(&adev->sdma.instance[i].page);
2011 }
2012
2013 sdma_v4_0_destroy_inst_ctx(adev);
2014
2015 return 0;
2016 }
2017
sdma_v4_0_hw_init(void * handle)2018 static int sdma_v4_0_hw_init(void *handle)
2019 {
2020 int r;
2021 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2022
2023 if (adev->flags & AMD_IS_APU)
2024 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, false);
2025
2026 if (!amdgpu_sriov_vf(adev))
2027 sdma_v4_0_init_golden_registers(adev);
2028
2029 r = sdma_v4_0_start(adev);
2030
2031 return r;
2032 }
2033
sdma_v4_0_hw_fini(void * handle)2034 static int sdma_v4_0_hw_fini(void *handle)
2035 {
2036 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2037 int i;
2038
2039 if (amdgpu_sriov_vf(adev))
2040 return 0;
2041
2042 for (i = 0; i < adev->sdma.num_instances; i++) {
2043 amdgpu_irq_put(adev, &adev->sdma.ecc_irq,
2044 AMDGPU_SDMA_IRQ_INSTANCE0 + i);
2045 }
2046
2047 sdma_v4_0_ctx_switch_enable(adev, false);
2048 sdma_v4_0_enable(adev, false);
2049
2050 if (adev->flags & AMD_IS_APU)
2051 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, true);
2052
2053 return 0;
2054 }
2055
sdma_v4_0_suspend(void * handle)2056 static int sdma_v4_0_suspend(void *handle)
2057 {
2058 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2059
2060 return sdma_v4_0_hw_fini(adev);
2061 }
2062
sdma_v4_0_resume(void * handle)2063 static int sdma_v4_0_resume(void *handle)
2064 {
2065 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2066
2067 return sdma_v4_0_hw_init(adev);
2068 }
2069
sdma_v4_0_is_idle(void * handle)2070 static bool sdma_v4_0_is_idle(void *handle)
2071 {
2072 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2073 u32 i;
2074
2075 for (i = 0; i < adev->sdma.num_instances; i++) {
2076 u32 tmp = RREG32_SDMA(i, mmSDMA0_STATUS_REG);
2077
2078 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
2079 return false;
2080 }
2081
2082 return true;
2083 }
2084
sdma_v4_0_wait_for_idle(void * handle)2085 static int sdma_v4_0_wait_for_idle(void *handle)
2086 {
2087 unsigned i, j;
2088 u32 sdma[AMDGPU_MAX_SDMA_INSTANCES];
2089 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2090
2091 for (i = 0; i < adev->usec_timeout; i++) {
2092 for (j = 0; j < adev->sdma.num_instances; j++) {
2093 sdma[j] = RREG32_SDMA(j, mmSDMA0_STATUS_REG);
2094 if (!(sdma[j] & SDMA0_STATUS_REG__IDLE_MASK))
2095 break;
2096 }
2097 if (j == adev->sdma.num_instances)
2098 return 0;
2099 udelay(1);
2100 }
2101 return -ETIMEDOUT;
2102 }
2103
sdma_v4_0_soft_reset(void * handle)2104 static int sdma_v4_0_soft_reset(void *handle)
2105 {
2106 /* todo */
2107
2108 return 0;
2109 }
2110
sdma_v4_0_set_trap_irq_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned type,enum amdgpu_interrupt_state state)2111 static int sdma_v4_0_set_trap_irq_state(struct amdgpu_device *adev,
2112 struct amdgpu_irq_src *source,
2113 unsigned type,
2114 enum amdgpu_interrupt_state state)
2115 {
2116 u32 sdma_cntl;
2117
2118 sdma_cntl = RREG32_SDMA(type, mmSDMA0_CNTL);
2119 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
2120 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
2121 WREG32_SDMA(type, mmSDMA0_CNTL, sdma_cntl);
2122
2123 return 0;
2124 }
2125
sdma_v4_0_process_trap_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)2126 static int sdma_v4_0_process_trap_irq(struct amdgpu_device *adev,
2127 struct amdgpu_irq_src *source,
2128 struct amdgpu_iv_entry *entry)
2129 {
2130 uint32_t instance;
2131
2132 DRM_DEBUG("IH: SDMA trap\n");
2133 instance = sdma_v4_0_irq_id_to_seq(entry->client_id);
2134 switch (entry->ring_id) {
2135 case 0:
2136 amdgpu_fence_process(&adev->sdma.instance[instance].ring);
2137 break;
2138 case 1:
2139 if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 0))
2140 amdgpu_fence_process(&adev->sdma.instance[instance].page);
2141 break;
2142 case 2:
2143 /* XXX compute */
2144 break;
2145 case 3:
2146 if (adev->ip_versions[SDMA0_HWIP][0] != IP_VERSION(4, 2, 0))
2147 amdgpu_fence_process(&adev->sdma.instance[instance].page);
2148 break;
2149 }
2150 return 0;
2151 }
2152
sdma_v4_0_process_ras_data_cb(struct amdgpu_device * adev,void * err_data,struct amdgpu_iv_entry * entry)2153 static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev,
2154 void *err_data,
2155 struct amdgpu_iv_entry *entry)
2156 {
2157 int instance;
2158
2159 /* When “Full RAS” is enabled, the per-IP interrupt sources should
2160 * be disabled and the driver should only look for the aggregated
2161 * interrupt via sync flood
2162 */
2163 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))
2164 goto out;
2165
2166 instance = sdma_v4_0_irq_id_to_seq(entry->client_id);
2167 if (instance < 0)
2168 goto out;
2169
2170 amdgpu_sdma_process_ras_data_cb(adev, err_data, entry);
2171
2172 out:
2173 return AMDGPU_RAS_SUCCESS;
2174 }
2175
sdma_v4_0_process_illegal_inst_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)2176 static int sdma_v4_0_process_illegal_inst_irq(struct amdgpu_device *adev,
2177 struct amdgpu_irq_src *source,
2178 struct amdgpu_iv_entry *entry)
2179 {
2180 int instance;
2181
2182 DRM_ERROR("Illegal instruction in SDMA command stream\n");
2183
2184 instance = sdma_v4_0_irq_id_to_seq(entry->client_id);
2185 if (instance < 0)
2186 return 0;
2187
2188 switch (entry->ring_id) {
2189 case 0:
2190 drm_sched_fault(&adev->sdma.instance[instance].ring.sched);
2191 break;
2192 }
2193 return 0;
2194 }
2195
sdma_v4_0_set_ecc_irq_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned type,enum amdgpu_interrupt_state state)2196 static int sdma_v4_0_set_ecc_irq_state(struct amdgpu_device *adev,
2197 struct amdgpu_irq_src *source,
2198 unsigned type,
2199 enum amdgpu_interrupt_state state)
2200 {
2201 u32 sdma_edc_config;
2202
2203 sdma_edc_config = RREG32_SDMA(type, mmSDMA0_EDC_CONFIG);
2204 sdma_edc_config = REG_SET_FIELD(sdma_edc_config, SDMA0_EDC_CONFIG, ECC_INT_ENABLE,
2205 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
2206 WREG32_SDMA(type, mmSDMA0_EDC_CONFIG, sdma_edc_config);
2207
2208 return 0;
2209 }
2210
sdma_v4_0_print_iv_entry(struct amdgpu_device * adev,struct amdgpu_iv_entry * entry)2211 static int sdma_v4_0_print_iv_entry(struct amdgpu_device *adev,
2212 struct amdgpu_iv_entry *entry)
2213 {
2214 int instance;
2215 struct amdgpu_task_info task_info;
2216 u64 addr;
2217
2218 instance = sdma_v4_0_irq_id_to_seq(entry->client_id);
2219 if (instance < 0 || instance >= adev->sdma.num_instances) {
2220 dev_err(adev->dev, "sdma instance invalid %d\n", instance);
2221 return -EINVAL;
2222 }
2223
2224 addr = (u64)entry->src_data[0] << 12;
2225 addr |= ((u64)entry->src_data[1] & 0xf) << 44;
2226
2227 memset(&task_info, 0, sizeof(struct amdgpu_task_info));
2228 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info);
2229
2230 dev_dbg_ratelimited(adev->dev,
2231 "[sdma%d] address:0x%016llx src_id:%u ring:%u vmid:%u "
2232 "pasid:%u, for process %s pid %d thread %s pid %d\n",
2233 instance, addr, entry->src_id, entry->ring_id, entry->vmid,
2234 entry->pasid, task_info.process_name, task_info.tgid,
2235 task_info.task_name, task_info.pid);
2236 return 0;
2237 }
2238
sdma_v4_0_process_vm_hole_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)2239 static int sdma_v4_0_process_vm_hole_irq(struct amdgpu_device *adev,
2240 struct amdgpu_irq_src *source,
2241 struct amdgpu_iv_entry *entry)
2242 {
2243 dev_dbg_ratelimited(adev->dev, "MC or SEM address in VM hole\n");
2244 sdma_v4_0_print_iv_entry(adev, entry);
2245 return 0;
2246 }
2247
sdma_v4_0_process_doorbell_invalid_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)2248 static int sdma_v4_0_process_doorbell_invalid_irq(struct amdgpu_device *adev,
2249 struct amdgpu_irq_src *source,
2250 struct amdgpu_iv_entry *entry)
2251 {
2252 dev_dbg_ratelimited(adev->dev, "SDMA received a doorbell from BIF with byte_enable !=0xff\n");
2253 sdma_v4_0_print_iv_entry(adev, entry);
2254 return 0;
2255 }
2256
sdma_v4_0_process_pool_timeout_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)2257 static int sdma_v4_0_process_pool_timeout_irq(struct amdgpu_device *adev,
2258 struct amdgpu_irq_src *source,
2259 struct amdgpu_iv_entry *entry)
2260 {
2261 dev_dbg_ratelimited(adev->dev,
2262 "Polling register/memory timeout executing POLL_REG/MEM with finite timer\n");
2263 sdma_v4_0_print_iv_entry(adev, entry);
2264 return 0;
2265 }
2266
sdma_v4_0_process_srbm_write_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)2267 static int sdma_v4_0_process_srbm_write_irq(struct amdgpu_device *adev,
2268 struct amdgpu_irq_src *source,
2269 struct amdgpu_iv_entry *entry)
2270 {
2271 dev_dbg_ratelimited(adev->dev,
2272 "SDMA gets an Register Write SRBM_WRITE command in non-privilege command buffer\n");
2273 sdma_v4_0_print_iv_entry(adev, entry);
2274 return 0;
2275 }
2276
sdma_v4_0_update_medium_grain_clock_gating(struct amdgpu_device * adev,bool enable)2277 static void sdma_v4_0_update_medium_grain_clock_gating(
2278 struct amdgpu_device *adev,
2279 bool enable)
2280 {
2281 uint32_t data, def;
2282 int i;
2283
2284 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
2285 for (i = 0; i < adev->sdma.num_instances; i++) {
2286 def = data = RREG32_SDMA(i, mmSDMA0_CLK_CTRL);
2287 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
2288 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
2289 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
2290 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
2291 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
2292 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
2293 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
2294 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
2295 if (def != data)
2296 WREG32_SDMA(i, mmSDMA0_CLK_CTRL, data);
2297 }
2298 } else {
2299 for (i = 0; i < adev->sdma.num_instances; i++) {
2300 def = data = RREG32_SDMA(i, mmSDMA0_CLK_CTRL);
2301 data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
2302 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
2303 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
2304 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
2305 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
2306 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
2307 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
2308 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
2309 if (def != data)
2310 WREG32_SDMA(i, mmSDMA0_CLK_CTRL, data);
2311 }
2312 }
2313 }
2314
2315
sdma_v4_0_update_medium_grain_light_sleep(struct amdgpu_device * adev,bool enable)2316 static void sdma_v4_0_update_medium_grain_light_sleep(
2317 struct amdgpu_device *adev,
2318 bool enable)
2319 {
2320 uint32_t data, def;
2321 int i;
2322
2323 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
2324 for (i = 0; i < adev->sdma.num_instances; i++) {
2325 /* 1-not override: enable sdma mem light sleep */
2326 def = data = RREG32_SDMA(0, mmSDMA0_POWER_CNTL);
2327 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
2328 if (def != data)
2329 WREG32_SDMA(0, mmSDMA0_POWER_CNTL, data);
2330 }
2331 } else {
2332 for (i = 0; i < adev->sdma.num_instances; i++) {
2333 /* 0-override:disable sdma mem light sleep */
2334 def = data = RREG32_SDMA(0, mmSDMA0_POWER_CNTL);
2335 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
2336 if (def != data)
2337 WREG32_SDMA(0, mmSDMA0_POWER_CNTL, data);
2338 }
2339 }
2340 }
2341
sdma_v4_0_set_clockgating_state(void * handle,enum amd_clockgating_state state)2342 static int sdma_v4_0_set_clockgating_state(void *handle,
2343 enum amd_clockgating_state state)
2344 {
2345 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2346
2347 if (amdgpu_sriov_vf(adev))
2348 return 0;
2349
2350 sdma_v4_0_update_medium_grain_clock_gating(adev,
2351 state == AMD_CG_STATE_GATE);
2352 sdma_v4_0_update_medium_grain_light_sleep(adev,
2353 state == AMD_CG_STATE_GATE);
2354 return 0;
2355 }
2356
sdma_v4_0_set_powergating_state(void * handle,enum amd_powergating_state state)2357 static int sdma_v4_0_set_powergating_state(void *handle,
2358 enum amd_powergating_state state)
2359 {
2360 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2361
2362 switch (adev->ip_versions[SDMA0_HWIP][0]) {
2363 case IP_VERSION(4, 1, 0):
2364 case IP_VERSION(4, 1, 1):
2365 case IP_VERSION(4, 1, 2):
2366 sdma_v4_1_update_power_gating(adev,
2367 state == AMD_PG_STATE_GATE);
2368 break;
2369 default:
2370 break;
2371 }
2372
2373 return 0;
2374 }
2375
sdma_v4_0_get_clockgating_state(void * handle,u32 * flags)2376 static void sdma_v4_0_get_clockgating_state(void *handle, u32 *flags)
2377 {
2378 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2379 int data;
2380
2381 if (amdgpu_sriov_vf(adev))
2382 *flags = 0;
2383
2384 /* AMD_CG_SUPPORT_SDMA_MGCG */
2385 data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL));
2386 if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK))
2387 *flags |= AMD_CG_SUPPORT_SDMA_MGCG;
2388
2389 /* AMD_CG_SUPPORT_SDMA_LS */
2390 data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
2391 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
2392 *flags |= AMD_CG_SUPPORT_SDMA_LS;
2393 }
2394
2395 const struct amd_ip_funcs sdma_v4_0_ip_funcs = {
2396 .name = "sdma_v4_0",
2397 .early_init = sdma_v4_0_early_init,
2398 .late_init = sdma_v4_0_late_init,
2399 .sw_init = sdma_v4_0_sw_init,
2400 .sw_fini = sdma_v4_0_sw_fini,
2401 .hw_init = sdma_v4_0_hw_init,
2402 .hw_fini = sdma_v4_0_hw_fini,
2403 .suspend = sdma_v4_0_suspend,
2404 .resume = sdma_v4_0_resume,
2405 .is_idle = sdma_v4_0_is_idle,
2406 .wait_for_idle = sdma_v4_0_wait_for_idle,
2407 .soft_reset = sdma_v4_0_soft_reset,
2408 .set_clockgating_state = sdma_v4_0_set_clockgating_state,
2409 .set_powergating_state = sdma_v4_0_set_powergating_state,
2410 .get_clockgating_state = sdma_v4_0_get_clockgating_state,
2411 };
2412
2413 static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs = {
2414 .type = AMDGPU_RING_TYPE_SDMA,
2415 .align_mask = 0xf,
2416 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
2417 .support_64bit_ptrs = true,
2418 .vmhub = AMDGPU_MMHUB_0,
2419 .get_rptr = sdma_v4_0_ring_get_rptr,
2420 .get_wptr = sdma_v4_0_ring_get_wptr,
2421 .set_wptr = sdma_v4_0_ring_set_wptr,
2422 .emit_frame_size =
2423 6 + /* sdma_v4_0_ring_emit_hdp_flush */
2424 3 + /* hdp invalidate */
2425 6 + /* sdma_v4_0_ring_emit_pipeline_sync */
2426 /* sdma_v4_0_ring_emit_vm_flush */
2427 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
2428 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
2429 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */
2430 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */
2431 .emit_ib = sdma_v4_0_ring_emit_ib,
2432 .emit_fence = sdma_v4_0_ring_emit_fence,
2433 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync,
2434 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush,
2435 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush,
2436 .test_ring = sdma_v4_0_ring_test_ring,
2437 .test_ib = sdma_v4_0_ring_test_ib,
2438 .insert_nop = sdma_v4_0_ring_insert_nop,
2439 .pad_ib = sdma_v4_0_ring_pad_ib,
2440 .emit_wreg = sdma_v4_0_ring_emit_wreg,
2441 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait,
2442 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2443 };
2444
2445 /*
2446 * On Arcturus, SDMA instance 5~7 has a different vmhub type(AMDGPU_MMHUB_1).
2447 * So create a individual constant ring_funcs for those instances.
2448 */
2449 static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs_2nd_mmhub = {
2450 .type = AMDGPU_RING_TYPE_SDMA,
2451 .align_mask = 0xf,
2452 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
2453 .support_64bit_ptrs = true,
2454 .vmhub = AMDGPU_MMHUB_1,
2455 .get_rptr = sdma_v4_0_ring_get_rptr,
2456 .get_wptr = sdma_v4_0_ring_get_wptr,
2457 .set_wptr = sdma_v4_0_ring_set_wptr,
2458 .emit_frame_size =
2459 6 + /* sdma_v4_0_ring_emit_hdp_flush */
2460 3 + /* hdp invalidate */
2461 6 + /* sdma_v4_0_ring_emit_pipeline_sync */
2462 /* sdma_v4_0_ring_emit_vm_flush */
2463 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
2464 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
2465 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */
2466 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */
2467 .emit_ib = sdma_v4_0_ring_emit_ib,
2468 .emit_fence = sdma_v4_0_ring_emit_fence,
2469 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync,
2470 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush,
2471 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush,
2472 .test_ring = sdma_v4_0_ring_test_ring,
2473 .test_ib = sdma_v4_0_ring_test_ib,
2474 .insert_nop = sdma_v4_0_ring_insert_nop,
2475 .pad_ib = sdma_v4_0_ring_pad_ib,
2476 .emit_wreg = sdma_v4_0_ring_emit_wreg,
2477 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait,
2478 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2479 };
2480
2481 static const struct amdgpu_ring_funcs sdma_v4_0_page_ring_funcs = {
2482 .type = AMDGPU_RING_TYPE_SDMA,
2483 .align_mask = 0xf,
2484 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
2485 .support_64bit_ptrs = true,
2486 .vmhub = AMDGPU_MMHUB_0,
2487 .get_rptr = sdma_v4_0_ring_get_rptr,
2488 .get_wptr = sdma_v4_0_page_ring_get_wptr,
2489 .set_wptr = sdma_v4_0_page_ring_set_wptr,
2490 .emit_frame_size =
2491 6 + /* sdma_v4_0_ring_emit_hdp_flush */
2492 3 + /* hdp invalidate */
2493 6 + /* sdma_v4_0_ring_emit_pipeline_sync */
2494 /* sdma_v4_0_ring_emit_vm_flush */
2495 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
2496 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
2497 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */
2498 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */
2499 .emit_ib = sdma_v4_0_ring_emit_ib,
2500 .emit_fence = sdma_v4_0_ring_emit_fence,
2501 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync,
2502 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush,
2503 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush,
2504 .test_ring = sdma_v4_0_ring_test_ring,
2505 .test_ib = sdma_v4_0_ring_test_ib,
2506 .insert_nop = sdma_v4_0_ring_insert_nop,
2507 .pad_ib = sdma_v4_0_ring_pad_ib,
2508 .emit_wreg = sdma_v4_0_ring_emit_wreg,
2509 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait,
2510 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2511 };
2512
2513 static const struct amdgpu_ring_funcs sdma_v4_0_page_ring_funcs_2nd_mmhub = {
2514 .type = AMDGPU_RING_TYPE_SDMA,
2515 .align_mask = 0xf,
2516 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
2517 .support_64bit_ptrs = true,
2518 .vmhub = AMDGPU_MMHUB_1,
2519 .get_rptr = sdma_v4_0_ring_get_rptr,
2520 .get_wptr = sdma_v4_0_page_ring_get_wptr,
2521 .set_wptr = sdma_v4_0_page_ring_set_wptr,
2522 .emit_frame_size =
2523 6 + /* sdma_v4_0_ring_emit_hdp_flush */
2524 3 + /* hdp invalidate */
2525 6 + /* sdma_v4_0_ring_emit_pipeline_sync */
2526 /* sdma_v4_0_ring_emit_vm_flush */
2527 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
2528 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
2529 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */
2530 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */
2531 .emit_ib = sdma_v4_0_ring_emit_ib,
2532 .emit_fence = sdma_v4_0_ring_emit_fence,
2533 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync,
2534 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush,
2535 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush,
2536 .test_ring = sdma_v4_0_ring_test_ring,
2537 .test_ib = sdma_v4_0_ring_test_ib,
2538 .insert_nop = sdma_v4_0_ring_insert_nop,
2539 .pad_ib = sdma_v4_0_ring_pad_ib,
2540 .emit_wreg = sdma_v4_0_ring_emit_wreg,
2541 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait,
2542 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2543 };
2544
sdma_v4_0_set_ring_funcs(struct amdgpu_device * adev)2545 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev)
2546 {
2547 int i;
2548
2549 for (i = 0; i < adev->sdma.num_instances; i++) {
2550 if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) && i >= 5)
2551 adev->sdma.instance[i].ring.funcs =
2552 &sdma_v4_0_ring_funcs_2nd_mmhub;
2553 else
2554 adev->sdma.instance[i].ring.funcs =
2555 &sdma_v4_0_ring_funcs;
2556 adev->sdma.instance[i].ring.me = i;
2557 if (adev->sdma.has_page_queue) {
2558 if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) && i >= 5)
2559 adev->sdma.instance[i].page.funcs =
2560 &sdma_v4_0_page_ring_funcs_2nd_mmhub;
2561 else
2562 adev->sdma.instance[i].page.funcs =
2563 &sdma_v4_0_page_ring_funcs;
2564 adev->sdma.instance[i].page.me = i;
2565 }
2566 }
2567 }
2568
2569 static const struct amdgpu_irq_src_funcs sdma_v4_0_trap_irq_funcs = {
2570 .set = sdma_v4_0_set_trap_irq_state,
2571 .process = sdma_v4_0_process_trap_irq,
2572 };
2573
2574 static const struct amdgpu_irq_src_funcs sdma_v4_0_illegal_inst_irq_funcs = {
2575 .process = sdma_v4_0_process_illegal_inst_irq,
2576 };
2577
2578 static const struct amdgpu_irq_src_funcs sdma_v4_0_ecc_irq_funcs = {
2579 .set = sdma_v4_0_set_ecc_irq_state,
2580 .process = amdgpu_sdma_process_ecc_irq,
2581 };
2582
2583 static const struct amdgpu_irq_src_funcs sdma_v4_0_vm_hole_irq_funcs = {
2584 .process = sdma_v4_0_process_vm_hole_irq,
2585 };
2586
2587 static const struct amdgpu_irq_src_funcs sdma_v4_0_doorbell_invalid_irq_funcs = {
2588 .process = sdma_v4_0_process_doorbell_invalid_irq,
2589 };
2590
2591 static const struct amdgpu_irq_src_funcs sdma_v4_0_pool_timeout_irq_funcs = {
2592 .process = sdma_v4_0_process_pool_timeout_irq,
2593 };
2594
2595 static const struct amdgpu_irq_src_funcs sdma_v4_0_srbm_write_irq_funcs = {
2596 .process = sdma_v4_0_process_srbm_write_irq,
2597 };
2598
sdma_v4_0_set_irq_funcs(struct amdgpu_device * adev)2599 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev)
2600 {
2601 adev->sdma.trap_irq.num_types = adev->sdma.num_instances;
2602 adev->sdma.ecc_irq.num_types = adev->sdma.num_instances;
2603 /*For Arcturus and Aldebaran, add another 4 irq handler*/
2604 switch (adev->sdma.num_instances) {
2605 case 5:
2606 case 8:
2607 adev->sdma.vm_hole_irq.num_types = adev->sdma.num_instances;
2608 adev->sdma.doorbell_invalid_irq.num_types = adev->sdma.num_instances;
2609 adev->sdma.pool_timeout_irq.num_types = adev->sdma.num_instances;
2610 adev->sdma.srbm_write_irq.num_types = adev->sdma.num_instances;
2611 break;
2612 default:
2613 break;
2614 }
2615 adev->sdma.trap_irq.funcs = &sdma_v4_0_trap_irq_funcs;
2616 adev->sdma.illegal_inst_irq.funcs = &sdma_v4_0_illegal_inst_irq_funcs;
2617 adev->sdma.ecc_irq.funcs = &sdma_v4_0_ecc_irq_funcs;
2618 adev->sdma.vm_hole_irq.funcs = &sdma_v4_0_vm_hole_irq_funcs;
2619 adev->sdma.doorbell_invalid_irq.funcs = &sdma_v4_0_doorbell_invalid_irq_funcs;
2620 adev->sdma.pool_timeout_irq.funcs = &sdma_v4_0_pool_timeout_irq_funcs;
2621 adev->sdma.srbm_write_irq.funcs = &sdma_v4_0_srbm_write_irq_funcs;
2622 }
2623
2624 /**
2625 * sdma_v4_0_emit_copy_buffer - copy buffer using the sDMA engine
2626 *
2627 * @ib: indirect buffer to copy to
2628 * @src_offset: src GPU address
2629 * @dst_offset: dst GPU address
2630 * @byte_count: number of bytes to xfer
2631 * @tmz: if a secure copy should be used
2632 *
2633 * Copy GPU buffers using the DMA engine (VEGA10/12).
2634 * Used by the amdgpu ttm implementation to move pages if
2635 * registered as the asic copy callback.
2636 */
sdma_v4_0_emit_copy_buffer(struct amdgpu_ib * ib,uint64_t src_offset,uint64_t dst_offset,uint32_t byte_count,bool tmz)2637 static void sdma_v4_0_emit_copy_buffer(struct amdgpu_ib *ib,
2638 uint64_t src_offset,
2639 uint64_t dst_offset,
2640 uint32_t byte_count,
2641 bool tmz)
2642 {
2643 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
2644 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
2645 SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0);
2646 ib->ptr[ib->length_dw++] = byte_count - 1;
2647 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
2648 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
2649 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
2650 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
2651 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
2652 }
2653
2654 /**
2655 * sdma_v4_0_emit_fill_buffer - fill buffer using the sDMA engine
2656 *
2657 * @ib: indirect buffer to copy to
2658 * @src_data: value to write to buffer
2659 * @dst_offset: dst GPU address
2660 * @byte_count: number of bytes to xfer
2661 *
2662 * Fill GPU buffers using the DMA engine (VEGA10/12).
2663 */
sdma_v4_0_emit_fill_buffer(struct amdgpu_ib * ib,uint32_t src_data,uint64_t dst_offset,uint32_t byte_count)2664 static void sdma_v4_0_emit_fill_buffer(struct amdgpu_ib *ib,
2665 uint32_t src_data,
2666 uint64_t dst_offset,
2667 uint32_t byte_count)
2668 {
2669 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
2670 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
2671 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
2672 ib->ptr[ib->length_dw++] = src_data;
2673 ib->ptr[ib->length_dw++] = byte_count - 1;
2674 }
2675
2676 static const struct amdgpu_buffer_funcs sdma_v4_0_buffer_funcs = {
2677 .copy_max_bytes = 0x400000,
2678 .copy_num_dw = 7,
2679 .emit_copy_buffer = sdma_v4_0_emit_copy_buffer,
2680
2681 .fill_max_bytes = 0x400000,
2682 .fill_num_dw = 5,
2683 .emit_fill_buffer = sdma_v4_0_emit_fill_buffer,
2684 };
2685
sdma_v4_0_set_buffer_funcs(struct amdgpu_device * adev)2686 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev)
2687 {
2688 adev->mman.buffer_funcs = &sdma_v4_0_buffer_funcs;
2689 if (adev->sdma.has_page_queue)
2690 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].page;
2691 else
2692 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
2693 }
2694
2695 static const struct amdgpu_vm_pte_funcs sdma_v4_0_vm_pte_funcs = {
2696 .copy_pte_num_dw = 7,
2697 .copy_pte = sdma_v4_0_vm_copy_pte,
2698
2699 .write_pte = sdma_v4_0_vm_write_pte,
2700 .set_pte_pde = sdma_v4_0_vm_set_pte_pde,
2701 };
2702
sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device * adev)2703 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev)
2704 {
2705 struct drm_gpu_scheduler *sched;
2706 unsigned i;
2707
2708 adev->vm_manager.vm_pte_funcs = &sdma_v4_0_vm_pte_funcs;
2709 for (i = 0; i < adev->sdma.num_instances; i++) {
2710 if (adev->sdma.has_page_queue)
2711 sched = &adev->sdma.instance[i].page.sched;
2712 else
2713 sched = &adev->sdma.instance[i].ring.sched;
2714 adev->vm_manager.vm_pte_scheds[i] = sched;
2715 }
2716 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
2717 }
2718
sdma_v4_0_get_ras_error_count(uint32_t value,uint32_t instance,uint32_t * sec_count)2719 static void sdma_v4_0_get_ras_error_count(uint32_t value,
2720 uint32_t instance,
2721 uint32_t *sec_count)
2722 {
2723 uint32_t i;
2724 uint32_t sec_cnt;
2725
2726 /* double bits error (multiple bits) error detection is not supported */
2727 for (i = 0; i < ARRAY_SIZE(sdma_v4_0_ras_fields); i++) {
2728 /* the SDMA_EDC_COUNTER register in each sdma instance
2729 * shares the same sed shift_mask
2730 * */
2731 sec_cnt = (value &
2732 sdma_v4_0_ras_fields[i].sec_count_mask) >>
2733 sdma_v4_0_ras_fields[i].sec_count_shift;
2734 if (sec_cnt) {
2735 DRM_INFO("Detected %s in SDMA%d, SED %d\n",
2736 sdma_v4_0_ras_fields[i].name,
2737 instance, sec_cnt);
2738 *sec_count += sec_cnt;
2739 }
2740 }
2741 }
2742
sdma_v4_0_query_ras_error_count(struct amdgpu_device * adev,uint32_t instance,void * ras_error_status)2743 static int sdma_v4_0_query_ras_error_count(struct amdgpu_device *adev,
2744 uint32_t instance, void *ras_error_status)
2745 {
2746 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
2747 uint32_t sec_count = 0;
2748 uint32_t reg_value = 0;
2749
2750 reg_value = RREG32_SDMA(instance, mmSDMA0_EDC_COUNTER);
2751 /* double bit error is not supported */
2752 if (reg_value)
2753 sdma_v4_0_get_ras_error_count(reg_value,
2754 instance, &sec_count);
2755 /* err_data->ce_count should be initialized to 0
2756 * before calling into this function */
2757 err_data->ce_count += sec_count;
2758 /* double bit error is not supported
2759 * set ue count to 0 */
2760 err_data->ue_count = 0;
2761
2762 return 0;
2763 };
2764
sdma_v4_0_reset_ras_error_count(struct amdgpu_device * adev)2765 static void sdma_v4_0_reset_ras_error_count(struct amdgpu_device *adev)
2766 {
2767 int i;
2768
2769 /* read back edc counter registers to clear the counters */
2770 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) {
2771 for (i = 0; i < adev->sdma.num_instances; i++)
2772 RREG32_SDMA(i, mmSDMA0_EDC_COUNTER);
2773 }
2774 }
2775
2776 static const struct amdgpu_sdma_ras_funcs sdma_v4_0_ras_funcs = {
2777 .ras_late_init = amdgpu_sdma_ras_late_init,
2778 .ras_fini = amdgpu_sdma_ras_fini,
2779 .query_ras_error_count = sdma_v4_0_query_ras_error_count,
2780 .reset_ras_error_count = sdma_v4_0_reset_ras_error_count,
2781 };
2782
sdma_v4_0_set_ras_funcs(struct amdgpu_device * adev)2783 static void sdma_v4_0_set_ras_funcs(struct amdgpu_device *adev)
2784 {
2785 switch (adev->ip_versions[SDMA0_HWIP][0]) {
2786 case IP_VERSION(4, 2, 0):
2787 case IP_VERSION(4, 2, 2):
2788 adev->sdma.funcs = &sdma_v4_0_ras_funcs;
2789 break;
2790 case IP_VERSION(4, 4, 0):
2791 adev->sdma.funcs = &sdma_v4_4_ras_funcs;
2792 break;
2793 default:
2794 break;
2795 }
2796 }
2797
2798 const struct amdgpu_ip_block_version sdma_v4_0_ip_block = {
2799 .type = AMD_IP_BLOCK_TYPE_SDMA,
2800 .major = 4,
2801 .minor = 0,
2802 .rev = 0,
2803 .funcs = &sdma_v4_0_ip_funcs,
2804 };
2805