1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <linux/firmware.h>
25 #include <drm/drm_drv.h>
26
27 #include "amdgpu.h"
28 #include "amdgpu_vcn.h"
29 #include "amdgpu_pm.h"
30 #include "soc15.h"
31 #include "soc15d.h"
32 #include "vcn_v2_0.h"
33 #include "mmsch_v1_0.h"
34
35 #include "vcn/vcn_2_5_offset.h"
36 #include "vcn/vcn_2_5_sh_mask.h"
37 #include "ivsrcid/vcn/irqsrcs_vcn_2_0.h"
38
39 #define mmUVD_CONTEXT_ID_INTERNAL_OFFSET 0x27
40 #define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET 0x0f
41 #define mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET 0x10
42 #define mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET 0x11
43 #define mmUVD_NO_OP_INTERNAL_OFFSET 0x29
44 #define mmUVD_GP_SCRATCH8_INTERNAL_OFFSET 0x66
45 #define mmUVD_SCRATCH9_INTERNAL_OFFSET 0xc01d
46
47 #define mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET 0x431
48 #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET 0x3b4
49 #define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x3b5
50 #define mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET 0x25c
51
52 #define VCN25_MAX_HW_INSTANCES_ARCTURUS 2
53
54 static void vcn_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev);
55 static void vcn_v2_5_set_enc_ring_funcs(struct amdgpu_device *adev);
56 static void vcn_v2_5_set_irq_funcs(struct amdgpu_device *adev);
57 static int vcn_v2_5_set_powergating_state(void *handle,
58 enum amd_powergating_state state);
59 static int vcn_v2_5_pause_dpg_mode(struct amdgpu_device *adev,
60 int inst_idx, struct dpg_pause_state *new_state);
61 static int vcn_v2_5_sriov_start(struct amdgpu_device *adev);
62
63 static int amdgpu_ih_clientid_vcns[] = {
64 SOC15_IH_CLIENTID_VCN,
65 SOC15_IH_CLIENTID_VCN1
66 };
67
68 /**
69 * vcn_v2_5_early_init - set function pointers
70 *
71 * @handle: amdgpu_device pointer
72 *
73 * Set ring and irq function pointers
74 */
vcn_v2_5_early_init(void * handle)75 static int vcn_v2_5_early_init(void *handle)
76 {
77 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
78
79 if (amdgpu_sriov_vf(adev)) {
80 adev->vcn.num_vcn_inst = 2;
81 adev->vcn.harvest_config = 0;
82 adev->vcn.num_enc_rings = 1;
83 } else {
84 u32 harvest;
85 int i;
86
87 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
88 harvest = RREG32_SOC15(VCN, i, mmCC_UVD_HARVESTING);
89 if (harvest & CC_UVD_HARVESTING__UVD_DISABLE_MASK)
90 adev->vcn.harvest_config |= 1 << i;
91 }
92 if (adev->vcn.harvest_config == (AMDGPU_VCN_HARVEST_VCN0 |
93 AMDGPU_VCN_HARVEST_VCN1))
94 /* both instances are harvested, disable the block */
95 return -ENOENT;
96
97 adev->vcn.num_enc_rings = 2;
98 }
99
100 vcn_v2_5_set_dec_ring_funcs(adev);
101 vcn_v2_5_set_enc_ring_funcs(adev);
102 vcn_v2_5_set_irq_funcs(adev);
103
104 return 0;
105 }
106
107 /**
108 * vcn_v2_5_sw_init - sw init for VCN block
109 *
110 * @handle: amdgpu_device pointer
111 *
112 * Load firmware and sw initialization
113 */
vcn_v2_5_sw_init(void * handle)114 static int vcn_v2_5_sw_init(void *handle)
115 {
116 struct amdgpu_ring *ring;
117 int i, j, r;
118 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
119
120 for (j = 0; j < adev->vcn.num_vcn_inst; j++) {
121 if (adev->vcn.harvest_config & (1 << j))
122 continue;
123 /* VCN DEC TRAP */
124 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[j],
125 VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst[j].irq);
126 if (r)
127 return r;
128
129 /* VCN ENC TRAP */
130 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
131 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[j],
132 i + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[j].irq);
133 if (r)
134 return r;
135 }
136 }
137
138 r = amdgpu_vcn_sw_init(adev);
139 if (r)
140 return r;
141
142 amdgpu_vcn_setup_ucode(adev);
143
144 r = amdgpu_vcn_resume(adev);
145 if (r)
146 return r;
147
148 for (j = 0; j < adev->vcn.num_vcn_inst; j++) {
149 volatile struct amdgpu_fw_shared *fw_shared;
150
151 if (adev->vcn.harvest_config & (1 << j))
152 continue;
153 adev->vcn.internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET;
154 adev->vcn.internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET;
155 adev->vcn.internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET;
156 adev->vcn.internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET;
157 adev->vcn.internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET;
158 adev->vcn.internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET;
159
160 adev->vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET;
161 adev->vcn.inst[j].external.scratch9 = SOC15_REG_OFFSET(VCN, j, mmUVD_SCRATCH9);
162 adev->vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET;
163 adev->vcn.inst[j].external.data0 = SOC15_REG_OFFSET(VCN, j, mmUVD_GPCOM_VCPU_DATA0);
164 adev->vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET;
165 adev->vcn.inst[j].external.data1 = SOC15_REG_OFFSET(VCN, j, mmUVD_GPCOM_VCPU_DATA1);
166 adev->vcn.internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET;
167 adev->vcn.inst[j].external.cmd = SOC15_REG_OFFSET(VCN, j, mmUVD_GPCOM_VCPU_CMD);
168 adev->vcn.internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET;
169 adev->vcn.inst[j].external.nop = SOC15_REG_OFFSET(VCN, j, mmUVD_NO_OP);
170
171 ring = &adev->vcn.inst[j].ring_dec;
172 ring->use_doorbell = true;
173
174 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
175 (amdgpu_sriov_vf(adev) ? 2*j : 8*j);
176 sprintf(ring->name, "vcn_dec_%d", j);
177 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[j].irq,
178 0, AMDGPU_RING_PRIO_DEFAULT, NULL);
179 if (r)
180 return r;
181
182 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
183 enum amdgpu_ring_priority_level hw_prio = amdgpu_vcn_get_enc_ring_prio(i);
184
185 ring = &adev->vcn.inst[j].ring_enc[i];
186 ring->use_doorbell = true;
187
188 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
189 (amdgpu_sriov_vf(adev) ? (1 + i + 2*j) : (2 + i + 8*j));
190
191 sprintf(ring->name, "vcn_enc_%d.%d", j, i);
192 r = amdgpu_ring_init(adev, ring, 512,
193 &adev->vcn.inst[j].irq, 0,
194 hw_prio, NULL);
195 if (r)
196 return r;
197 }
198
199 fw_shared = adev->vcn.inst[j].fw_shared_cpu_addr;
200 fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_VCN_MULTI_QUEUE_FLAG);
201 }
202
203 if (amdgpu_sriov_vf(adev)) {
204 r = amdgpu_virt_alloc_mm_table(adev);
205 if (r)
206 return r;
207 }
208
209 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
210 adev->vcn.pause_dpg_mode = vcn_v2_5_pause_dpg_mode;
211
212 return 0;
213 }
214
215 /**
216 * vcn_v2_5_sw_fini - sw fini for VCN block
217 *
218 * @handle: amdgpu_device pointer
219 *
220 * VCN suspend and free up sw allocation
221 */
vcn_v2_5_sw_fini(void * handle)222 static int vcn_v2_5_sw_fini(void *handle)
223 {
224 int i, r, idx;
225 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
226 volatile struct amdgpu_fw_shared *fw_shared;
227
228 if (drm_dev_enter(adev_to_drm(adev), &idx)) {
229 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
230 if (adev->vcn.harvest_config & (1 << i))
231 continue;
232 fw_shared = adev->vcn.inst[i].fw_shared_cpu_addr;
233 fw_shared->present_flag_0 = 0;
234 }
235 drm_dev_exit(idx);
236 }
237
238
239 if (amdgpu_sriov_vf(adev))
240 amdgpu_virt_free_mm_table(adev);
241
242 r = amdgpu_vcn_suspend(adev);
243 if (r)
244 return r;
245
246 r = amdgpu_vcn_sw_fini(adev);
247
248 return r;
249 }
250
251 /**
252 * vcn_v2_5_hw_init - start and test VCN block
253 *
254 * @handle: amdgpu_device pointer
255 *
256 * Initialize the hardware, boot up the VCPU and do some testing
257 */
vcn_v2_5_hw_init(void * handle)258 static int vcn_v2_5_hw_init(void *handle)
259 {
260 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
261 struct amdgpu_ring *ring;
262 int i, j, r = 0;
263
264 if (amdgpu_sriov_vf(adev))
265 r = vcn_v2_5_sriov_start(adev);
266
267 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
268 if (adev->vcn.harvest_config & (1 << j))
269 continue;
270
271 if (amdgpu_sriov_vf(adev)) {
272 adev->vcn.inst[j].ring_enc[0].sched.ready = true;
273 adev->vcn.inst[j].ring_enc[1].sched.ready = false;
274 adev->vcn.inst[j].ring_enc[2].sched.ready = false;
275 adev->vcn.inst[j].ring_dec.sched.ready = true;
276 } else {
277
278 ring = &adev->vcn.inst[j].ring_dec;
279
280 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
281 ring->doorbell_index, j);
282
283 r = amdgpu_ring_test_helper(ring);
284 if (r)
285 goto done;
286
287 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
288 ring = &adev->vcn.inst[j].ring_enc[i];
289 r = amdgpu_ring_test_helper(ring);
290 if (r)
291 goto done;
292 }
293 }
294 }
295
296 done:
297 if (!r)
298 DRM_INFO("VCN decode and encode initialized successfully(under %s).\n",
299 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode");
300
301 return r;
302 }
303
304 /**
305 * vcn_v2_5_hw_fini - stop the hardware block
306 *
307 * @handle: amdgpu_device pointer
308 *
309 * Stop the VCN block, mark ring as not ready any more
310 */
vcn_v2_5_hw_fini(void * handle)311 static int vcn_v2_5_hw_fini(void *handle)
312 {
313 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
314 int i;
315
316 cancel_delayed_work_sync(&adev->vcn.idle_work);
317
318 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
319 if (adev->vcn.harvest_config & (1 << i))
320 continue;
321
322 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
323 (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
324 RREG32_SOC15(VCN, i, mmUVD_STATUS)))
325 vcn_v2_5_set_powergating_state(adev, AMD_PG_STATE_GATE);
326 }
327
328 return 0;
329 }
330
331 /**
332 * vcn_v2_5_suspend - suspend VCN block
333 *
334 * @handle: amdgpu_device pointer
335 *
336 * HW fini and suspend VCN block
337 */
vcn_v2_5_suspend(void * handle)338 static int vcn_v2_5_suspend(void *handle)
339 {
340 int r;
341 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
342
343 r = vcn_v2_5_hw_fini(adev);
344 if (r)
345 return r;
346
347 r = amdgpu_vcn_suspend(adev);
348
349 return r;
350 }
351
352 /**
353 * vcn_v2_5_resume - resume VCN block
354 *
355 * @handle: amdgpu_device pointer
356 *
357 * Resume firmware and hw init VCN block
358 */
vcn_v2_5_resume(void * handle)359 static int vcn_v2_5_resume(void *handle)
360 {
361 int r;
362 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
363
364 r = amdgpu_vcn_resume(adev);
365 if (r)
366 return r;
367
368 r = vcn_v2_5_hw_init(adev);
369
370 return r;
371 }
372
373 /**
374 * vcn_v2_5_mc_resume - memory controller programming
375 *
376 * @adev: amdgpu_device pointer
377 *
378 * Let the VCN memory controller know it's offsets
379 */
vcn_v2_5_mc_resume(struct amdgpu_device * adev)380 static void vcn_v2_5_mc_resume(struct amdgpu_device *adev)
381 {
382 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
383 uint32_t offset;
384 int i;
385
386 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
387 if (adev->vcn.harvest_config & (1 << i))
388 continue;
389 /* cache window 0: fw */
390 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
391 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
392 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_lo));
393 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
394 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_hi));
395 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET0, 0);
396 offset = 0;
397 } else {
398 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
399 lower_32_bits(adev->vcn.inst[i].gpu_addr));
400 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
401 upper_32_bits(adev->vcn.inst[i].gpu_addr));
402 offset = size;
403 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET0,
404 AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
405 }
406 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_SIZE0, size);
407
408 /* cache window 1: stack */
409 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
410 lower_32_bits(adev->vcn.inst[i].gpu_addr + offset));
411 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
412 upper_32_bits(adev->vcn.inst[i].gpu_addr + offset));
413 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET1, 0);
414 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE);
415
416 /* cache window 2: context */
417 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
418 lower_32_bits(adev->vcn.inst[i].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
419 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
420 upper_32_bits(adev->vcn.inst[i].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
421 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET2, 0);
422 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);
423
424 /* non-cache window */
425 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW,
426 lower_32_bits(adev->vcn.inst[i].fw_shared_gpu_addr));
427 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH,
428 upper_32_bits(adev->vcn.inst[i].fw_shared_gpu_addr));
429 WREG32_SOC15(VCN, i, mmUVD_VCPU_NONCACHE_OFFSET0, 0);
430 WREG32_SOC15(VCN, i, mmUVD_VCPU_NONCACHE_SIZE0,
431 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)));
432 }
433 }
434
vcn_v2_5_mc_resume_dpg_mode(struct amdgpu_device * adev,int inst_idx,bool indirect)435 static void vcn_v2_5_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)
436 {
437 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
438 uint32_t offset;
439
440 /* cache window 0: fw */
441 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
442 if (!indirect) {
443 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
444 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
445 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect);
446 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
447 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
448 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect);
449 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
450 VCN, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
451 } else {
452 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
453 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect);
454 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
455 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect);
456 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
457 VCN, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
458 }
459 offset = 0;
460 } else {
461 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
462 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
463 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
464 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
465 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
466 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
467 offset = size;
468 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
469 VCN, 0, mmUVD_VCPU_CACHE_OFFSET0),
470 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect);
471 }
472
473 if (!indirect)
474 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
475 VCN, 0, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect);
476 else
477 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
478 VCN, 0, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);
479
480 /* cache window 1: stack */
481 if (!indirect) {
482 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
483 VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
484 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
485 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
486 VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
487 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
488 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
489 VCN, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
490 } else {
491 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
492 VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect);
493 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
494 VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect);
495 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
496 VCN, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
497 }
498 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
499 VCN, 0, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect);
500
501 /* cache window 2: context */
502 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
503 VCN, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
504 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
505 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
506 VCN, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
507 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
508 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
509 VCN, 0, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);
510 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
511 VCN, 0, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);
512
513 /* non-cache window */
514 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
515 VCN, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW),
516 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared_gpu_addr), 0, indirect);
517 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
518 VCN, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH),
519 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared_gpu_addr), 0, indirect);
520 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
521 VCN, 0, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
522 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
523 VCN, 0, mmUVD_VCPU_NONCACHE_SIZE0),
524 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect);
525
526 /* VCN global tiling registers */
527 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
528 VCN, 0, mmUVD_GFX8_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);
529 }
530
531 /**
532 * vcn_v2_5_disable_clock_gating - disable VCN clock gating
533 *
534 * @adev: amdgpu_device pointer
535 *
536 * Disable clock gating for VCN block
537 */
vcn_v2_5_disable_clock_gating(struct amdgpu_device * adev)538 static void vcn_v2_5_disable_clock_gating(struct amdgpu_device *adev)
539 {
540 uint32_t data;
541 int i;
542
543 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
544 if (adev->vcn.harvest_config & (1 << i))
545 continue;
546 /* UVD disable CGC */
547 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL);
548 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
549 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
550 else
551 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
552 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
553 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
554 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data);
555
556 data = RREG32_SOC15(VCN, i, mmUVD_CGC_GATE);
557 data &= ~(UVD_CGC_GATE__SYS_MASK
558 | UVD_CGC_GATE__UDEC_MASK
559 | UVD_CGC_GATE__MPEG2_MASK
560 | UVD_CGC_GATE__REGS_MASK
561 | UVD_CGC_GATE__RBC_MASK
562 | UVD_CGC_GATE__LMI_MC_MASK
563 | UVD_CGC_GATE__LMI_UMC_MASK
564 | UVD_CGC_GATE__IDCT_MASK
565 | UVD_CGC_GATE__MPRD_MASK
566 | UVD_CGC_GATE__MPC_MASK
567 | UVD_CGC_GATE__LBSI_MASK
568 | UVD_CGC_GATE__LRBBM_MASK
569 | UVD_CGC_GATE__UDEC_RE_MASK
570 | UVD_CGC_GATE__UDEC_CM_MASK
571 | UVD_CGC_GATE__UDEC_IT_MASK
572 | UVD_CGC_GATE__UDEC_DB_MASK
573 | UVD_CGC_GATE__UDEC_MP_MASK
574 | UVD_CGC_GATE__WCB_MASK
575 | UVD_CGC_GATE__VCPU_MASK
576 | UVD_CGC_GATE__MMSCH_MASK);
577
578 WREG32_SOC15(VCN, i, mmUVD_CGC_GATE, data);
579
580 SOC15_WAIT_ON_RREG(VCN, i, mmUVD_CGC_GATE, 0, 0xFFFFFFFF);
581
582 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL);
583 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK
584 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
585 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
586 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
587 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
588 | UVD_CGC_CTRL__SYS_MODE_MASK
589 | UVD_CGC_CTRL__UDEC_MODE_MASK
590 | UVD_CGC_CTRL__MPEG2_MODE_MASK
591 | UVD_CGC_CTRL__REGS_MODE_MASK
592 | UVD_CGC_CTRL__RBC_MODE_MASK
593 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
594 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
595 | UVD_CGC_CTRL__IDCT_MODE_MASK
596 | UVD_CGC_CTRL__MPRD_MODE_MASK
597 | UVD_CGC_CTRL__MPC_MODE_MASK
598 | UVD_CGC_CTRL__LBSI_MODE_MASK
599 | UVD_CGC_CTRL__LRBBM_MODE_MASK
600 | UVD_CGC_CTRL__WCB_MODE_MASK
601 | UVD_CGC_CTRL__VCPU_MODE_MASK
602 | UVD_CGC_CTRL__MMSCH_MODE_MASK);
603 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data);
604
605 /* turn on */
606 data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_GATE);
607 data |= (UVD_SUVD_CGC_GATE__SRE_MASK
608 | UVD_SUVD_CGC_GATE__SIT_MASK
609 | UVD_SUVD_CGC_GATE__SMP_MASK
610 | UVD_SUVD_CGC_GATE__SCM_MASK
611 | UVD_SUVD_CGC_GATE__SDB_MASK
612 | UVD_SUVD_CGC_GATE__SRE_H264_MASK
613 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK
614 | UVD_SUVD_CGC_GATE__SIT_H264_MASK
615 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK
616 | UVD_SUVD_CGC_GATE__SCM_H264_MASK
617 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK
618 | UVD_SUVD_CGC_GATE__SDB_H264_MASK
619 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK
620 | UVD_SUVD_CGC_GATE__SCLR_MASK
621 | UVD_SUVD_CGC_GATE__UVD_SC_MASK
622 | UVD_SUVD_CGC_GATE__ENT_MASK
623 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK
624 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK
625 | UVD_SUVD_CGC_GATE__SITE_MASK
626 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK
627 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK
628 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK
629 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK
630 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK);
631 WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_GATE, data);
632
633 data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL);
634 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
635 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
636 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
637 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
638 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
639 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
640 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
641 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
642 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
643 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
644 WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL, data);
645 }
646 }
647
vcn_v2_5_clock_gating_dpg_mode(struct amdgpu_device * adev,uint8_t sram_sel,int inst_idx,uint8_t indirect)648 static void vcn_v2_5_clock_gating_dpg_mode(struct amdgpu_device *adev,
649 uint8_t sram_sel, int inst_idx, uint8_t indirect)
650 {
651 uint32_t reg_data = 0;
652
653 /* enable sw clock gating control */
654 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
655 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
656 else
657 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
658 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
659 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
660 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
661 UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
662 UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
663 UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
664 UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
665 UVD_CGC_CTRL__SYS_MODE_MASK |
666 UVD_CGC_CTRL__UDEC_MODE_MASK |
667 UVD_CGC_CTRL__MPEG2_MODE_MASK |
668 UVD_CGC_CTRL__REGS_MODE_MASK |
669 UVD_CGC_CTRL__RBC_MODE_MASK |
670 UVD_CGC_CTRL__LMI_MC_MODE_MASK |
671 UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
672 UVD_CGC_CTRL__IDCT_MODE_MASK |
673 UVD_CGC_CTRL__MPRD_MODE_MASK |
674 UVD_CGC_CTRL__MPC_MODE_MASK |
675 UVD_CGC_CTRL__LBSI_MODE_MASK |
676 UVD_CGC_CTRL__LRBBM_MODE_MASK |
677 UVD_CGC_CTRL__WCB_MODE_MASK |
678 UVD_CGC_CTRL__VCPU_MODE_MASK |
679 UVD_CGC_CTRL__MMSCH_MODE_MASK);
680 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
681 VCN, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect);
682
683 /* turn off clock gating */
684 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
685 VCN, 0, mmUVD_CGC_GATE), 0, sram_sel, indirect);
686
687 /* turn on SUVD clock gating */
688 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
689 VCN, 0, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);
690
691 /* turn on sw mode in UVD_SUVD_CGC_CTRL */
692 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
693 VCN, 0, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);
694 }
695
696 /**
697 * vcn_v2_5_enable_clock_gating - enable VCN clock gating
698 *
699 * @adev: amdgpu_device pointer
700 *
701 * Enable clock gating for VCN block
702 */
vcn_v2_5_enable_clock_gating(struct amdgpu_device * adev)703 static void vcn_v2_5_enable_clock_gating(struct amdgpu_device *adev)
704 {
705 uint32_t data = 0;
706 int i;
707
708 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
709 if (adev->vcn.harvest_config & (1 << i))
710 continue;
711 /* enable UVD CGC */
712 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL);
713 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
714 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
715 else
716 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
717 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
718 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
719 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data);
720
721 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL);
722 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK
723 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
724 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
725 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
726 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
727 | UVD_CGC_CTRL__SYS_MODE_MASK
728 | UVD_CGC_CTRL__UDEC_MODE_MASK
729 | UVD_CGC_CTRL__MPEG2_MODE_MASK
730 | UVD_CGC_CTRL__REGS_MODE_MASK
731 | UVD_CGC_CTRL__RBC_MODE_MASK
732 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
733 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
734 | UVD_CGC_CTRL__IDCT_MODE_MASK
735 | UVD_CGC_CTRL__MPRD_MODE_MASK
736 | UVD_CGC_CTRL__MPC_MODE_MASK
737 | UVD_CGC_CTRL__LBSI_MODE_MASK
738 | UVD_CGC_CTRL__LRBBM_MODE_MASK
739 | UVD_CGC_CTRL__WCB_MODE_MASK
740 | UVD_CGC_CTRL__VCPU_MODE_MASK);
741 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data);
742
743 data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL);
744 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
745 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
746 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
747 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
748 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
749 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
750 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
751 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
752 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
753 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
754 WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL, data);
755 }
756 }
757
vcn_v2_5_start_dpg_mode(struct amdgpu_device * adev,int inst_idx,bool indirect)758 static int vcn_v2_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)
759 {
760 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared_cpu_addr;
761 struct amdgpu_ring *ring;
762 uint32_t rb_bufsz, tmp;
763
764 /* disable register anti-hang mechanism */
765 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1,
766 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
767 /* enable dynamic power gating mode */
768 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS);
769 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK;
770 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK;
771 WREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS, tmp);
772
773 if (indirect)
774 adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr;
775
776 /* enable clock gating */
777 vcn_v2_5_clock_gating_dpg_mode(adev, 0, inst_idx, indirect);
778
779 /* enable VCPU clock */
780 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
781 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
782 tmp |= UVD_VCPU_CNTL__BLK_RST_MASK;
783 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
784 VCN, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect);
785
786 /* disable master interupt */
787 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
788 VCN, 0, mmUVD_MASTINT_EN), 0, 0, indirect);
789
790 /* setup mmUVD_LMI_CTRL */
791 tmp = (0x8 | UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
792 UVD_LMI_CTRL__REQ_MODE_MASK |
793 UVD_LMI_CTRL__CRC_RESET_MASK |
794 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
795 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
796 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
797 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
798 0x00100000L);
799 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
800 VCN, 0, mmUVD_LMI_CTRL), tmp, 0, indirect);
801
802 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
803 VCN, 0, mmUVD_MPC_CNTL),
804 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect);
805
806 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
807 VCN, 0, mmUVD_MPC_SET_MUXA0),
808 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
809 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
810 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
811 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect);
812
813 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
814 VCN, 0, mmUVD_MPC_SET_MUXB0),
815 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
816 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
817 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
818 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect);
819
820 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
821 VCN, 0, mmUVD_MPC_SET_MUX),
822 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
823 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
824 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect);
825
826 vcn_v2_5_mc_resume_dpg_mode(adev, inst_idx, indirect);
827
828 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
829 VCN, 0, mmUVD_REG_XX_MASK), 0x10, 0, indirect);
830 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
831 VCN, 0, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect);
832
833 /* enable LMI MC and UMC channels */
834 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
835 VCN, 0, mmUVD_LMI_CTRL2), 0, 0, indirect);
836
837 /* unblock VCPU register access */
838 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
839 VCN, 0, mmUVD_RB_ARB_CTRL), 0, 0, indirect);
840
841 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
842 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
843 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
844 VCN, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect);
845
846 /* enable master interrupt */
847 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
848 VCN, 0, mmUVD_MASTINT_EN),
849 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
850
851 if (indirect)
852 psp_update_vcn_sram(adev, inst_idx, adev->vcn.inst[inst_idx].dpg_sram_gpu_addr,
853 (uint32_t)((uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_curr_addr -
854 (uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr));
855
856 ring = &adev->vcn.inst[inst_idx].ring_dec;
857 /* force RBC into idle state */
858 rb_bufsz = order_base_2(ring->ring_size);
859 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
860 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
861 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
862 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
863 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
864 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_CNTL, tmp);
865
866 /* Stall DPG before WPTR/RPTR reset */
867 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),
868 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK,
869 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
870 fw_shared->multi_queue.decode_queue_mode |= FW_QUEUE_RING_RESET;
871
872 /* set the write pointer delay */
873 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR_CNTL, 0);
874
875 /* set the wb address */
876 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR_ADDR,
877 (upper_32_bits(ring->gpu_addr) >> 2));
878
879 /* program the RB_BASE for ring buffer */
880 WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
881 lower_32_bits(ring->gpu_addr));
882 WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
883 upper_32_bits(ring->gpu_addr));
884
885 /* Initialize the ring buffer's read and write pointers */
886 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR, 0);
887
888 WREG32_SOC15(VCN, inst_idx, mmUVD_SCRATCH2, 0);
889
890 ring->wptr = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR);
891 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR,
892 lower_32_bits(ring->wptr));
893
894 fw_shared->multi_queue.decode_queue_mode &= ~FW_QUEUE_RING_RESET;
895 /* Unstall DPG */
896 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),
897 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
898
899 return 0;
900 }
901
vcn_v2_5_start(struct amdgpu_device * adev)902 static int vcn_v2_5_start(struct amdgpu_device *adev)
903 {
904 struct amdgpu_ring *ring;
905 uint32_t rb_bufsz, tmp;
906 int i, j, k, r;
907
908 if (adev->pm.dpm_enabled)
909 amdgpu_dpm_enable_uvd(adev, true);
910
911 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
912 if (adev->vcn.harvest_config & (1 << i))
913 continue;
914 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
915 r = vcn_v2_5_start_dpg_mode(adev, i, adev->vcn.indirect_sram);
916 continue;
917 }
918
919 /* disable register anti-hang mechanism */
920 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_POWER_STATUS), 0,
921 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
922
923 /* set uvd status busy */
924 tmp = RREG32_SOC15(VCN, i, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;
925 WREG32_SOC15(VCN, i, mmUVD_STATUS, tmp);
926 }
927
928 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
929 return 0;
930
931 /*SW clock gating */
932 vcn_v2_5_disable_clock_gating(adev);
933
934 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
935 if (adev->vcn.harvest_config & (1 << i))
936 continue;
937 /* enable VCPU clock */
938 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),
939 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK);
940
941 /* disable master interrupt */
942 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 0,
943 ~UVD_MASTINT_EN__VCPU_EN_MASK);
944
945 /* setup mmUVD_LMI_CTRL */
946 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL);
947 tmp &= ~0xff;
948 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL, tmp | 0x8|
949 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
950 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
951 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
952 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
953
954 /* setup mmUVD_MPC_CNTL */
955 tmp = RREG32_SOC15(VCN, i, mmUVD_MPC_CNTL);
956 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
957 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
958 WREG32_SOC15(VCN, i, mmUVD_MPC_CNTL, tmp);
959
960 /* setup UVD_MPC_SET_MUXA0 */
961 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXA0,
962 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
963 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
964 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
965 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));
966
967 /* setup UVD_MPC_SET_MUXB0 */
968 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXB0,
969 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
970 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
971 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
972 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
973
974 /* setup mmUVD_MPC_SET_MUX */
975 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUX,
976 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
977 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
978 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
979 }
980
981 vcn_v2_5_mc_resume(adev);
982
983 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
984 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[i].fw_shared_cpu_addr;
985 if (adev->vcn.harvest_config & (1 << i))
986 continue;
987 /* VCN global tiling registers */
988 WREG32_SOC15(VCN, i, mmUVD_GFX8_ADDR_CONFIG,
989 adev->gfx.config.gb_addr_config);
990 WREG32_SOC15(VCN, i, mmUVD_GFX8_ADDR_CONFIG,
991 adev->gfx.config.gb_addr_config);
992
993 /* enable LMI MC and UMC channels */
994 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_LMI_CTRL2), 0,
995 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
996
997 /* unblock VCPU register access */
998 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), 0,
999 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
1000
1001 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,
1002 ~UVD_VCPU_CNTL__BLK_RST_MASK);
1003
1004 for (k = 0; k < 10; ++k) {
1005 uint32_t status;
1006
1007 for (j = 0; j < 100; ++j) {
1008 status = RREG32_SOC15(VCN, i, mmUVD_STATUS);
1009 if (status & 2)
1010 break;
1011 if (amdgpu_emu_mode == 1)
1012 msleep(500);
1013 else
1014 mdelay(10);
1015 }
1016 r = 0;
1017 if (status & 2)
1018 break;
1019
1020 DRM_ERROR("VCN decode not responding, trying to reset the VCPU!!!\n");
1021 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),
1022 UVD_VCPU_CNTL__BLK_RST_MASK,
1023 ~UVD_VCPU_CNTL__BLK_RST_MASK);
1024 mdelay(10);
1025 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,
1026 ~UVD_VCPU_CNTL__BLK_RST_MASK);
1027
1028 mdelay(10);
1029 r = -1;
1030 }
1031
1032 if (r) {
1033 DRM_ERROR("VCN decode not responding, giving up!!!\n");
1034 return r;
1035 }
1036
1037 /* enable master interrupt */
1038 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN),
1039 UVD_MASTINT_EN__VCPU_EN_MASK,
1040 ~UVD_MASTINT_EN__VCPU_EN_MASK);
1041
1042 /* clear the busy bit of VCN_STATUS */
1043 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS), 0,
1044 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
1045
1046 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_VMID, 0);
1047
1048 ring = &adev->vcn.inst[i].ring_dec;
1049 /* force RBC into idle state */
1050 rb_bufsz = order_base_2(ring->ring_size);
1051 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
1052 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
1053 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
1054 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
1055 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
1056 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_CNTL, tmp);
1057
1058 fw_shared->multi_queue.decode_queue_mode |= FW_QUEUE_RING_RESET;
1059 /* program the RB_BASE for ring buffer */
1060 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
1061 lower_32_bits(ring->gpu_addr));
1062 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
1063 upper_32_bits(ring->gpu_addr));
1064
1065 /* Initialize the ring buffer's read and write pointers */
1066 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR, 0);
1067
1068 ring->wptr = RREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR);
1069 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_WPTR,
1070 lower_32_bits(ring->wptr));
1071 fw_shared->multi_queue.decode_queue_mode &= ~FW_QUEUE_RING_RESET;
1072
1073 fw_shared->multi_queue.encode_generalpurpose_queue_mode |= FW_QUEUE_RING_RESET;
1074 ring = &adev->vcn.inst[i].ring_enc[0];
1075 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1076 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1077 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO, ring->gpu_addr);
1078 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
1079 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE, ring->ring_size / 4);
1080 fw_shared->multi_queue.encode_generalpurpose_queue_mode &= ~FW_QUEUE_RING_RESET;
1081
1082 fw_shared->multi_queue.encode_lowlatency_queue_mode |= FW_QUEUE_RING_RESET;
1083 ring = &adev->vcn.inst[i].ring_enc[1];
1084 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
1085 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1086 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO2, ring->gpu_addr);
1087 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
1088 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE2, ring->ring_size / 4);
1089 fw_shared->multi_queue.encode_lowlatency_queue_mode &= ~FW_QUEUE_RING_RESET;
1090 }
1091
1092 return 0;
1093 }
1094
vcn_v2_5_mmsch_start(struct amdgpu_device * adev,struct amdgpu_mm_table * table)1095 static int vcn_v2_5_mmsch_start(struct amdgpu_device *adev,
1096 struct amdgpu_mm_table *table)
1097 {
1098 uint32_t data = 0, loop = 0, size = 0;
1099 uint64_t addr = table->gpu_addr;
1100 struct mmsch_v1_1_init_header *header = NULL;
1101
1102 header = (struct mmsch_v1_1_init_header *)table->cpu_addr;
1103 size = header->total_size;
1104
1105 /*
1106 * 1, write to vce_mmsch_vf_ctx_addr_lo/hi register with GPU mc addr of
1107 * memory descriptor location
1108 */
1109 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_LO, lower_32_bits(addr));
1110 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_HI, upper_32_bits(addr));
1111
1112 /* 2, update vmid of descriptor */
1113 data = RREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID);
1114 data &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK;
1115 /* use domain0 for MM scheduler */
1116 data |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT);
1117 WREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID, data);
1118
1119 /* 3, notify mmsch about the size of this descriptor */
1120 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_SIZE, size);
1121
1122 /* 4, set resp to zero */
1123 WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP, 0);
1124
1125 /*
1126 * 5, kick off the initialization and wait until
1127 * VCE_MMSCH_VF_MAILBOX_RESP becomes non-zero
1128 */
1129 WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_HOST, 0x10000001);
1130
1131 data = RREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP);
1132 loop = 10;
1133 while ((data & 0x10000002) != 0x10000002) {
1134 udelay(100);
1135 data = RREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP);
1136 loop--;
1137 if (!loop)
1138 break;
1139 }
1140
1141 if (!loop) {
1142 dev_err(adev->dev,
1143 "failed to init MMSCH, mmMMSCH_VF_MAILBOX_RESP = %x\n",
1144 data);
1145 return -EBUSY;
1146 }
1147
1148 return 0;
1149 }
1150
vcn_v2_5_sriov_start(struct amdgpu_device * adev)1151 static int vcn_v2_5_sriov_start(struct amdgpu_device *adev)
1152 {
1153 struct amdgpu_ring *ring;
1154 uint32_t offset, size, tmp, i, rb_bufsz;
1155 uint32_t table_size = 0;
1156 struct mmsch_v1_0_cmd_direct_write direct_wt = { { 0 } };
1157 struct mmsch_v1_0_cmd_direct_read_modify_write direct_rd_mod_wt = { { 0 } };
1158 struct mmsch_v1_0_cmd_end end = { { 0 } };
1159 uint32_t *init_table = adev->virt.mm_table.cpu_addr;
1160 struct mmsch_v1_1_init_header *header = (struct mmsch_v1_1_init_header *)init_table;
1161
1162 direct_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_WRITE;
1163 direct_rd_mod_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE;
1164 end.cmd_header.command_type = MMSCH_COMMAND__END;
1165
1166 header->version = MMSCH_VERSION;
1167 header->total_size = sizeof(struct mmsch_v1_1_init_header) >> 2;
1168 init_table += header->total_size;
1169
1170 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1171 header->eng[i].table_offset = header->total_size;
1172 header->eng[i].init_status = 0;
1173 header->eng[i].table_size = 0;
1174
1175 table_size = 0;
1176
1177 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(
1178 SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS),
1179 ~UVD_STATUS__UVD_BUSY, UVD_STATUS__UVD_BUSY);
1180
1181 size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
1182 /* mc resume*/
1183 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1184 MMSCH_V1_0_INSERT_DIRECT_WT(
1185 SOC15_REG_OFFSET(VCN, i,
1186 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
1187 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_lo);
1188 MMSCH_V1_0_INSERT_DIRECT_WT(
1189 SOC15_REG_OFFSET(VCN, i,
1190 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
1191 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_hi);
1192 offset = 0;
1193 MMSCH_V1_0_INSERT_DIRECT_WT(
1194 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_OFFSET0), 0);
1195 } else {
1196 MMSCH_V1_0_INSERT_DIRECT_WT(
1197 SOC15_REG_OFFSET(VCN, i,
1198 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
1199 lower_32_bits(adev->vcn.inst[i].gpu_addr));
1200 MMSCH_V1_0_INSERT_DIRECT_WT(
1201 SOC15_REG_OFFSET(VCN, i,
1202 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
1203 upper_32_bits(adev->vcn.inst[i].gpu_addr));
1204 offset = size;
1205 MMSCH_V1_0_INSERT_DIRECT_WT(
1206 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_OFFSET0),
1207 AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
1208 }
1209
1210 MMSCH_V1_0_INSERT_DIRECT_WT(
1211 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_SIZE0),
1212 size);
1213 MMSCH_V1_0_INSERT_DIRECT_WT(
1214 SOC15_REG_OFFSET(VCN, i,
1215 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
1216 lower_32_bits(adev->vcn.inst[i].gpu_addr + offset));
1217 MMSCH_V1_0_INSERT_DIRECT_WT(
1218 SOC15_REG_OFFSET(VCN, i,
1219 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
1220 upper_32_bits(adev->vcn.inst[i].gpu_addr + offset));
1221 MMSCH_V1_0_INSERT_DIRECT_WT(
1222 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_OFFSET1),
1223 0);
1224 MMSCH_V1_0_INSERT_DIRECT_WT(
1225 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_SIZE1),
1226 AMDGPU_VCN_STACK_SIZE);
1227 MMSCH_V1_0_INSERT_DIRECT_WT(
1228 SOC15_REG_OFFSET(VCN, i,
1229 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
1230 lower_32_bits(adev->vcn.inst[i].gpu_addr + offset +
1231 AMDGPU_VCN_STACK_SIZE));
1232 MMSCH_V1_0_INSERT_DIRECT_WT(
1233 SOC15_REG_OFFSET(VCN, i,
1234 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
1235 upper_32_bits(adev->vcn.inst[i].gpu_addr + offset +
1236 AMDGPU_VCN_STACK_SIZE));
1237 MMSCH_V1_0_INSERT_DIRECT_WT(
1238 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_OFFSET2),
1239 0);
1240 MMSCH_V1_0_INSERT_DIRECT_WT(
1241 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_SIZE2),
1242 AMDGPU_VCN_CONTEXT_SIZE);
1243
1244 ring = &adev->vcn.inst[i].ring_enc[0];
1245 ring->wptr = 0;
1246
1247 MMSCH_V1_0_INSERT_DIRECT_WT(
1248 SOC15_REG_OFFSET(VCN, i, mmUVD_RB_BASE_LO),
1249 lower_32_bits(ring->gpu_addr));
1250 MMSCH_V1_0_INSERT_DIRECT_WT(
1251 SOC15_REG_OFFSET(VCN, i, mmUVD_RB_BASE_HI),
1252 upper_32_bits(ring->gpu_addr));
1253 MMSCH_V1_0_INSERT_DIRECT_WT(
1254 SOC15_REG_OFFSET(VCN, i, mmUVD_RB_SIZE),
1255 ring->ring_size / 4);
1256
1257 ring = &adev->vcn.inst[i].ring_dec;
1258 ring->wptr = 0;
1259 MMSCH_V1_0_INSERT_DIRECT_WT(
1260 SOC15_REG_OFFSET(VCN, i,
1261 mmUVD_LMI_RBC_RB_64BIT_BAR_LOW),
1262 lower_32_bits(ring->gpu_addr));
1263 MMSCH_V1_0_INSERT_DIRECT_WT(
1264 SOC15_REG_OFFSET(VCN, i,
1265 mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH),
1266 upper_32_bits(ring->gpu_addr));
1267
1268 /* force RBC into idle state */
1269 rb_bufsz = order_base_2(ring->ring_size);
1270 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
1271 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
1272 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
1273 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
1274 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
1275 MMSCH_V1_0_INSERT_DIRECT_WT(
1276 SOC15_REG_OFFSET(VCN, i, mmUVD_RBC_RB_CNTL), tmp);
1277
1278 /* add end packet */
1279 memcpy((void *)init_table, &end, sizeof(struct mmsch_v1_0_cmd_end));
1280 table_size += sizeof(struct mmsch_v1_0_cmd_end) / 4;
1281 init_table += sizeof(struct mmsch_v1_0_cmd_end) / 4;
1282
1283 /* refine header */
1284 header->eng[i].table_size = table_size;
1285 header->total_size += table_size;
1286 }
1287
1288 return vcn_v2_5_mmsch_start(adev, &adev->virt.mm_table);
1289 }
1290
vcn_v2_5_stop_dpg_mode(struct amdgpu_device * adev,int inst_idx)1291 static int vcn_v2_5_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx)
1292 {
1293 uint32_t tmp;
1294
1295 /* Wait for power status to be 1 */
1296 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1,
1297 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1298
1299 /* wait for read ptr to be equal to write ptr */
1300 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR);
1301 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF);
1302
1303 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2);
1304 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF);
1305
1306 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF;
1307 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF);
1308
1309 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1,
1310 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1311
1312 /* disable dynamic power gating mode */
1313 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 0,
1314 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
1315
1316 return 0;
1317 }
1318
vcn_v2_5_stop(struct amdgpu_device * adev)1319 static int vcn_v2_5_stop(struct amdgpu_device *adev)
1320 {
1321 uint32_t tmp;
1322 int i, r = 0;
1323
1324 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1325 if (adev->vcn.harvest_config & (1 << i))
1326 continue;
1327 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
1328 r = vcn_v2_5_stop_dpg_mode(adev, i);
1329 continue;
1330 }
1331
1332 /* wait for vcn idle */
1333 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7);
1334 if (r)
1335 return r;
1336
1337 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
1338 UVD_LMI_STATUS__READ_CLEAN_MASK |
1339 UVD_LMI_STATUS__WRITE_CLEAN_MASK |
1340 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
1341 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp);
1342 if (r)
1343 return r;
1344
1345 /* block LMI UMC channel */
1346 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2);
1347 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;
1348 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2, tmp);
1349
1350 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK|
1351 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
1352 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp);
1353 if (r)
1354 return r;
1355
1356 /* block VCPU register access */
1357 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL),
1358 UVD_RB_ARB_CTRL__VCPU_DIS_MASK,
1359 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
1360
1361 /* reset VCPU */
1362 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),
1363 UVD_VCPU_CNTL__BLK_RST_MASK,
1364 ~UVD_VCPU_CNTL__BLK_RST_MASK);
1365
1366 /* disable VCPU clock */
1367 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,
1368 ~(UVD_VCPU_CNTL__CLK_EN_MASK));
1369
1370 /* clear status */
1371 WREG32_SOC15(VCN, i, mmUVD_STATUS, 0);
1372
1373 vcn_v2_5_enable_clock_gating(adev);
1374
1375 /* enable register anti-hang mechanism */
1376 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_POWER_STATUS),
1377 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK,
1378 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1379 }
1380
1381 if (adev->pm.dpm_enabled)
1382 amdgpu_dpm_enable_uvd(adev, false);
1383
1384 return 0;
1385 }
1386
vcn_v2_5_pause_dpg_mode(struct amdgpu_device * adev,int inst_idx,struct dpg_pause_state * new_state)1387 static int vcn_v2_5_pause_dpg_mode(struct amdgpu_device *adev,
1388 int inst_idx, struct dpg_pause_state *new_state)
1389 {
1390 struct amdgpu_ring *ring;
1391 uint32_t reg_data = 0;
1392 int ret_code = 0;
1393
1394 /* pause/unpause if state is changed */
1395 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) {
1396 DRM_DEBUG("dpg pause state changed %d -> %d",
1397 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based);
1398 reg_data = RREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE) &
1399 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
1400
1401 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) {
1402 ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 0x1,
1403 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1404
1405 if (!ret_code) {
1406 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared_cpu_addr;
1407
1408 /* pause DPG */
1409 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
1410 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data);
1411
1412 /* wait for ACK */
1413 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_DPG_PAUSE,
1414 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK,
1415 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
1416
1417 /* Stall DPG before WPTR/RPTR reset */
1418 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),
1419 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK,
1420 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
1421
1422 /* Restore */
1423 fw_shared->multi_queue.encode_generalpurpose_queue_mode |= FW_QUEUE_RING_RESET;
1424 ring = &adev->vcn.inst[inst_idx].ring_enc[0];
1425 ring->wptr = 0;
1426 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO, ring->gpu_addr);
1427 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
1428 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE, ring->ring_size / 4);
1429 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1430 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1431 fw_shared->multi_queue.encode_generalpurpose_queue_mode &= ~FW_QUEUE_RING_RESET;
1432
1433 fw_shared->multi_queue.encode_lowlatency_queue_mode |= FW_QUEUE_RING_RESET;
1434 ring = &adev->vcn.inst[inst_idx].ring_enc[1];
1435 ring->wptr = 0;
1436 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO2, ring->gpu_addr);
1437 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
1438 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE2, ring->ring_size / 4);
1439 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
1440 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1441 fw_shared->multi_queue.encode_lowlatency_queue_mode &= ~FW_QUEUE_RING_RESET;
1442
1443 /* Unstall DPG */
1444 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),
1445 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
1446
1447 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS,
1448 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1449 }
1450 } else {
1451 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
1452 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data);
1453 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 0x1,
1454 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1455 }
1456 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based;
1457 }
1458
1459 return 0;
1460 }
1461
1462 /**
1463 * vcn_v2_5_dec_ring_get_rptr - get read pointer
1464 *
1465 * @ring: amdgpu_ring pointer
1466 *
1467 * Returns the current hardware read pointer
1468 */
vcn_v2_5_dec_ring_get_rptr(struct amdgpu_ring * ring)1469 static uint64_t vcn_v2_5_dec_ring_get_rptr(struct amdgpu_ring *ring)
1470 {
1471 struct amdgpu_device *adev = ring->adev;
1472
1473 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_RPTR);
1474 }
1475
1476 /**
1477 * vcn_v2_5_dec_ring_get_wptr - get write pointer
1478 *
1479 * @ring: amdgpu_ring pointer
1480 *
1481 * Returns the current hardware write pointer
1482 */
vcn_v2_5_dec_ring_get_wptr(struct amdgpu_ring * ring)1483 static uint64_t vcn_v2_5_dec_ring_get_wptr(struct amdgpu_ring *ring)
1484 {
1485 struct amdgpu_device *adev = ring->adev;
1486
1487 if (ring->use_doorbell)
1488 return adev->wb.wb[ring->wptr_offs];
1489 else
1490 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR);
1491 }
1492
1493 /**
1494 * vcn_v2_5_dec_ring_set_wptr - set write pointer
1495 *
1496 * @ring: amdgpu_ring pointer
1497 *
1498 * Commits the write pointer to the hardware
1499 */
vcn_v2_5_dec_ring_set_wptr(struct amdgpu_ring * ring)1500 static void vcn_v2_5_dec_ring_set_wptr(struct amdgpu_ring *ring)
1501 {
1502 struct amdgpu_device *adev = ring->adev;
1503
1504 if (ring->use_doorbell) {
1505 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
1506 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
1507 } else {
1508 WREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
1509 }
1510 }
1511
1512 static const struct amdgpu_ring_funcs vcn_v2_5_dec_ring_vm_funcs = {
1513 .type = AMDGPU_RING_TYPE_VCN_DEC,
1514 .align_mask = 0xf,
1515 .vmhub = AMDGPU_MMHUB_1,
1516 .get_rptr = vcn_v2_5_dec_ring_get_rptr,
1517 .get_wptr = vcn_v2_5_dec_ring_get_wptr,
1518 .set_wptr = vcn_v2_5_dec_ring_set_wptr,
1519 .emit_frame_size =
1520 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
1521 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
1522 8 + /* vcn_v2_0_dec_ring_emit_vm_flush */
1523 14 + 14 + /* vcn_v2_0_dec_ring_emit_fence x2 vm fence */
1524 6,
1525 .emit_ib_size = 8, /* vcn_v2_0_dec_ring_emit_ib */
1526 .emit_ib = vcn_v2_0_dec_ring_emit_ib,
1527 .emit_fence = vcn_v2_0_dec_ring_emit_fence,
1528 .emit_vm_flush = vcn_v2_0_dec_ring_emit_vm_flush,
1529 .test_ring = vcn_v2_0_dec_ring_test_ring,
1530 .test_ib = amdgpu_vcn_dec_ring_test_ib,
1531 .insert_nop = vcn_v2_0_dec_ring_insert_nop,
1532 .insert_start = vcn_v2_0_dec_ring_insert_start,
1533 .insert_end = vcn_v2_0_dec_ring_insert_end,
1534 .pad_ib = amdgpu_ring_generic_pad_ib,
1535 .begin_use = amdgpu_vcn_ring_begin_use,
1536 .end_use = amdgpu_vcn_ring_end_use,
1537 .emit_wreg = vcn_v2_0_dec_ring_emit_wreg,
1538 .emit_reg_wait = vcn_v2_0_dec_ring_emit_reg_wait,
1539 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1540 };
1541
1542 static const struct amdgpu_ring_funcs vcn_v2_6_dec_ring_vm_funcs = {
1543 .type = AMDGPU_RING_TYPE_VCN_DEC,
1544 .align_mask = 0xf,
1545 .vmhub = AMDGPU_MMHUB_0,
1546 .get_rptr = vcn_v2_5_dec_ring_get_rptr,
1547 .get_wptr = vcn_v2_5_dec_ring_get_wptr,
1548 .set_wptr = vcn_v2_5_dec_ring_set_wptr,
1549 .emit_frame_size =
1550 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
1551 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
1552 8 + /* vcn_v2_0_dec_ring_emit_vm_flush */
1553 14 + 14 + /* vcn_v2_0_dec_ring_emit_fence x2 vm fence */
1554 6,
1555 .emit_ib_size = 8, /* vcn_v2_0_dec_ring_emit_ib */
1556 .emit_ib = vcn_v2_0_dec_ring_emit_ib,
1557 .emit_fence = vcn_v2_0_dec_ring_emit_fence,
1558 .emit_vm_flush = vcn_v2_0_dec_ring_emit_vm_flush,
1559 .test_ring = vcn_v2_0_dec_ring_test_ring,
1560 .test_ib = amdgpu_vcn_dec_ring_test_ib,
1561 .insert_nop = vcn_v2_0_dec_ring_insert_nop,
1562 .insert_start = vcn_v2_0_dec_ring_insert_start,
1563 .insert_end = vcn_v2_0_dec_ring_insert_end,
1564 .pad_ib = amdgpu_ring_generic_pad_ib,
1565 .begin_use = amdgpu_vcn_ring_begin_use,
1566 .end_use = amdgpu_vcn_ring_end_use,
1567 .emit_wreg = vcn_v2_0_dec_ring_emit_wreg,
1568 .emit_reg_wait = vcn_v2_0_dec_ring_emit_reg_wait,
1569 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1570 };
1571
1572 /**
1573 * vcn_v2_5_enc_ring_get_rptr - get enc read pointer
1574 *
1575 * @ring: amdgpu_ring pointer
1576 *
1577 * Returns the current hardware enc read pointer
1578 */
vcn_v2_5_enc_ring_get_rptr(struct amdgpu_ring * ring)1579 static uint64_t vcn_v2_5_enc_ring_get_rptr(struct amdgpu_ring *ring)
1580 {
1581 struct amdgpu_device *adev = ring->adev;
1582
1583 if (ring == &adev->vcn.inst[ring->me].ring_enc[0])
1584 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR);
1585 else
1586 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR2);
1587 }
1588
1589 /**
1590 * vcn_v2_5_enc_ring_get_wptr - get enc write pointer
1591 *
1592 * @ring: amdgpu_ring pointer
1593 *
1594 * Returns the current hardware enc write pointer
1595 */
vcn_v2_5_enc_ring_get_wptr(struct amdgpu_ring * ring)1596 static uint64_t vcn_v2_5_enc_ring_get_wptr(struct amdgpu_ring *ring)
1597 {
1598 struct amdgpu_device *adev = ring->adev;
1599
1600 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) {
1601 if (ring->use_doorbell)
1602 return adev->wb.wb[ring->wptr_offs];
1603 else
1604 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR);
1605 } else {
1606 if (ring->use_doorbell)
1607 return adev->wb.wb[ring->wptr_offs];
1608 else
1609 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2);
1610 }
1611 }
1612
1613 /**
1614 * vcn_v2_5_enc_ring_set_wptr - set enc write pointer
1615 *
1616 * @ring: amdgpu_ring pointer
1617 *
1618 * Commits the enc write pointer to the hardware
1619 */
vcn_v2_5_enc_ring_set_wptr(struct amdgpu_ring * ring)1620 static void vcn_v2_5_enc_ring_set_wptr(struct amdgpu_ring *ring)
1621 {
1622 struct amdgpu_device *adev = ring->adev;
1623
1624 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) {
1625 if (ring->use_doorbell) {
1626 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
1627 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
1628 } else {
1629 WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1630 }
1631 } else {
1632 if (ring->use_doorbell) {
1633 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
1634 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
1635 } else {
1636 WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1637 }
1638 }
1639 }
1640
1641 static const struct amdgpu_ring_funcs vcn_v2_5_enc_ring_vm_funcs = {
1642 .type = AMDGPU_RING_TYPE_VCN_ENC,
1643 .align_mask = 0x3f,
1644 .nop = VCN_ENC_CMD_NO_OP,
1645 .vmhub = AMDGPU_MMHUB_1,
1646 .get_rptr = vcn_v2_5_enc_ring_get_rptr,
1647 .get_wptr = vcn_v2_5_enc_ring_get_wptr,
1648 .set_wptr = vcn_v2_5_enc_ring_set_wptr,
1649 .emit_frame_size =
1650 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1651 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
1652 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */
1653 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */
1654 1, /* vcn_v2_0_enc_ring_insert_end */
1655 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */
1656 .emit_ib = vcn_v2_0_enc_ring_emit_ib,
1657 .emit_fence = vcn_v2_0_enc_ring_emit_fence,
1658 .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush,
1659 .test_ring = amdgpu_vcn_enc_ring_test_ring,
1660 .test_ib = amdgpu_vcn_enc_ring_test_ib,
1661 .insert_nop = amdgpu_ring_insert_nop,
1662 .insert_end = vcn_v2_0_enc_ring_insert_end,
1663 .pad_ib = amdgpu_ring_generic_pad_ib,
1664 .begin_use = amdgpu_vcn_ring_begin_use,
1665 .end_use = amdgpu_vcn_ring_end_use,
1666 .emit_wreg = vcn_v2_0_enc_ring_emit_wreg,
1667 .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait,
1668 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1669 };
1670
1671 static const struct amdgpu_ring_funcs vcn_v2_6_enc_ring_vm_funcs = {
1672 .type = AMDGPU_RING_TYPE_VCN_ENC,
1673 .align_mask = 0x3f,
1674 .nop = VCN_ENC_CMD_NO_OP,
1675 .vmhub = AMDGPU_MMHUB_0,
1676 .get_rptr = vcn_v2_5_enc_ring_get_rptr,
1677 .get_wptr = vcn_v2_5_enc_ring_get_wptr,
1678 .set_wptr = vcn_v2_5_enc_ring_set_wptr,
1679 .emit_frame_size =
1680 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1681 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
1682 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */
1683 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */
1684 1, /* vcn_v2_0_enc_ring_insert_end */
1685 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */
1686 .emit_ib = vcn_v2_0_enc_ring_emit_ib,
1687 .emit_fence = vcn_v2_0_enc_ring_emit_fence,
1688 .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush,
1689 .test_ring = amdgpu_vcn_enc_ring_test_ring,
1690 .test_ib = amdgpu_vcn_enc_ring_test_ib,
1691 .insert_nop = amdgpu_ring_insert_nop,
1692 .insert_end = vcn_v2_0_enc_ring_insert_end,
1693 .pad_ib = amdgpu_ring_generic_pad_ib,
1694 .begin_use = amdgpu_vcn_ring_begin_use,
1695 .end_use = amdgpu_vcn_ring_end_use,
1696 .emit_wreg = vcn_v2_0_enc_ring_emit_wreg,
1697 .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait,
1698 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1699 };
1700
vcn_v2_5_set_dec_ring_funcs(struct amdgpu_device * adev)1701 static void vcn_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev)
1702 {
1703 int i;
1704
1705 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1706 if (adev->vcn.harvest_config & (1 << i))
1707 continue;
1708 if (adev->ip_versions[UVD_HWIP][0] == IP_VERSION(2, 5, 0))
1709 adev->vcn.inst[i].ring_dec.funcs = &vcn_v2_5_dec_ring_vm_funcs;
1710 else /* CHIP_ALDEBARAN */
1711 adev->vcn.inst[i].ring_dec.funcs = &vcn_v2_6_dec_ring_vm_funcs;
1712 adev->vcn.inst[i].ring_dec.me = i;
1713 DRM_INFO("VCN(%d) decode is enabled in VM mode\n", i);
1714 }
1715 }
1716
vcn_v2_5_set_enc_ring_funcs(struct amdgpu_device * adev)1717 static void vcn_v2_5_set_enc_ring_funcs(struct amdgpu_device *adev)
1718 {
1719 int i, j;
1720
1721 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
1722 if (adev->vcn.harvest_config & (1 << j))
1723 continue;
1724 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
1725 if (adev->ip_versions[UVD_HWIP][0] == IP_VERSION(2, 5, 0))
1726 adev->vcn.inst[j].ring_enc[i].funcs = &vcn_v2_5_enc_ring_vm_funcs;
1727 else /* CHIP_ALDEBARAN */
1728 adev->vcn.inst[j].ring_enc[i].funcs = &vcn_v2_6_enc_ring_vm_funcs;
1729 adev->vcn.inst[j].ring_enc[i].me = j;
1730 }
1731 DRM_INFO("VCN(%d) encode is enabled in VM mode\n", j);
1732 }
1733 }
1734
vcn_v2_5_is_idle(void * handle)1735 static bool vcn_v2_5_is_idle(void *handle)
1736 {
1737 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1738 int i, ret = 1;
1739
1740 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1741 if (adev->vcn.harvest_config & (1 << i))
1742 continue;
1743 ret &= (RREG32_SOC15(VCN, i, mmUVD_STATUS) == UVD_STATUS__IDLE);
1744 }
1745
1746 return ret;
1747 }
1748
vcn_v2_5_wait_for_idle(void * handle)1749 static int vcn_v2_5_wait_for_idle(void *handle)
1750 {
1751 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1752 int i, ret = 0;
1753
1754 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1755 if (adev->vcn.harvest_config & (1 << i))
1756 continue;
1757 ret = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE,
1758 UVD_STATUS__IDLE);
1759 if (ret)
1760 return ret;
1761 }
1762
1763 return ret;
1764 }
1765
vcn_v2_5_set_clockgating_state(void * handle,enum amd_clockgating_state state)1766 static int vcn_v2_5_set_clockgating_state(void *handle,
1767 enum amd_clockgating_state state)
1768 {
1769 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1770 bool enable = (state == AMD_CG_STATE_GATE);
1771
1772 if (amdgpu_sriov_vf(adev))
1773 return 0;
1774
1775 if (enable) {
1776 if (!vcn_v2_5_is_idle(handle))
1777 return -EBUSY;
1778 vcn_v2_5_enable_clock_gating(adev);
1779 } else {
1780 vcn_v2_5_disable_clock_gating(adev);
1781 }
1782
1783 return 0;
1784 }
1785
vcn_v2_5_set_powergating_state(void * handle,enum amd_powergating_state state)1786 static int vcn_v2_5_set_powergating_state(void *handle,
1787 enum amd_powergating_state state)
1788 {
1789 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1790 int ret;
1791
1792 if (amdgpu_sriov_vf(adev))
1793 return 0;
1794
1795 if(state == adev->vcn.cur_state)
1796 return 0;
1797
1798 if (state == AMD_PG_STATE_GATE)
1799 ret = vcn_v2_5_stop(adev);
1800 else
1801 ret = vcn_v2_5_start(adev);
1802
1803 if(!ret)
1804 adev->vcn.cur_state = state;
1805
1806 return ret;
1807 }
1808
vcn_v2_5_set_interrupt_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned type,enum amdgpu_interrupt_state state)1809 static int vcn_v2_5_set_interrupt_state(struct amdgpu_device *adev,
1810 struct amdgpu_irq_src *source,
1811 unsigned type,
1812 enum amdgpu_interrupt_state state)
1813 {
1814 return 0;
1815 }
1816
vcn_v2_5_process_interrupt(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1817 static int vcn_v2_5_process_interrupt(struct amdgpu_device *adev,
1818 struct amdgpu_irq_src *source,
1819 struct amdgpu_iv_entry *entry)
1820 {
1821 uint32_t ip_instance;
1822
1823 switch (entry->client_id) {
1824 case SOC15_IH_CLIENTID_VCN:
1825 ip_instance = 0;
1826 break;
1827 case SOC15_IH_CLIENTID_VCN1:
1828 ip_instance = 1;
1829 break;
1830 default:
1831 DRM_ERROR("Unhandled client id: %d\n", entry->client_id);
1832 return 0;
1833 }
1834
1835 DRM_DEBUG("IH: VCN TRAP\n");
1836
1837 switch (entry->src_id) {
1838 case VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT:
1839 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_dec);
1840 break;
1841 case VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE:
1842 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]);
1843 break;
1844 case VCN_2_0__SRCID__UVD_ENC_LOW_LATENCY:
1845 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[1]);
1846 break;
1847 default:
1848 DRM_ERROR("Unhandled interrupt: %d %d\n",
1849 entry->src_id, entry->src_data[0]);
1850 break;
1851 }
1852
1853 return 0;
1854 }
1855
1856 static const struct amdgpu_irq_src_funcs vcn_v2_5_irq_funcs = {
1857 .set = vcn_v2_5_set_interrupt_state,
1858 .process = vcn_v2_5_process_interrupt,
1859 };
1860
vcn_v2_5_set_irq_funcs(struct amdgpu_device * adev)1861 static void vcn_v2_5_set_irq_funcs(struct amdgpu_device *adev)
1862 {
1863 int i;
1864
1865 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1866 if (adev->vcn.harvest_config & (1 << i))
1867 continue;
1868 adev->vcn.inst[i].irq.num_types = adev->vcn.num_enc_rings + 1;
1869 adev->vcn.inst[i].irq.funcs = &vcn_v2_5_irq_funcs;
1870 }
1871 }
1872
1873 static const struct amd_ip_funcs vcn_v2_5_ip_funcs = {
1874 .name = "vcn_v2_5",
1875 .early_init = vcn_v2_5_early_init,
1876 .late_init = NULL,
1877 .sw_init = vcn_v2_5_sw_init,
1878 .sw_fini = vcn_v2_5_sw_fini,
1879 .hw_init = vcn_v2_5_hw_init,
1880 .hw_fini = vcn_v2_5_hw_fini,
1881 .suspend = vcn_v2_5_suspend,
1882 .resume = vcn_v2_5_resume,
1883 .is_idle = vcn_v2_5_is_idle,
1884 .wait_for_idle = vcn_v2_5_wait_for_idle,
1885 .check_soft_reset = NULL,
1886 .pre_soft_reset = NULL,
1887 .soft_reset = NULL,
1888 .post_soft_reset = NULL,
1889 .set_clockgating_state = vcn_v2_5_set_clockgating_state,
1890 .set_powergating_state = vcn_v2_5_set_powergating_state,
1891 };
1892
1893 static const struct amd_ip_funcs vcn_v2_6_ip_funcs = {
1894 .name = "vcn_v2_6",
1895 .early_init = vcn_v2_5_early_init,
1896 .late_init = NULL,
1897 .sw_init = vcn_v2_5_sw_init,
1898 .sw_fini = vcn_v2_5_sw_fini,
1899 .hw_init = vcn_v2_5_hw_init,
1900 .hw_fini = vcn_v2_5_hw_fini,
1901 .suspend = vcn_v2_5_suspend,
1902 .resume = vcn_v2_5_resume,
1903 .is_idle = vcn_v2_5_is_idle,
1904 .wait_for_idle = vcn_v2_5_wait_for_idle,
1905 .check_soft_reset = NULL,
1906 .pre_soft_reset = NULL,
1907 .soft_reset = NULL,
1908 .post_soft_reset = NULL,
1909 .set_clockgating_state = vcn_v2_5_set_clockgating_state,
1910 .set_powergating_state = vcn_v2_5_set_powergating_state,
1911 };
1912
1913 const struct amdgpu_ip_block_version vcn_v2_5_ip_block =
1914 {
1915 .type = AMD_IP_BLOCK_TYPE_VCN,
1916 .major = 2,
1917 .minor = 5,
1918 .rev = 0,
1919 .funcs = &vcn_v2_5_ip_funcs,
1920 };
1921
1922 const struct amdgpu_ip_block_version vcn_v2_6_ip_block =
1923 {
1924 .type = AMD_IP_BLOCK_TYPE_VCN,
1925 .major = 2,
1926 .minor = 6,
1927 .rev = 0,
1928 .funcs = &vcn_v2_6_ip_funcs,
1929 };
1930