1 /*
2 * Copyright 2018 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include <linux/slab.h>
27
28 #include "dm_services.h"
29
30 #include "include/logger_interface.h"
31
32 #include "../dce110/irq_service_dce110.h"
33
34 #include "dcn/dcn_2_1_0_offset.h"
35 #include "dcn/dcn_2_1_0_sh_mask.h"
36 #include "renoir_ip_offset.h"
37
38
39 #include "irq_service_dcn21.h"
40
41 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
42
to_dal_irq_source_dcn21(struct irq_service * irq_service,uint32_t src_id,uint32_t ext_id)43 enum dc_irq_source to_dal_irq_source_dcn21(
44 struct irq_service *irq_service,
45 uint32_t src_id,
46 uint32_t ext_id)
47 {
48 switch (src_id) {
49 case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP:
50 return DC_IRQ_SOURCE_VBLANK1;
51 case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP:
52 return DC_IRQ_SOURCE_VBLANK2;
53 case DCN_1_0__SRCID__DC_D3_OTG_VSTARTUP:
54 return DC_IRQ_SOURCE_VBLANK3;
55 case DCN_1_0__SRCID__DC_D4_OTG_VSTARTUP:
56 return DC_IRQ_SOURCE_VBLANK4;
57 case DCN_1_0__SRCID__DC_D5_OTG_VSTARTUP:
58 return DC_IRQ_SOURCE_VBLANK5;
59 case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP:
60 return DC_IRQ_SOURCE_VBLANK6;
61 case DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT:
62 return DC_IRQ_SOURCE_DMCUB_OUTBOX;
63 case DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL:
64 return DC_IRQ_SOURCE_DC1_VLINE0;
65 case DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL:
66 return DC_IRQ_SOURCE_DC2_VLINE0;
67 case DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL:
68 return DC_IRQ_SOURCE_DC3_VLINE0;
69 case DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL:
70 return DC_IRQ_SOURCE_DC4_VLINE0;
71 case DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL:
72 return DC_IRQ_SOURCE_DC5_VLINE0;
73 case DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL:
74 return DC_IRQ_SOURCE_DC6_VLINE0;
75 case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT:
76 return DC_IRQ_SOURCE_PFLIP1;
77 case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT:
78 return DC_IRQ_SOURCE_PFLIP2;
79 case DCN_1_0__SRCID__HUBP2_FLIP_INTERRUPT:
80 return DC_IRQ_SOURCE_PFLIP3;
81 case DCN_1_0__SRCID__HUBP3_FLIP_INTERRUPT:
82 return DC_IRQ_SOURCE_PFLIP4;
83 case DCN_1_0__SRCID__HUBP4_FLIP_INTERRUPT:
84 return DC_IRQ_SOURCE_PFLIP5;
85 case DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT:
86 return DC_IRQ_SOURCE_PFLIP6;
87 case DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
88 return DC_IRQ_SOURCE_VUPDATE1;
89 case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
90 return DC_IRQ_SOURCE_VUPDATE2;
91 case DCN_1_0__SRCID__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
92 return DC_IRQ_SOURCE_VUPDATE3;
93 case DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
94 return DC_IRQ_SOURCE_VUPDATE4;
95 case DCN_1_0__SRCID__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
96 return DC_IRQ_SOURCE_VUPDATE5;
97 case DCN_1_0__SRCID__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
98 return DC_IRQ_SOURCE_VUPDATE6;
99
100 case DCN_1_0__SRCID__DC_HPD1_INT:
101 /* generic src_id for all HPD and HPDRX interrupts */
102 switch (ext_id) {
103 case DCN_1_0__CTXID__DC_HPD1_INT:
104 return DC_IRQ_SOURCE_HPD1;
105 case DCN_1_0__CTXID__DC_HPD2_INT:
106 return DC_IRQ_SOURCE_HPD2;
107 case DCN_1_0__CTXID__DC_HPD3_INT:
108 return DC_IRQ_SOURCE_HPD3;
109 case DCN_1_0__CTXID__DC_HPD4_INT:
110 return DC_IRQ_SOURCE_HPD4;
111 case DCN_1_0__CTXID__DC_HPD5_INT:
112 return DC_IRQ_SOURCE_HPD5;
113 case DCN_1_0__CTXID__DC_HPD6_INT:
114 return DC_IRQ_SOURCE_HPD6;
115 case DCN_1_0__CTXID__DC_HPD1_RX_INT:
116 return DC_IRQ_SOURCE_HPD1RX;
117 case DCN_1_0__CTXID__DC_HPD2_RX_INT:
118 return DC_IRQ_SOURCE_HPD2RX;
119 case DCN_1_0__CTXID__DC_HPD3_RX_INT:
120 return DC_IRQ_SOURCE_HPD3RX;
121 case DCN_1_0__CTXID__DC_HPD4_RX_INT:
122 return DC_IRQ_SOURCE_HPD4RX;
123 case DCN_1_0__CTXID__DC_HPD5_RX_INT:
124 return DC_IRQ_SOURCE_HPD5RX;
125 case DCN_1_0__CTXID__DC_HPD6_RX_INT:
126 return DC_IRQ_SOURCE_HPD6RX;
127 default:
128 return DC_IRQ_SOURCE_INVALID;
129 }
130 break;
131
132 default:
133 break;
134 }
135 return DC_IRQ_SOURCE_INVALID;
136 }
137
dc_get_hpd_state_dcn21(struct irq_service * irq_service,enum dc_irq_source source)138 uint32_t dc_get_hpd_state_dcn21(struct irq_service *irq_service, enum dc_irq_source source)
139 {
140 const struct irq_source_info *info;
141 uint32_t addr;
142 uint32_t value;
143 uint32_t current_status;
144
145 info = find_irq_source_info(irq_service, source);
146 if (!info)
147 return 0;
148
149 addr = info->status_reg;
150 if (!addr)
151 return 0;
152
153 value = dm_read_reg(irq_service->ctx, addr);
154 current_status =
155 get_reg_field_value(
156 value,
157 HPD0_DC_HPD_INT_STATUS,
158 DC_HPD_SENSE);
159
160 return current_status;
161 }
162
hpd_ack(struct irq_service * irq_service,const struct irq_source_info * info)163 static bool hpd_ack(
164 struct irq_service *irq_service,
165 const struct irq_source_info *info)
166 {
167 uint32_t addr = info->status_reg;
168 uint32_t value = dm_read_reg(irq_service->ctx, addr);
169 uint32_t current_status =
170 get_reg_field_value(
171 value,
172 HPD0_DC_HPD_INT_STATUS,
173 DC_HPD_SENSE_DELAYED);
174
175 dal_irq_service_ack_generic(irq_service, info);
176
177 value = dm_read_reg(irq_service->ctx, info->enable_reg);
178
179 set_reg_field_value(
180 value,
181 current_status ? 0 : 1,
182 HPD0_DC_HPD_INT_CONTROL,
183 DC_HPD_INT_POLARITY);
184
185 dm_write_reg(irq_service->ctx, info->enable_reg, value);
186
187 return true;
188 }
189
190 static const struct irq_source_info_funcs hpd_irq_info_funcs = {
191 .set = NULL,
192 .ack = hpd_ack
193 };
194
195 static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
196 .set = NULL,
197 .ack = NULL
198 };
199
200 static const struct irq_source_info_funcs pflip_irq_info_funcs = {
201 .set = NULL,
202 .ack = NULL
203 };
204
205 static const struct irq_source_info_funcs vblank_irq_info_funcs = {
206 .set = NULL,
207 .ack = NULL
208 };
209
210 static const struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = {
211 .set = NULL,
212 .ack = NULL
213 };
214
215 static const struct irq_source_info_funcs dmub_outbox_irq_info_funcs = {
216 .set = NULL,
217 .ack = NULL
218 };
219
220 static const struct irq_source_info_funcs vline0_irq_info_funcs = {
221 .set = NULL,
222 .ack = NULL
223 };
224
225 #undef BASE_INNER
226 #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
227
228 /* compile time expand base address. */
229 #define BASE(seg) \
230 BASE_INNER(seg)
231
232
233 #define SRI(reg_name, block, id)\
234 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
235 mm ## block ## id ## _ ## reg_name
236
237 #define SRI_DMUB(reg_name)\
238 BASE(mm ## reg_name ## _BASE_IDX) + \
239 mm ## reg_name
240
241 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
242 .enable_reg = SRI(reg1, block, reg_num),\
243 .enable_mask = \
244 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
245 .enable_value = {\
246 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
247 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
248 },\
249 .ack_reg = SRI(reg2, block, reg_num),\
250 .ack_mask = \
251 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
252 .ack_value = \
253 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
254
255 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\
256 .enable_reg = SRI_DMUB(reg1),\
257 .enable_mask = \
258 reg1 ## __ ## mask1 ## _MASK,\
259 .enable_value = {\
260 reg1 ## __ ## mask1 ## _MASK,\
261 ~reg1 ## __ ## mask1 ## _MASK \
262 },\
263 .ack_reg = SRI_DMUB(reg2),\
264 .ack_mask = \
265 reg2 ## __ ## mask2 ## _MASK,\
266 .ack_value = \
267 reg2 ## __ ## mask2 ## _MASK \
268
269 #define hpd_int_entry(reg_num)\
270 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
271 IRQ_REG_ENTRY(HPD, reg_num,\
272 DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\
273 DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\
274 .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
275 .funcs = &hpd_irq_info_funcs\
276 }
277
278 #define hpd_rx_int_entry(reg_num)\
279 [DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
280 IRQ_REG_ENTRY(HPD, reg_num,\
281 DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\
282 DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\
283 .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
284 .funcs = &hpd_rx_irq_info_funcs\
285 }
286 #define pflip_int_entry(reg_num)\
287 [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
288 IRQ_REG_ENTRY(HUBPREQ, reg_num,\
289 DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK,\
290 DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_CLEAR),\
291 .funcs = &pflip_irq_info_funcs\
292 }
293
294 #define vupdate_int_entry(reg_num)\
295 [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
296 IRQ_REG_ENTRY(OTG, reg_num,\
297 OTG_GLOBAL_SYNC_STATUS, VUPDATE_INT_EN,\
298 OTG_GLOBAL_SYNC_STATUS, VUPDATE_EVENT_CLEAR),\
299 .funcs = &vblank_irq_info_funcs\
300 }
301
302 /* vupdate_no_lock_int_entry maps to DC_IRQ_SOURCE_VUPDATEx, to match semantic
303 * of DCE's DC_IRQ_SOURCE_VUPDATEx.
304 */
305 #define vupdate_no_lock_int_entry(reg_num)\
306 [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
307 IRQ_REG_ENTRY(OTG, reg_num,\
308 OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_INT_EN,\
309 OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR),\
310 .funcs = &vupdate_no_lock_irq_info_funcs\
311 }
312
313 #define vblank_int_entry(reg_num)\
314 [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
315 IRQ_REG_ENTRY(OTG, reg_num,\
316 OTG_GLOBAL_SYNC_STATUS, VSTARTUP_INT_EN,\
317 OTG_GLOBAL_SYNC_STATUS, VSTARTUP_EVENT_CLEAR),\
318 .funcs = &vblank_irq_info_funcs\
319 }
320
321 #define vline0_int_entry(reg_num)\
322 [DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\
323 IRQ_REG_ENTRY(OTG, reg_num,\
324 OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE,\
325 OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_CLEAR),\
326 .funcs = &vline0_irq_info_funcs\
327 }
328
329 #define dmub_outbox_int_entry()\
330 [DC_IRQ_SOURCE_DMCUB_OUTBOX] = {\
331 IRQ_REG_ENTRY_DMUB(DMCUB_INTERRUPT_ENABLE, DMCUB_OUTBOX1_READY_INT_EN,\
332 DMCUB_INTERRUPT_ACK, DMCUB_OUTBOX1_READY_INT_ACK),\
333 .funcs = &dmub_outbox_irq_info_funcs\
334 }
335
336 #define dummy_irq_entry() \
337 {\
338 .funcs = &dummy_irq_info_funcs\
339 }
340
341 #define i2c_int_entry(reg_num) \
342 [DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
343
344 #define dp_sink_int_entry(reg_num) \
345 [DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
346
347 #define gpio_pad_int_entry(reg_num) \
348 [DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
349
350 #define dc_underflow_int_entry(reg_num) \
351 [DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
352
353 static const struct irq_source_info_funcs dummy_irq_info_funcs = {
354 .set = dal_irq_service_dummy_set,
355 .ack = dal_irq_service_dummy_ack
356 };
357
358 static const struct irq_source_info
359 irq_source_info_dcn21[DAL_IRQ_SOURCES_NUMBER] = {
360 [DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(),
361 hpd_int_entry(0),
362 hpd_int_entry(1),
363 hpd_int_entry(2),
364 hpd_int_entry(3),
365 hpd_int_entry(4),
366 hpd_rx_int_entry(0),
367 hpd_rx_int_entry(1),
368 hpd_rx_int_entry(2),
369 hpd_rx_int_entry(3),
370 hpd_rx_int_entry(4),
371 i2c_int_entry(1),
372 i2c_int_entry(2),
373 i2c_int_entry(3),
374 i2c_int_entry(4),
375 i2c_int_entry(5),
376 i2c_int_entry(6),
377 dp_sink_int_entry(1),
378 dp_sink_int_entry(2),
379 dp_sink_int_entry(3),
380 dp_sink_int_entry(4),
381 dp_sink_int_entry(5),
382 dp_sink_int_entry(6),
383 [DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(),
384 pflip_int_entry(0),
385 pflip_int_entry(1),
386 pflip_int_entry(2),
387 pflip_int_entry(3),
388 [DC_IRQ_SOURCE_PFLIP5] = dummy_irq_entry(),
389 [DC_IRQ_SOURCE_PFLIP6] = dummy_irq_entry(),
390 [DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),
391 gpio_pad_int_entry(0),
392 gpio_pad_int_entry(1),
393 gpio_pad_int_entry(2),
394 gpio_pad_int_entry(3),
395 gpio_pad_int_entry(4),
396 gpio_pad_int_entry(5),
397 gpio_pad_int_entry(6),
398 gpio_pad_int_entry(7),
399 gpio_pad_int_entry(8),
400 gpio_pad_int_entry(9),
401 gpio_pad_int_entry(10),
402 gpio_pad_int_entry(11),
403 gpio_pad_int_entry(12),
404 gpio_pad_int_entry(13),
405 gpio_pad_int_entry(14),
406 gpio_pad_int_entry(15),
407 gpio_pad_int_entry(16),
408 gpio_pad_int_entry(17),
409 gpio_pad_int_entry(18),
410 gpio_pad_int_entry(19),
411 gpio_pad_int_entry(20),
412 gpio_pad_int_entry(21),
413 gpio_pad_int_entry(22),
414 gpio_pad_int_entry(23),
415 gpio_pad_int_entry(24),
416 gpio_pad_int_entry(25),
417 gpio_pad_int_entry(26),
418 gpio_pad_int_entry(27),
419 gpio_pad_int_entry(28),
420 gpio_pad_int_entry(29),
421 gpio_pad_int_entry(30),
422 dc_underflow_int_entry(1),
423 dc_underflow_int_entry(2),
424 dc_underflow_int_entry(3),
425 dc_underflow_int_entry(4),
426 dc_underflow_int_entry(5),
427 dc_underflow_int_entry(6),
428 [DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
429 [DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
430 vupdate_int_entry(0),
431 vupdate_int_entry(1),
432 vupdate_int_entry(2),
433 vupdate_int_entry(3),
434 vupdate_int_entry(4),
435 vupdate_int_entry(5),
436 vupdate_no_lock_int_entry(0),
437 vupdate_no_lock_int_entry(1),
438 vupdate_no_lock_int_entry(2),
439 vupdate_no_lock_int_entry(3),
440 vupdate_no_lock_int_entry(4),
441 vupdate_no_lock_int_entry(5),
442 vblank_int_entry(0),
443 vblank_int_entry(1),
444 vblank_int_entry(2),
445 vblank_int_entry(3),
446 vblank_int_entry(4),
447 vblank_int_entry(5),
448 vline0_int_entry(0),
449 vline0_int_entry(1),
450 vline0_int_entry(2),
451 vline0_int_entry(3),
452 vline0_int_entry(4),
453 vline0_int_entry(5),
454 dmub_outbox_int_entry(),
455 };
456
457 static const struct irq_service_funcs irq_service_funcs_dcn21 = {
458 .to_dal_irq_source = to_dal_irq_source_dcn21
459 };
460
dcn21_irq_construct(struct irq_service * irq_service,struct irq_service_init_data * init_data)461 static void dcn21_irq_construct(
462 struct irq_service *irq_service,
463 struct irq_service_init_data *init_data)
464 {
465 dal_irq_service_construct(irq_service, init_data);
466
467 irq_service->info = irq_source_info_dcn21;
468 irq_service->funcs = &irq_service_funcs_dcn21;
469 }
470
dal_irq_service_dcn21_create(struct irq_service_init_data * init_data)471 struct irq_service *dal_irq_service_dcn21_create(
472 struct irq_service_init_data *init_data)
473 {
474 struct irq_service *irq_service = kzalloc(sizeof(*irq_service),
475 GFP_KERNEL);
476
477 if (!irq_service)
478 return NULL;
479
480 dcn21_irq_construct(irq_service, init_data);
481 return irq_service;
482 }
483