1 /*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #define SWSMU_CODE_LAYER_L2
25
26 #include "amdgpu.h"
27 #include "amdgpu_smu.h"
28 #include "smu_v11_0.h"
29 #include "smu11_driver_if_vangogh.h"
30 #include "vangogh_ppt.h"
31 #include "smu_v11_5_ppsmc.h"
32 #include "smu_v11_5_pmfw.h"
33 #include "smu_cmn.h"
34 #include "soc15_common.h"
35 #include "asic_reg/gc/gc_10_3_0_offset.h"
36 #include "asic_reg/gc/gc_10_3_0_sh_mask.h"
37 #include <asm/processor.h>
38
39 /*
40 * DO NOT use these for err/warn/info/debug messages.
41 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
42 * They are more MGPU friendly.
43 */
44 #undef pr_err
45 #undef pr_warn
46 #undef pr_info
47 #undef pr_debug
48
49 #define FEATURE_MASK(feature) (1ULL << feature)
50 #define SMC_DPM_FEATURE ( \
51 FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \
52 FEATURE_MASK(FEATURE_VCN_DPM_BIT) | \
53 FEATURE_MASK(FEATURE_FCLK_DPM_BIT) | \
54 FEATURE_MASK(FEATURE_SOCCLK_DPM_BIT) | \
55 FEATURE_MASK(FEATURE_MP0CLK_DPM_BIT) | \
56 FEATURE_MASK(FEATURE_LCLK_DPM_BIT) | \
57 FEATURE_MASK(FEATURE_SHUBCLK_DPM_BIT) | \
58 FEATURE_MASK(FEATURE_DCFCLK_DPM_BIT)| \
59 FEATURE_MASK(FEATURE_GFX_DPM_BIT))
60
61 static struct cmn2asic_msg_mapping vangogh_message_map[SMU_MSG_MAX_COUNT] = {
62 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 0),
63 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 0),
64 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 0),
65 MSG_MAP(EnableGfxOff, PPSMC_MSG_EnableGfxOff, 0),
66 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0),
67 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0),
68 MSG_MAP(PowerDownIspByTile, PPSMC_MSG_PowerDownIspByTile, 0),
69 MSG_MAP(PowerUpIspByTile, PPSMC_MSG_PowerUpIspByTile, 0),
70 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0),
71 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0),
72 MSG_MAP(RlcPowerNotify, PPSMC_MSG_RlcPowerNotify, 0),
73 MSG_MAP(SetHardMinVcn, PPSMC_MSG_SetHardMinVcn, 0),
74 MSG_MAP(SetSoftMinGfxclk, PPSMC_MSG_SetSoftMinGfxclk, 0),
75 MSG_MAP(ActiveProcessNotify, PPSMC_MSG_ActiveProcessNotify, 0),
76 MSG_MAP(SetHardMinIspiclkByFreq, PPSMC_MSG_SetHardMinIspiclkByFreq, 0),
77 MSG_MAP(SetHardMinIspxclkByFreq, PPSMC_MSG_SetHardMinIspxclkByFreq, 0),
78 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 0),
79 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 0),
80 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 0),
81 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0),
82 MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDeviceDriverReset, 0),
83 MSG_MAP(GetEnabledSmuFeatures, PPSMC_MSG_GetEnabledSmuFeatures, 0),
84 MSG_MAP(SetHardMinSocclkByFreq, PPSMC_MSG_SetHardMinSocclkByFreq, 0),
85 MSG_MAP(SetSoftMinFclk, PPSMC_MSG_SetSoftMinFclk, 0),
86 MSG_MAP(SetSoftMinVcn, PPSMC_MSG_SetSoftMinVcn, 0),
87 MSG_MAP(EnablePostCode, PPSMC_MSG_EnablePostCode, 0),
88 MSG_MAP(GetGfxclkFrequency, PPSMC_MSG_GetGfxclkFrequency, 0),
89 MSG_MAP(GetFclkFrequency, PPSMC_MSG_GetFclkFrequency, 0),
90 MSG_MAP(SetSoftMaxGfxClk, PPSMC_MSG_SetSoftMaxGfxClk, 0),
91 MSG_MAP(SetHardMinGfxClk, PPSMC_MSG_SetHardMinGfxClk, 0),
92 MSG_MAP(SetSoftMaxSocclkByFreq, PPSMC_MSG_SetSoftMaxSocclkByFreq, 0),
93 MSG_MAP(SetSoftMaxFclkByFreq, PPSMC_MSG_SetSoftMaxFclkByFreq, 0),
94 MSG_MAP(SetSoftMaxVcn, PPSMC_MSG_SetSoftMaxVcn, 0),
95 MSG_MAP(SetPowerLimitPercentage, PPSMC_MSG_SetPowerLimitPercentage, 0),
96 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0),
97 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0),
98 MSG_MAP(SetHardMinFclkByFreq, PPSMC_MSG_SetHardMinFclkByFreq, 0),
99 MSG_MAP(SetSoftMinSocclkByFreq, PPSMC_MSG_SetSoftMinSocclkByFreq, 0),
100 MSG_MAP(PowerUpCvip, PPSMC_MSG_PowerUpCvip, 0),
101 MSG_MAP(PowerDownCvip, PPSMC_MSG_PowerDownCvip, 0),
102 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0),
103 MSG_MAP(GetThermalLimit, PPSMC_MSG_GetThermalLimit, 0),
104 MSG_MAP(GetCurrentTemperature, PPSMC_MSG_GetCurrentTemperature, 0),
105 MSG_MAP(GetCurrentPower, PPSMC_MSG_GetCurrentPower, 0),
106 MSG_MAP(GetCurrentVoltage, PPSMC_MSG_GetCurrentVoltage, 0),
107 MSG_MAP(GetCurrentCurrent, PPSMC_MSG_GetCurrentCurrent, 0),
108 MSG_MAP(GetAverageCpuActivity, PPSMC_MSG_GetAverageCpuActivity, 0),
109 MSG_MAP(GetAverageGfxActivity, PPSMC_MSG_GetAverageGfxActivity, 0),
110 MSG_MAP(GetAveragePower, PPSMC_MSG_GetAveragePower, 0),
111 MSG_MAP(GetAverageTemperature, PPSMC_MSG_GetAverageTemperature, 0),
112 MSG_MAP(SetAveragePowerTimeConstant, PPSMC_MSG_SetAveragePowerTimeConstant, 0),
113 MSG_MAP(SetAverageActivityTimeConstant, PPSMC_MSG_SetAverageActivityTimeConstant, 0),
114 MSG_MAP(SetAverageTemperatureTimeConstant, PPSMC_MSG_SetAverageTemperatureTimeConstant, 0),
115 MSG_MAP(SetMitigationEndHysteresis, PPSMC_MSG_SetMitigationEndHysteresis, 0),
116 MSG_MAP(GetCurrentFreq, PPSMC_MSG_GetCurrentFreq, 0),
117 MSG_MAP(SetReducedPptLimit, PPSMC_MSG_SetReducedPptLimit, 0),
118 MSG_MAP(SetReducedThermalLimit, PPSMC_MSG_SetReducedThermalLimit, 0),
119 MSG_MAP(DramLogSetDramAddr, PPSMC_MSG_DramLogSetDramAddr, 0),
120 MSG_MAP(StartDramLogging, PPSMC_MSG_StartDramLogging, 0),
121 MSG_MAP(StopDramLogging, PPSMC_MSG_StopDramLogging, 0),
122 MSG_MAP(SetSoftMinCclk, PPSMC_MSG_SetSoftMinCclk, 0),
123 MSG_MAP(SetSoftMaxCclk, PPSMC_MSG_SetSoftMaxCclk, 0),
124 MSG_MAP(RequestActiveWgp, PPSMC_MSG_RequestActiveWgp, 0),
125 MSG_MAP(SetFastPPTLimit, PPSMC_MSG_SetFastPPTLimit, 0),
126 MSG_MAP(SetSlowPPTLimit, PPSMC_MSG_SetSlowPPTLimit, 0),
127 MSG_MAP(GetFastPPTLimit, PPSMC_MSG_GetFastPPTLimit, 0),
128 MSG_MAP(GetSlowPPTLimit, PPSMC_MSG_GetSlowPPTLimit, 0),
129 };
130
131 static struct cmn2asic_mapping vangogh_feature_mask_map[SMU_FEATURE_COUNT] = {
132 FEA_MAP(PPT),
133 FEA_MAP(TDC),
134 FEA_MAP(THERMAL),
135 FEA_MAP(DS_GFXCLK),
136 FEA_MAP(DS_SOCCLK),
137 FEA_MAP(DS_LCLK),
138 FEA_MAP(DS_FCLK),
139 FEA_MAP(DS_MP1CLK),
140 FEA_MAP(DS_MP0CLK),
141 FEA_MAP(ATHUB_PG),
142 FEA_MAP(CCLK_DPM),
143 FEA_MAP(FAN_CONTROLLER),
144 FEA_MAP(ULV),
145 FEA_MAP(VCN_DPM),
146 FEA_MAP(LCLK_DPM),
147 FEA_MAP(SHUBCLK_DPM),
148 FEA_MAP(DCFCLK_DPM),
149 FEA_MAP(DS_DCFCLK),
150 FEA_MAP(S0I2),
151 FEA_MAP(SMU_LOW_POWER),
152 FEA_MAP(GFX_DEM),
153 FEA_MAP(PSI),
154 FEA_MAP(PROCHOT),
155 FEA_MAP(CPUOFF),
156 FEA_MAP(STAPM),
157 FEA_MAP(S0I3),
158 FEA_MAP(DF_CSTATES),
159 FEA_MAP(PERF_LIMIT),
160 FEA_MAP(CORE_DLDO),
161 FEA_MAP(RSMU_LOW_POWER),
162 FEA_MAP(SMN_LOW_POWER),
163 FEA_MAP(THM_LOW_POWER),
164 FEA_MAP(SMUIO_LOW_POWER),
165 FEA_MAP(MP1_LOW_POWER),
166 FEA_MAP(DS_VCN),
167 FEA_MAP(CPPC),
168 FEA_MAP(OS_CSTATES),
169 FEA_MAP(ISP_DPM),
170 FEA_MAP(A55_DPM),
171 FEA_MAP(CVIP_DSP_DPM),
172 FEA_MAP(MSMU_LOW_POWER),
173 FEA_MAP_REVERSE(SOCCLK),
174 FEA_MAP_REVERSE(FCLK),
175 FEA_MAP_HALF_REVERSE(GFX),
176 };
177
178 static struct cmn2asic_mapping vangogh_table_map[SMU_TABLE_COUNT] = {
179 TAB_MAP_VALID(WATERMARKS),
180 TAB_MAP_VALID(SMU_METRICS),
181 TAB_MAP_VALID(CUSTOM_DPM),
182 TAB_MAP_VALID(DPMCLOCKS),
183 };
184
185 static struct cmn2asic_mapping vangogh_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
186 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
187 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
188 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT),
189 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT),
190 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
191 };
192
193 static const uint8_t vangogh_throttler_map[] = {
194 [THROTTLER_STATUS_BIT_SPL] = (SMU_THROTTLER_SPL_BIT),
195 [THROTTLER_STATUS_BIT_FPPT] = (SMU_THROTTLER_FPPT_BIT),
196 [THROTTLER_STATUS_BIT_SPPT] = (SMU_THROTTLER_SPPT_BIT),
197 [THROTTLER_STATUS_BIT_SPPT_APU] = (SMU_THROTTLER_SPPT_APU_BIT),
198 [THROTTLER_STATUS_BIT_THM_CORE] = (SMU_THROTTLER_TEMP_CORE_BIT),
199 [THROTTLER_STATUS_BIT_THM_GFX] = (SMU_THROTTLER_TEMP_GPU_BIT),
200 [THROTTLER_STATUS_BIT_THM_SOC] = (SMU_THROTTLER_TEMP_SOC_BIT),
201 [THROTTLER_STATUS_BIT_TDC_VDD] = (SMU_THROTTLER_TDC_VDD_BIT),
202 [THROTTLER_STATUS_BIT_TDC_SOC] = (SMU_THROTTLER_TDC_SOC_BIT),
203 [THROTTLER_STATUS_BIT_TDC_GFX] = (SMU_THROTTLER_TDC_GFX_BIT),
204 [THROTTLER_STATUS_BIT_TDC_CVIP] = (SMU_THROTTLER_TDC_CVIP_BIT),
205 };
206
vangogh_tables_init(struct smu_context * smu)207 static int vangogh_tables_init(struct smu_context *smu)
208 {
209 struct smu_table_context *smu_table = &smu->smu_table;
210 struct smu_table *tables = smu_table->tables;
211 struct amdgpu_device *adev = smu->adev;
212 uint32_t if_version;
213 uint32_t ret = 0;
214
215 ret = smu_cmn_get_smc_version(smu, &if_version, NULL);
216 if (ret) {
217 dev_err(adev->dev, "Failed to get smu if version!\n");
218 goto err0_out;
219 }
220
221 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
222 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
223 SMU_TABLE_INIT(tables, SMU_TABLE_DPMCLOCKS, sizeof(DpmClocks_t),
224 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
225 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
226 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
227 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF, sizeof(DpmActivityMonitorCoeffExt_t),
228 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
229
230 if (if_version < 0x3) {
231 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_legacy_t),
232 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
233 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_legacy_t), GFP_KERNEL);
234 } else {
235 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
236 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
237 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
238 }
239 if (!smu_table->metrics_table)
240 goto err0_out;
241 smu_table->metrics_time = 0;
242
243 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_2);
244 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
245 if (!smu_table->gpu_metrics_table)
246 goto err1_out;
247
248 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
249 if (!smu_table->watermarks_table)
250 goto err2_out;
251
252 smu_table->clocks_table = kzalloc(sizeof(DpmClocks_t), GFP_KERNEL);
253 if (!smu_table->clocks_table)
254 goto err3_out;
255
256 return 0;
257
258 err3_out:
259 kfree(smu_table->watermarks_table);
260 err2_out:
261 kfree(smu_table->gpu_metrics_table);
262 err1_out:
263 kfree(smu_table->metrics_table);
264 err0_out:
265 return -ENOMEM;
266 }
267
vangogh_get_legacy_smu_metrics_data(struct smu_context * smu,MetricsMember_t member,uint32_t * value)268 static int vangogh_get_legacy_smu_metrics_data(struct smu_context *smu,
269 MetricsMember_t member,
270 uint32_t *value)
271 {
272 struct smu_table_context *smu_table = &smu->smu_table;
273 SmuMetrics_legacy_t *metrics = (SmuMetrics_legacy_t *)smu_table->metrics_table;
274 int ret = 0;
275
276 mutex_lock(&smu->metrics_lock);
277
278 ret = smu_cmn_get_metrics_table_locked(smu,
279 NULL,
280 false);
281 if (ret) {
282 mutex_unlock(&smu->metrics_lock);
283 return ret;
284 }
285
286 switch (member) {
287 case METRICS_CURR_GFXCLK:
288 *value = metrics->GfxclkFrequency;
289 break;
290 case METRICS_AVERAGE_SOCCLK:
291 *value = metrics->SocclkFrequency;
292 break;
293 case METRICS_AVERAGE_VCLK:
294 *value = metrics->VclkFrequency;
295 break;
296 case METRICS_AVERAGE_DCLK:
297 *value = metrics->DclkFrequency;
298 break;
299 case METRICS_CURR_UCLK:
300 *value = metrics->MemclkFrequency;
301 break;
302 case METRICS_AVERAGE_GFXACTIVITY:
303 *value = metrics->GfxActivity / 100;
304 break;
305 case METRICS_AVERAGE_VCNACTIVITY:
306 *value = metrics->UvdActivity;
307 break;
308 case METRICS_AVERAGE_SOCKETPOWER:
309 *value = (metrics->CurrentSocketPower << 8) /
310 1000 ;
311 break;
312 case METRICS_TEMPERATURE_EDGE:
313 *value = metrics->GfxTemperature / 100 *
314 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
315 break;
316 case METRICS_TEMPERATURE_HOTSPOT:
317 *value = metrics->SocTemperature / 100 *
318 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
319 break;
320 case METRICS_THROTTLER_STATUS:
321 *value = metrics->ThrottlerStatus;
322 break;
323 case METRICS_VOLTAGE_VDDGFX:
324 *value = metrics->Voltage[2];
325 break;
326 case METRICS_VOLTAGE_VDDSOC:
327 *value = metrics->Voltage[1];
328 break;
329 case METRICS_AVERAGE_CPUCLK:
330 memcpy(value, &metrics->CoreFrequency[0],
331 smu->cpu_core_num * sizeof(uint16_t));
332 break;
333 default:
334 *value = UINT_MAX;
335 break;
336 }
337
338 mutex_unlock(&smu->metrics_lock);
339
340 return ret;
341 }
342
vangogh_get_smu_metrics_data(struct smu_context * smu,MetricsMember_t member,uint32_t * value)343 static int vangogh_get_smu_metrics_data(struct smu_context *smu,
344 MetricsMember_t member,
345 uint32_t *value)
346 {
347 struct smu_table_context *smu_table = &smu->smu_table;
348 SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
349 int ret = 0;
350
351 mutex_lock(&smu->metrics_lock);
352
353 ret = smu_cmn_get_metrics_table_locked(smu,
354 NULL,
355 false);
356 if (ret) {
357 mutex_unlock(&smu->metrics_lock);
358 return ret;
359 }
360
361 switch (member) {
362 case METRICS_CURR_GFXCLK:
363 *value = metrics->Current.GfxclkFrequency;
364 break;
365 case METRICS_AVERAGE_SOCCLK:
366 *value = metrics->Current.SocclkFrequency;
367 break;
368 case METRICS_AVERAGE_VCLK:
369 *value = metrics->Current.VclkFrequency;
370 break;
371 case METRICS_AVERAGE_DCLK:
372 *value = metrics->Current.DclkFrequency;
373 break;
374 case METRICS_CURR_UCLK:
375 *value = metrics->Current.MemclkFrequency;
376 break;
377 case METRICS_AVERAGE_GFXACTIVITY:
378 *value = metrics->Current.GfxActivity;
379 break;
380 case METRICS_AVERAGE_VCNACTIVITY:
381 *value = metrics->Current.UvdActivity;
382 break;
383 case METRICS_AVERAGE_SOCKETPOWER:
384 *value = (metrics->Current.CurrentSocketPower << 8) /
385 1000;
386 break;
387 case METRICS_TEMPERATURE_EDGE:
388 *value = metrics->Current.GfxTemperature / 100 *
389 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
390 break;
391 case METRICS_TEMPERATURE_HOTSPOT:
392 *value = metrics->Current.SocTemperature / 100 *
393 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
394 break;
395 case METRICS_THROTTLER_STATUS:
396 *value = metrics->Current.ThrottlerStatus;
397 break;
398 case METRICS_VOLTAGE_VDDGFX:
399 *value = metrics->Current.Voltage[2];
400 break;
401 case METRICS_VOLTAGE_VDDSOC:
402 *value = metrics->Current.Voltage[1];
403 break;
404 case METRICS_AVERAGE_CPUCLK:
405 memcpy(value, &metrics->Current.CoreFrequency[0],
406 smu->cpu_core_num * sizeof(uint16_t));
407 break;
408 default:
409 *value = UINT_MAX;
410 break;
411 }
412
413 mutex_unlock(&smu->metrics_lock);
414
415 return ret;
416 }
417
vangogh_common_get_smu_metrics_data(struct smu_context * smu,MetricsMember_t member,uint32_t * value)418 static int vangogh_common_get_smu_metrics_data(struct smu_context *smu,
419 MetricsMember_t member,
420 uint32_t *value)
421 {
422 struct amdgpu_device *adev = smu->adev;
423 uint32_t if_version;
424 int ret = 0;
425
426 ret = smu_cmn_get_smc_version(smu, &if_version, NULL);
427 if (ret) {
428 dev_err(adev->dev, "Failed to get smu if version!\n");
429 return ret;
430 }
431
432 if (if_version < 0x3)
433 ret = vangogh_get_legacy_smu_metrics_data(smu, member, value);
434 else
435 ret = vangogh_get_smu_metrics_data(smu, member, value);
436
437 return ret;
438 }
439
vangogh_allocate_dpm_context(struct smu_context * smu)440 static int vangogh_allocate_dpm_context(struct smu_context *smu)
441 {
442 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
443
444 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
445 GFP_KERNEL);
446 if (!smu_dpm->dpm_context)
447 return -ENOMEM;
448
449 smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
450
451 return 0;
452 }
453
vangogh_init_smc_tables(struct smu_context * smu)454 static int vangogh_init_smc_tables(struct smu_context *smu)
455 {
456 int ret = 0;
457
458 ret = vangogh_tables_init(smu);
459 if (ret)
460 return ret;
461
462 ret = vangogh_allocate_dpm_context(smu);
463 if (ret)
464 return ret;
465
466 #ifdef CONFIG_X86
467 /* AMD x86 APU only */
468 smu->cpu_core_num = boot_cpu_data.x86_max_cores;
469 #else
470 smu->cpu_core_num = 4;
471 #endif
472
473 return smu_v11_0_init_smc_tables(smu);
474 }
475
vangogh_dpm_set_vcn_enable(struct smu_context * smu,bool enable)476 static int vangogh_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
477 {
478 int ret = 0;
479
480 if (enable) {
481 /* vcn dpm on is a prerequisite for vcn power gate messages */
482 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0, NULL);
483 if (ret)
484 return ret;
485 } else {
486 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn, 0, NULL);
487 if (ret)
488 return ret;
489 }
490
491 return ret;
492 }
493
vangogh_dpm_set_jpeg_enable(struct smu_context * smu,bool enable)494 static int vangogh_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
495 {
496 int ret = 0;
497
498 if (enable) {
499 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL);
500 if (ret)
501 return ret;
502 } else {
503 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL);
504 if (ret)
505 return ret;
506 }
507
508 return ret;
509 }
510
vangogh_is_dpm_running(struct smu_context * smu)511 static bool vangogh_is_dpm_running(struct smu_context *smu)
512 {
513 struct amdgpu_device *adev = smu->adev;
514 int ret = 0;
515 uint32_t feature_mask[2];
516 uint64_t feature_enabled;
517
518 /* we need to re-init after suspend so return false */
519 if (adev->in_suspend)
520 return false;
521
522 ret = smu_cmn_get_enabled_32_bits_mask(smu, feature_mask, 2);
523
524 if (ret)
525 return false;
526
527 feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
528 ((uint64_t)feature_mask[1] << 32));
529
530 return !!(feature_enabled & SMC_DPM_FEATURE);
531 }
532
vangogh_get_dpm_clk_limited(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t dpm_level,uint32_t * freq)533 static int vangogh_get_dpm_clk_limited(struct smu_context *smu, enum smu_clk_type clk_type,
534 uint32_t dpm_level, uint32_t *freq)
535 {
536 DpmClocks_t *clk_table = smu->smu_table.clocks_table;
537
538 if (!clk_table || clk_type >= SMU_CLK_COUNT)
539 return -EINVAL;
540
541 switch (clk_type) {
542 case SMU_SOCCLK:
543 if (dpm_level >= clk_table->NumSocClkLevelsEnabled)
544 return -EINVAL;
545 *freq = clk_table->SocClocks[dpm_level];
546 break;
547 case SMU_VCLK:
548 if (dpm_level >= clk_table->VcnClkLevelsEnabled)
549 return -EINVAL;
550 *freq = clk_table->VcnClocks[dpm_level].vclk;
551 break;
552 case SMU_DCLK:
553 if (dpm_level >= clk_table->VcnClkLevelsEnabled)
554 return -EINVAL;
555 *freq = clk_table->VcnClocks[dpm_level].dclk;
556 break;
557 case SMU_UCLK:
558 case SMU_MCLK:
559 if (dpm_level >= clk_table->NumDfPstatesEnabled)
560 return -EINVAL;
561 *freq = clk_table->DfPstateTable[dpm_level].memclk;
562
563 break;
564 case SMU_FCLK:
565 if (dpm_level >= clk_table->NumDfPstatesEnabled)
566 return -EINVAL;
567 *freq = clk_table->DfPstateTable[dpm_level].fclk;
568 break;
569 default:
570 return -EINVAL;
571 }
572
573 return 0;
574 }
575
vangogh_print_legacy_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,char * buf)576 static int vangogh_print_legacy_clk_levels(struct smu_context *smu,
577 enum smu_clk_type clk_type, char *buf)
578 {
579 DpmClocks_t *clk_table = smu->smu_table.clocks_table;
580 SmuMetrics_legacy_t metrics;
581 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
582 int i, size = 0, ret = 0;
583 uint32_t cur_value = 0, value = 0, count = 0;
584 bool cur_value_match_level = false;
585
586 memset(&metrics, 0, sizeof(metrics));
587
588 ret = smu_cmn_get_metrics_table(smu, &metrics, false);
589 if (ret)
590 return ret;
591
592 smu_cmn_get_sysfs_buf(&buf, &size);
593
594 switch (clk_type) {
595 case SMU_OD_SCLK:
596 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
597 size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK");
598 size += sysfs_emit_at(buf, size, "0: %10uMhz\n",
599 (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq);
600 size += sysfs_emit_at(buf, size, "1: %10uMhz\n",
601 (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq);
602 }
603 break;
604 case SMU_OD_CCLK:
605 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
606 size += sysfs_emit_at(buf, size, "CCLK_RANGE in Core%d:\n", smu->cpu_core_id_select);
607 size += sysfs_emit_at(buf, size, "0: %10uMhz\n",
608 (smu->cpu_actual_soft_min_freq > 0) ? smu->cpu_actual_soft_min_freq : smu->cpu_default_soft_min_freq);
609 size += sysfs_emit_at(buf, size, "1: %10uMhz\n",
610 (smu->cpu_actual_soft_max_freq > 0) ? smu->cpu_actual_soft_max_freq : smu->cpu_default_soft_max_freq);
611 }
612 break;
613 case SMU_OD_RANGE:
614 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
615 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
616 size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",
617 smu->gfx_default_hard_min_freq, smu->gfx_default_soft_max_freq);
618 size += sysfs_emit_at(buf, size, "CCLK: %7uMhz %10uMhz\n",
619 smu->cpu_default_soft_min_freq, smu->cpu_default_soft_max_freq);
620 }
621 break;
622 case SMU_SOCCLK:
623 /* the level 3 ~ 6 of socclk use the same frequency for vangogh */
624 count = clk_table->NumSocClkLevelsEnabled;
625 cur_value = metrics.SocclkFrequency;
626 break;
627 case SMU_VCLK:
628 count = clk_table->VcnClkLevelsEnabled;
629 cur_value = metrics.VclkFrequency;
630 break;
631 case SMU_DCLK:
632 count = clk_table->VcnClkLevelsEnabled;
633 cur_value = metrics.DclkFrequency;
634 break;
635 case SMU_MCLK:
636 count = clk_table->NumDfPstatesEnabled;
637 cur_value = metrics.MemclkFrequency;
638 break;
639 case SMU_FCLK:
640 count = clk_table->NumDfPstatesEnabled;
641 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetFclkFrequency, 0, &cur_value);
642 if (ret)
643 return ret;
644 break;
645 default:
646 break;
647 }
648
649 switch (clk_type) {
650 case SMU_SOCCLK:
651 case SMU_VCLK:
652 case SMU_DCLK:
653 case SMU_MCLK:
654 case SMU_FCLK:
655 for (i = 0; i < count; i++) {
656 ret = vangogh_get_dpm_clk_limited(smu, clk_type, i, &value);
657 if (ret)
658 return ret;
659 if (!value)
660 continue;
661 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value,
662 cur_value == value ? "*" : "");
663 if (cur_value == value)
664 cur_value_match_level = true;
665 }
666
667 if (!cur_value_match_level)
668 size += sysfs_emit_at(buf, size, " %uMhz *\n", cur_value);
669 break;
670 default:
671 break;
672 }
673
674 return size;
675 }
676
vangogh_print_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,char * buf)677 static int vangogh_print_clk_levels(struct smu_context *smu,
678 enum smu_clk_type clk_type, char *buf)
679 {
680 DpmClocks_t *clk_table = smu->smu_table.clocks_table;
681 SmuMetrics_t metrics;
682 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
683 int i, size = 0, ret = 0;
684 uint32_t cur_value = 0, value = 0, count = 0;
685 bool cur_value_match_level = false;
686 uint32_t min, max;
687
688 memset(&metrics, 0, sizeof(metrics));
689
690 ret = smu_cmn_get_metrics_table(smu, &metrics, false);
691 if (ret)
692 return ret;
693
694 smu_cmn_get_sysfs_buf(&buf, &size);
695
696 switch (clk_type) {
697 case SMU_OD_SCLK:
698 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
699 size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK");
700 size += sysfs_emit_at(buf, size, "0: %10uMhz\n",
701 (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq);
702 size += sysfs_emit_at(buf, size, "1: %10uMhz\n",
703 (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq);
704 }
705 break;
706 case SMU_OD_CCLK:
707 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
708 size += sysfs_emit_at(buf, size, "CCLK_RANGE in Core%d:\n", smu->cpu_core_id_select);
709 size += sysfs_emit_at(buf, size, "0: %10uMhz\n",
710 (smu->cpu_actual_soft_min_freq > 0) ? smu->cpu_actual_soft_min_freq : smu->cpu_default_soft_min_freq);
711 size += sysfs_emit_at(buf, size, "1: %10uMhz\n",
712 (smu->cpu_actual_soft_max_freq > 0) ? smu->cpu_actual_soft_max_freq : smu->cpu_default_soft_max_freq);
713 }
714 break;
715 case SMU_OD_RANGE:
716 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
717 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
718 size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",
719 smu->gfx_default_hard_min_freq, smu->gfx_default_soft_max_freq);
720 size += sysfs_emit_at(buf, size, "CCLK: %7uMhz %10uMhz\n",
721 smu->cpu_default_soft_min_freq, smu->cpu_default_soft_max_freq);
722 }
723 break;
724 case SMU_SOCCLK:
725 /* the level 3 ~ 6 of socclk use the same frequency for vangogh */
726 count = clk_table->NumSocClkLevelsEnabled;
727 cur_value = metrics.Current.SocclkFrequency;
728 break;
729 case SMU_VCLK:
730 count = clk_table->VcnClkLevelsEnabled;
731 cur_value = metrics.Current.VclkFrequency;
732 break;
733 case SMU_DCLK:
734 count = clk_table->VcnClkLevelsEnabled;
735 cur_value = metrics.Current.DclkFrequency;
736 break;
737 case SMU_MCLK:
738 count = clk_table->NumDfPstatesEnabled;
739 cur_value = metrics.Current.MemclkFrequency;
740 break;
741 case SMU_FCLK:
742 count = clk_table->NumDfPstatesEnabled;
743 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetFclkFrequency, 0, &cur_value);
744 if (ret)
745 return ret;
746 break;
747 case SMU_GFXCLK:
748 case SMU_SCLK:
749 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetGfxclkFrequency, 0, &cur_value);
750 if (ret) {
751 return ret;
752 }
753 break;
754 default:
755 break;
756 }
757
758 switch (clk_type) {
759 case SMU_SOCCLK:
760 case SMU_VCLK:
761 case SMU_DCLK:
762 case SMU_MCLK:
763 case SMU_FCLK:
764 for (i = 0; i < count; i++) {
765 ret = vangogh_get_dpm_clk_limited(smu, clk_type, i, &value);
766 if (ret)
767 return ret;
768 if (!value)
769 continue;
770 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value,
771 cur_value == value ? "*" : "");
772 if (cur_value == value)
773 cur_value_match_level = true;
774 }
775
776 if (!cur_value_match_level)
777 size += sysfs_emit_at(buf, size, " %uMhz *\n", cur_value);
778 break;
779 case SMU_GFXCLK:
780 case SMU_SCLK:
781 min = (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq;
782 max = (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq;
783 if (cur_value == max)
784 i = 2;
785 else if (cur_value == min)
786 i = 0;
787 else
788 i = 1;
789 size += sysfs_emit_at(buf, size, "0: %uMhz %s\n", min,
790 i == 0 ? "*" : "");
791 size += sysfs_emit_at(buf, size, "1: %uMhz %s\n",
792 i == 1 ? cur_value : VANGOGH_UMD_PSTATE_STANDARD_GFXCLK,
793 i == 1 ? "*" : "");
794 size += sysfs_emit_at(buf, size, "2: %uMhz %s\n", max,
795 i == 2 ? "*" : "");
796 break;
797 default:
798 break;
799 }
800
801 return size;
802 }
803
vangogh_common_print_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,char * buf)804 static int vangogh_common_print_clk_levels(struct smu_context *smu,
805 enum smu_clk_type clk_type, char *buf)
806 {
807 struct amdgpu_device *adev = smu->adev;
808 uint32_t if_version;
809 int ret = 0;
810
811 ret = smu_cmn_get_smc_version(smu, &if_version, NULL);
812 if (ret) {
813 dev_err(adev->dev, "Failed to get smu if version!\n");
814 return ret;
815 }
816
817 if (if_version < 0x3)
818 ret = vangogh_print_legacy_clk_levels(smu, clk_type, buf);
819 else
820 ret = vangogh_print_clk_levels(smu, clk_type, buf);
821
822 return ret;
823 }
824
vangogh_get_profiling_clk_mask(struct smu_context * smu,enum amd_dpm_forced_level level,uint32_t * vclk_mask,uint32_t * dclk_mask,uint32_t * mclk_mask,uint32_t * fclk_mask,uint32_t * soc_mask)825 static int vangogh_get_profiling_clk_mask(struct smu_context *smu,
826 enum amd_dpm_forced_level level,
827 uint32_t *vclk_mask,
828 uint32_t *dclk_mask,
829 uint32_t *mclk_mask,
830 uint32_t *fclk_mask,
831 uint32_t *soc_mask)
832 {
833 DpmClocks_t *clk_table = smu->smu_table.clocks_table;
834
835 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
836 if (mclk_mask)
837 *mclk_mask = clk_table->NumDfPstatesEnabled - 1;
838
839 if (fclk_mask)
840 *fclk_mask = clk_table->NumDfPstatesEnabled - 1;
841
842 if (soc_mask)
843 *soc_mask = 0;
844 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
845 if (mclk_mask)
846 *mclk_mask = 0;
847
848 if (fclk_mask)
849 *fclk_mask = 0;
850
851 if (soc_mask)
852 *soc_mask = 1;
853
854 if (vclk_mask)
855 *vclk_mask = 1;
856
857 if (dclk_mask)
858 *dclk_mask = 1;
859 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) {
860 if (mclk_mask)
861 *mclk_mask = 0;
862
863 if (fclk_mask)
864 *fclk_mask = 0;
865
866 if (soc_mask)
867 *soc_mask = 1;
868
869 if (vclk_mask)
870 *vclk_mask = 1;
871
872 if (dclk_mask)
873 *dclk_mask = 1;
874 }
875
876 return 0;
877 }
878
vangogh_clk_dpm_is_enabled(struct smu_context * smu,enum smu_clk_type clk_type)879 static bool vangogh_clk_dpm_is_enabled(struct smu_context *smu,
880 enum smu_clk_type clk_type)
881 {
882 enum smu_feature_mask feature_id = 0;
883
884 switch (clk_type) {
885 case SMU_MCLK:
886 case SMU_UCLK:
887 case SMU_FCLK:
888 feature_id = SMU_FEATURE_DPM_FCLK_BIT;
889 break;
890 case SMU_GFXCLK:
891 case SMU_SCLK:
892 feature_id = SMU_FEATURE_DPM_GFXCLK_BIT;
893 break;
894 case SMU_SOCCLK:
895 feature_id = SMU_FEATURE_DPM_SOCCLK_BIT;
896 break;
897 case SMU_VCLK:
898 case SMU_DCLK:
899 feature_id = SMU_FEATURE_VCN_DPM_BIT;
900 break;
901 default:
902 return true;
903 }
904
905 if (!smu_cmn_feature_is_enabled(smu, feature_id))
906 return false;
907
908 return true;
909 }
910
vangogh_get_dpm_ultimate_freq(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * min,uint32_t * max)911 static int vangogh_get_dpm_ultimate_freq(struct smu_context *smu,
912 enum smu_clk_type clk_type,
913 uint32_t *min,
914 uint32_t *max)
915 {
916 int ret = 0;
917 uint32_t soc_mask;
918 uint32_t vclk_mask;
919 uint32_t dclk_mask;
920 uint32_t mclk_mask;
921 uint32_t fclk_mask;
922 uint32_t clock_limit;
923
924 if (!vangogh_clk_dpm_is_enabled(smu, clk_type)) {
925 switch (clk_type) {
926 case SMU_MCLK:
927 case SMU_UCLK:
928 clock_limit = smu->smu_table.boot_values.uclk;
929 break;
930 case SMU_FCLK:
931 clock_limit = smu->smu_table.boot_values.fclk;
932 break;
933 case SMU_GFXCLK:
934 case SMU_SCLK:
935 clock_limit = smu->smu_table.boot_values.gfxclk;
936 break;
937 case SMU_SOCCLK:
938 clock_limit = smu->smu_table.boot_values.socclk;
939 break;
940 case SMU_VCLK:
941 clock_limit = smu->smu_table.boot_values.vclk;
942 break;
943 case SMU_DCLK:
944 clock_limit = smu->smu_table.boot_values.dclk;
945 break;
946 default:
947 clock_limit = 0;
948 break;
949 }
950
951 /* clock in Mhz unit */
952 if (min)
953 *min = clock_limit / 100;
954 if (max)
955 *max = clock_limit / 100;
956
957 return 0;
958 }
959 if (max) {
960 ret = vangogh_get_profiling_clk_mask(smu,
961 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK,
962 &vclk_mask,
963 &dclk_mask,
964 &mclk_mask,
965 &fclk_mask,
966 &soc_mask);
967 if (ret)
968 goto failed;
969
970 switch (clk_type) {
971 case SMU_UCLK:
972 case SMU_MCLK:
973 ret = vangogh_get_dpm_clk_limited(smu, clk_type, mclk_mask, max);
974 if (ret)
975 goto failed;
976 break;
977 case SMU_SOCCLK:
978 ret = vangogh_get_dpm_clk_limited(smu, clk_type, soc_mask, max);
979 if (ret)
980 goto failed;
981 break;
982 case SMU_FCLK:
983 ret = vangogh_get_dpm_clk_limited(smu, clk_type, fclk_mask, max);
984 if (ret)
985 goto failed;
986 break;
987 case SMU_VCLK:
988 ret = vangogh_get_dpm_clk_limited(smu, clk_type, vclk_mask, max);
989 if (ret)
990 goto failed;
991 break;
992 case SMU_DCLK:
993 ret = vangogh_get_dpm_clk_limited(smu, clk_type, dclk_mask, max);
994 if (ret)
995 goto failed;
996 break;
997 default:
998 ret = -EINVAL;
999 goto failed;
1000 }
1001 }
1002 if (min) {
1003 switch (clk_type) {
1004 case SMU_UCLK:
1005 case SMU_MCLK:
1006 ret = vangogh_get_dpm_clk_limited(smu, clk_type, mclk_mask, min);
1007 if (ret)
1008 goto failed;
1009 break;
1010 case SMU_SOCCLK:
1011 ret = vangogh_get_dpm_clk_limited(smu, clk_type, soc_mask, min);
1012 if (ret)
1013 goto failed;
1014 break;
1015 case SMU_FCLK:
1016 ret = vangogh_get_dpm_clk_limited(smu, clk_type, fclk_mask, min);
1017 if (ret)
1018 goto failed;
1019 break;
1020 case SMU_VCLK:
1021 ret = vangogh_get_dpm_clk_limited(smu, clk_type, vclk_mask, min);
1022 if (ret)
1023 goto failed;
1024 break;
1025 case SMU_DCLK:
1026 ret = vangogh_get_dpm_clk_limited(smu, clk_type, dclk_mask, min);
1027 if (ret)
1028 goto failed;
1029 break;
1030 default:
1031 ret = -EINVAL;
1032 goto failed;
1033 }
1034 }
1035 failed:
1036 return ret;
1037 }
1038
vangogh_get_power_profile_mode(struct smu_context * smu,char * buf)1039 static int vangogh_get_power_profile_mode(struct smu_context *smu,
1040 char *buf)
1041 {
1042 static const char *profile_name[] = {
1043 "BOOTUP_DEFAULT",
1044 "3D_FULL_SCREEN",
1045 "POWER_SAVING",
1046 "VIDEO",
1047 "VR",
1048 "COMPUTE",
1049 "CUSTOM"};
1050 uint32_t i, size = 0;
1051 int16_t workload_type = 0;
1052
1053 if (!buf)
1054 return -EINVAL;
1055
1056 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1057 /*
1058 * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
1059 * Not all profile modes are supported on vangogh.
1060 */
1061 workload_type = smu_cmn_to_asic_specific_index(smu,
1062 CMN2ASIC_MAPPING_WORKLOAD,
1063 i);
1064
1065 if (workload_type < 0)
1066 continue;
1067
1068 size += sysfs_emit_at(buf, size, "%2d %14s%s\n",
1069 i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1070 }
1071
1072 return size;
1073 }
1074
vangogh_set_power_profile_mode(struct smu_context * smu,long * input,uint32_t size)1075 static int vangogh_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
1076 {
1077 int workload_type, ret;
1078 uint32_t profile_mode = input[size];
1079
1080 if (profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1081 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", profile_mode);
1082 return -EINVAL;
1083 }
1084
1085 if (profile_mode == PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT ||
1086 profile_mode == PP_SMC_POWER_PROFILE_POWERSAVING)
1087 return 0;
1088
1089 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1090 workload_type = smu_cmn_to_asic_specific_index(smu,
1091 CMN2ASIC_MAPPING_WORKLOAD,
1092 profile_mode);
1093 if (workload_type < 0) {
1094 dev_dbg(smu->adev->dev, "Unsupported power profile mode %d on VANGOGH\n",
1095 profile_mode);
1096 return -EINVAL;
1097 }
1098
1099 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ActiveProcessNotify,
1100 1 << workload_type,
1101 NULL);
1102 if (ret) {
1103 dev_err_once(smu->adev->dev, "Fail to set workload type %d\n",
1104 workload_type);
1105 return ret;
1106 }
1107
1108 smu->power_profile_mode = profile_mode;
1109
1110 return 0;
1111 }
1112
vangogh_set_soft_freq_limited_range(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t min,uint32_t max)1113 static int vangogh_set_soft_freq_limited_range(struct smu_context *smu,
1114 enum smu_clk_type clk_type,
1115 uint32_t min,
1116 uint32_t max)
1117 {
1118 int ret = 0;
1119
1120 if (!vangogh_clk_dpm_is_enabled(smu, clk_type))
1121 return 0;
1122
1123 switch (clk_type) {
1124 case SMU_GFXCLK:
1125 case SMU_SCLK:
1126 ret = smu_cmn_send_smc_msg_with_param(smu,
1127 SMU_MSG_SetHardMinGfxClk,
1128 min, NULL);
1129 if (ret)
1130 return ret;
1131
1132 ret = smu_cmn_send_smc_msg_with_param(smu,
1133 SMU_MSG_SetSoftMaxGfxClk,
1134 max, NULL);
1135 if (ret)
1136 return ret;
1137 break;
1138 case SMU_FCLK:
1139 ret = smu_cmn_send_smc_msg_with_param(smu,
1140 SMU_MSG_SetHardMinFclkByFreq,
1141 min, NULL);
1142 if (ret)
1143 return ret;
1144
1145 ret = smu_cmn_send_smc_msg_with_param(smu,
1146 SMU_MSG_SetSoftMaxFclkByFreq,
1147 max, NULL);
1148 if (ret)
1149 return ret;
1150 break;
1151 case SMU_SOCCLK:
1152 ret = smu_cmn_send_smc_msg_with_param(smu,
1153 SMU_MSG_SetHardMinSocclkByFreq,
1154 min, NULL);
1155 if (ret)
1156 return ret;
1157
1158 ret = smu_cmn_send_smc_msg_with_param(smu,
1159 SMU_MSG_SetSoftMaxSocclkByFreq,
1160 max, NULL);
1161 if (ret)
1162 return ret;
1163 break;
1164 case SMU_VCLK:
1165 ret = smu_cmn_send_smc_msg_with_param(smu,
1166 SMU_MSG_SetHardMinVcn,
1167 min << 16, NULL);
1168 if (ret)
1169 return ret;
1170 ret = smu_cmn_send_smc_msg_with_param(smu,
1171 SMU_MSG_SetSoftMaxVcn,
1172 max << 16, NULL);
1173 if (ret)
1174 return ret;
1175 break;
1176 case SMU_DCLK:
1177 ret = smu_cmn_send_smc_msg_with_param(smu,
1178 SMU_MSG_SetHardMinVcn,
1179 min, NULL);
1180 if (ret)
1181 return ret;
1182 ret = smu_cmn_send_smc_msg_with_param(smu,
1183 SMU_MSG_SetSoftMaxVcn,
1184 max, NULL);
1185 if (ret)
1186 return ret;
1187 break;
1188 default:
1189 return -EINVAL;
1190 }
1191
1192 return ret;
1193 }
1194
vangogh_force_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t mask)1195 static int vangogh_force_clk_levels(struct smu_context *smu,
1196 enum smu_clk_type clk_type, uint32_t mask)
1197 {
1198 uint32_t soft_min_level = 0, soft_max_level = 0;
1199 uint32_t min_freq = 0, max_freq = 0;
1200 int ret = 0 ;
1201
1202 soft_min_level = mask ? (ffs(mask) - 1) : 0;
1203 soft_max_level = mask ? (fls(mask) - 1) : 0;
1204
1205 switch (clk_type) {
1206 case SMU_SOCCLK:
1207 ret = vangogh_get_dpm_clk_limited(smu, clk_type,
1208 soft_min_level, &min_freq);
1209 if (ret)
1210 return ret;
1211 ret = vangogh_get_dpm_clk_limited(smu, clk_type,
1212 soft_max_level, &max_freq);
1213 if (ret)
1214 return ret;
1215 ret = smu_cmn_send_smc_msg_with_param(smu,
1216 SMU_MSG_SetSoftMaxSocclkByFreq,
1217 max_freq, NULL);
1218 if (ret)
1219 return ret;
1220 ret = smu_cmn_send_smc_msg_with_param(smu,
1221 SMU_MSG_SetHardMinSocclkByFreq,
1222 min_freq, NULL);
1223 if (ret)
1224 return ret;
1225 break;
1226 case SMU_FCLK:
1227 ret = vangogh_get_dpm_clk_limited(smu,
1228 clk_type, soft_min_level, &min_freq);
1229 if (ret)
1230 return ret;
1231 ret = vangogh_get_dpm_clk_limited(smu,
1232 clk_type, soft_max_level, &max_freq);
1233 if (ret)
1234 return ret;
1235 ret = smu_cmn_send_smc_msg_with_param(smu,
1236 SMU_MSG_SetSoftMaxFclkByFreq,
1237 max_freq, NULL);
1238 if (ret)
1239 return ret;
1240 ret = smu_cmn_send_smc_msg_with_param(smu,
1241 SMU_MSG_SetHardMinFclkByFreq,
1242 min_freq, NULL);
1243 if (ret)
1244 return ret;
1245 break;
1246 case SMU_VCLK:
1247 ret = vangogh_get_dpm_clk_limited(smu,
1248 clk_type, soft_min_level, &min_freq);
1249 if (ret)
1250 return ret;
1251
1252 ret = vangogh_get_dpm_clk_limited(smu,
1253 clk_type, soft_max_level, &max_freq);
1254 if (ret)
1255 return ret;
1256
1257
1258 ret = smu_cmn_send_smc_msg_with_param(smu,
1259 SMU_MSG_SetHardMinVcn,
1260 min_freq << 16, NULL);
1261 if (ret)
1262 return ret;
1263
1264 ret = smu_cmn_send_smc_msg_with_param(smu,
1265 SMU_MSG_SetSoftMaxVcn,
1266 max_freq << 16, NULL);
1267 if (ret)
1268 return ret;
1269
1270 break;
1271 case SMU_DCLK:
1272 ret = vangogh_get_dpm_clk_limited(smu,
1273 clk_type, soft_min_level, &min_freq);
1274 if (ret)
1275 return ret;
1276
1277 ret = vangogh_get_dpm_clk_limited(smu,
1278 clk_type, soft_max_level, &max_freq);
1279 if (ret)
1280 return ret;
1281
1282 ret = smu_cmn_send_smc_msg_with_param(smu,
1283 SMU_MSG_SetHardMinVcn,
1284 min_freq, NULL);
1285 if (ret)
1286 return ret;
1287
1288 ret = smu_cmn_send_smc_msg_with_param(smu,
1289 SMU_MSG_SetSoftMaxVcn,
1290 max_freq, NULL);
1291 if (ret)
1292 return ret;
1293
1294 break;
1295 default:
1296 break;
1297 }
1298
1299 return ret;
1300 }
1301
vangogh_force_dpm_limit_value(struct smu_context * smu,bool highest)1302 static int vangogh_force_dpm_limit_value(struct smu_context *smu, bool highest)
1303 {
1304 int ret = 0, i = 0;
1305 uint32_t min_freq, max_freq, force_freq;
1306 enum smu_clk_type clk_type;
1307
1308 enum smu_clk_type clks[] = {
1309 SMU_SOCCLK,
1310 SMU_VCLK,
1311 SMU_DCLK,
1312 SMU_FCLK,
1313 };
1314
1315 for (i = 0; i < ARRAY_SIZE(clks); i++) {
1316 clk_type = clks[i];
1317 ret = vangogh_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq);
1318 if (ret)
1319 return ret;
1320
1321 force_freq = highest ? max_freq : min_freq;
1322 ret = vangogh_set_soft_freq_limited_range(smu, clk_type, force_freq, force_freq);
1323 if (ret)
1324 return ret;
1325 }
1326
1327 return ret;
1328 }
1329
vangogh_unforce_dpm_levels(struct smu_context * smu)1330 static int vangogh_unforce_dpm_levels(struct smu_context *smu)
1331 {
1332 int ret = 0, i = 0;
1333 uint32_t min_freq, max_freq;
1334 enum smu_clk_type clk_type;
1335
1336 struct clk_feature_map {
1337 enum smu_clk_type clk_type;
1338 uint32_t feature;
1339 } clk_feature_map[] = {
1340 {SMU_FCLK, SMU_FEATURE_DPM_FCLK_BIT},
1341 {SMU_SOCCLK, SMU_FEATURE_DPM_SOCCLK_BIT},
1342 {SMU_VCLK, SMU_FEATURE_VCN_DPM_BIT},
1343 {SMU_DCLK, SMU_FEATURE_VCN_DPM_BIT},
1344 };
1345
1346 for (i = 0; i < ARRAY_SIZE(clk_feature_map); i++) {
1347
1348 if (!smu_cmn_feature_is_enabled(smu, clk_feature_map[i].feature))
1349 continue;
1350
1351 clk_type = clk_feature_map[i].clk_type;
1352
1353 ret = vangogh_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq);
1354
1355 if (ret)
1356 return ret;
1357
1358 ret = vangogh_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
1359
1360 if (ret)
1361 return ret;
1362 }
1363
1364 return ret;
1365 }
1366
vangogh_set_peak_clock_by_device(struct smu_context * smu)1367 static int vangogh_set_peak_clock_by_device(struct smu_context *smu)
1368 {
1369 int ret = 0;
1370 uint32_t socclk_freq = 0, fclk_freq = 0;
1371 uint32_t vclk_freq = 0, dclk_freq = 0;
1372
1373 ret = vangogh_get_dpm_ultimate_freq(smu, SMU_FCLK, NULL, &fclk_freq);
1374 if (ret)
1375 return ret;
1376
1377 ret = vangogh_set_soft_freq_limited_range(smu, SMU_FCLK, fclk_freq, fclk_freq);
1378 if (ret)
1379 return ret;
1380
1381 ret = vangogh_get_dpm_ultimate_freq(smu, SMU_SOCCLK, NULL, &socclk_freq);
1382 if (ret)
1383 return ret;
1384
1385 ret = vangogh_set_soft_freq_limited_range(smu, SMU_SOCCLK, socclk_freq, socclk_freq);
1386 if (ret)
1387 return ret;
1388
1389 ret = vangogh_get_dpm_ultimate_freq(smu, SMU_VCLK, NULL, &vclk_freq);
1390 if (ret)
1391 return ret;
1392
1393 ret = vangogh_set_soft_freq_limited_range(smu, SMU_VCLK, vclk_freq, vclk_freq);
1394 if (ret)
1395 return ret;
1396
1397 ret = vangogh_get_dpm_ultimate_freq(smu, SMU_DCLK, NULL, &dclk_freq);
1398 if (ret)
1399 return ret;
1400
1401 ret = vangogh_set_soft_freq_limited_range(smu, SMU_DCLK, dclk_freq, dclk_freq);
1402 if (ret)
1403 return ret;
1404
1405 return ret;
1406 }
1407
vangogh_set_performance_level(struct smu_context * smu,enum amd_dpm_forced_level level)1408 static int vangogh_set_performance_level(struct smu_context *smu,
1409 enum amd_dpm_forced_level level)
1410 {
1411 int ret = 0;
1412 uint32_t soc_mask, mclk_mask, fclk_mask;
1413 uint32_t vclk_mask = 0, dclk_mask = 0;
1414
1415 smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq;
1416 smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq;
1417
1418 switch (level) {
1419 case AMD_DPM_FORCED_LEVEL_HIGH:
1420 smu->gfx_actual_hard_min_freq = smu->gfx_default_soft_max_freq;
1421 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
1422
1423
1424 ret = vangogh_force_dpm_limit_value(smu, true);
1425 if (ret)
1426 return ret;
1427 break;
1428 case AMD_DPM_FORCED_LEVEL_LOW:
1429 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
1430 smu->gfx_actual_soft_max_freq = smu->gfx_default_hard_min_freq;
1431
1432 ret = vangogh_force_dpm_limit_value(smu, false);
1433 if (ret)
1434 return ret;
1435 break;
1436 case AMD_DPM_FORCED_LEVEL_AUTO:
1437 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
1438 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
1439
1440 ret = vangogh_unforce_dpm_levels(smu);
1441 if (ret)
1442 return ret;
1443 break;
1444 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1445 smu->gfx_actual_hard_min_freq = VANGOGH_UMD_PSTATE_STANDARD_GFXCLK;
1446 smu->gfx_actual_soft_max_freq = VANGOGH_UMD_PSTATE_STANDARD_GFXCLK;
1447
1448 ret = vangogh_get_profiling_clk_mask(smu, level,
1449 &vclk_mask,
1450 &dclk_mask,
1451 &mclk_mask,
1452 &fclk_mask,
1453 &soc_mask);
1454 if (ret)
1455 return ret;
1456
1457 vangogh_force_clk_levels(smu, SMU_FCLK, 1 << fclk_mask);
1458 vangogh_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask);
1459 vangogh_force_clk_levels(smu, SMU_VCLK, 1 << vclk_mask);
1460 vangogh_force_clk_levels(smu, SMU_DCLK, 1 << dclk_mask);
1461 break;
1462 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1463 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
1464 smu->gfx_actual_soft_max_freq = smu->gfx_default_hard_min_freq;
1465 break;
1466 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1467 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
1468 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
1469
1470 ret = vangogh_get_profiling_clk_mask(smu, level,
1471 NULL,
1472 NULL,
1473 &mclk_mask,
1474 &fclk_mask,
1475 NULL);
1476 if (ret)
1477 return ret;
1478
1479 vangogh_force_clk_levels(smu, SMU_FCLK, 1 << fclk_mask);
1480 break;
1481 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1482 smu->gfx_actual_hard_min_freq = VANGOGH_UMD_PSTATE_PEAK_GFXCLK;
1483 smu->gfx_actual_soft_max_freq = VANGOGH_UMD_PSTATE_PEAK_GFXCLK;
1484
1485 ret = vangogh_set_peak_clock_by_device(smu);
1486 if (ret)
1487 return ret;
1488 break;
1489 case AMD_DPM_FORCED_LEVEL_MANUAL:
1490 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1491 default:
1492 return 0;
1493 }
1494
1495 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk,
1496 smu->gfx_actual_hard_min_freq, NULL);
1497 if (ret)
1498 return ret;
1499
1500 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
1501 smu->gfx_actual_soft_max_freq, NULL);
1502 if (ret)
1503 return ret;
1504
1505 return ret;
1506 }
1507
vangogh_read_sensor(struct smu_context * smu,enum amd_pp_sensors sensor,void * data,uint32_t * size)1508 static int vangogh_read_sensor(struct smu_context *smu,
1509 enum amd_pp_sensors sensor,
1510 void *data, uint32_t *size)
1511 {
1512 int ret = 0;
1513
1514 if (!data || !size)
1515 return -EINVAL;
1516
1517 mutex_lock(&smu->sensor_lock);
1518 switch (sensor) {
1519 case AMDGPU_PP_SENSOR_GPU_LOAD:
1520 ret = vangogh_common_get_smu_metrics_data(smu,
1521 METRICS_AVERAGE_GFXACTIVITY,
1522 (uint32_t *)data);
1523 *size = 4;
1524 break;
1525 case AMDGPU_PP_SENSOR_GPU_POWER:
1526 ret = vangogh_common_get_smu_metrics_data(smu,
1527 METRICS_AVERAGE_SOCKETPOWER,
1528 (uint32_t *)data);
1529 *size = 4;
1530 break;
1531 case AMDGPU_PP_SENSOR_EDGE_TEMP:
1532 ret = vangogh_common_get_smu_metrics_data(smu,
1533 METRICS_TEMPERATURE_EDGE,
1534 (uint32_t *)data);
1535 *size = 4;
1536 break;
1537 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1538 ret = vangogh_common_get_smu_metrics_data(smu,
1539 METRICS_TEMPERATURE_HOTSPOT,
1540 (uint32_t *)data);
1541 *size = 4;
1542 break;
1543 case AMDGPU_PP_SENSOR_GFX_MCLK:
1544 ret = vangogh_common_get_smu_metrics_data(smu,
1545 METRICS_CURR_UCLK,
1546 (uint32_t *)data);
1547 *(uint32_t *)data *= 100;
1548 *size = 4;
1549 break;
1550 case AMDGPU_PP_SENSOR_GFX_SCLK:
1551 ret = vangogh_common_get_smu_metrics_data(smu,
1552 METRICS_CURR_GFXCLK,
1553 (uint32_t *)data);
1554 *(uint32_t *)data *= 100;
1555 *size = 4;
1556 break;
1557 case AMDGPU_PP_SENSOR_VDDGFX:
1558 ret = vangogh_common_get_smu_metrics_data(smu,
1559 METRICS_VOLTAGE_VDDGFX,
1560 (uint32_t *)data);
1561 *size = 4;
1562 break;
1563 case AMDGPU_PP_SENSOR_VDDNB:
1564 ret = vangogh_common_get_smu_metrics_data(smu,
1565 METRICS_VOLTAGE_VDDSOC,
1566 (uint32_t *)data);
1567 *size = 4;
1568 break;
1569 case AMDGPU_PP_SENSOR_CPU_CLK:
1570 ret = vangogh_common_get_smu_metrics_data(smu,
1571 METRICS_AVERAGE_CPUCLK,
1572 (uint32_t *)data);
1573 *size = smu->cpu_core_num * sizeof(uint16_t);
1574 break;
1575 default:
1576 ret = -EOPNOTSUPP;
1577 break;
1578 }
1579 mutex_unlock(&smu->sensor_lock);
1580
1581 return ret;
1582 }
1583
vangogh_set_watermarks_table(struct smu_context * smu,struct pp_smu_wm_range_sets * clock_ranges)1584 static int vangogh_set_watermarks_table(struct smu_context *smu,
1585 struct pp_smu_wm_range_sets *clock_ranges)
1586 {
1587 int i;
1588 int ret = 0;
1589 Watermarks_t *table = smu->smu_table.watermarks_table;
1590
1591 if (!table || !clock_ranges)
1592 return -EINVAL;
1593
1594 if (clock_ranges) {
1595 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
1596 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
1597 return -EINVAL;
1598
1599 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
1600 table->WatermarkRow[WM_DCFCLK][i].MinClock =
1601 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
1602 table->WatermarkRow[WM_DCFCLK][i].MaxClock =
1603 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
1604 table->WatermarkRow[WM_DCFCLK][i].MinMclk =
1605 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
1606 table->WatermarkRow[WM_DCFCLK][i].MaxMclk =
1607 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;
1608
1609 table->WatermarkRow[WM_DCFCLK][i].WmSetting =
1610 clock_ranges->reader_wm_sets[i].wm_inst;
1611 }
1612
1613 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
1614 table->WatermarkRow[WM_SOCCLK][i].MinClock =
1615 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
1616 table->WatermarkRow[WM_SOCCLK][i].MaxClock =
1617 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
1618 table->WatermarkRow[WM_SOCCLK][i].MinMclk =
1619 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
1620 table->WatermarkRow[WM_SOCCLK][i].MaxMclk =
1621 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;
1622
1623 table->WatermarkRow[WM_SOCCLK][i].WmSetting =
1624 clock_ranges->writer_wm_sets[i].wm_inst;
1625 }
1626
1627 smu->watermarks_bitmap |= WATERMARKS_EXIST;
1628 }
1629
1630 /* pass data to smu controller */
1631 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1632 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
1633 ret = smu_cmn_write_watermarks_table(smu);
1634 if (ret) {
1635 dev_err(smu->adev->dev, "Failed to update WMTABLE!");
1636 return ret;
1637 }
1638 smu->watermarks_bitmap |= WATERMARKS_LOADED;
1639 }
1640
1641 return 0;
1642 }
1643
vangogh_get_legacy_gpu_metrics(struct smu_context * smu,void ** table)1644 static ssize_t vangogh_get_legacy_gpu_metrics(struct smu_context *smu,
1645 void **table)
1646 {
1647 struct smu_table_context *smu_table = &smu->smu_table;
1648 struct gpu_metrics_v2_2 *gpu_metrics =
1649 (struct gpu_metrics_v2_2 *)smu_table->gpu_metrics_table;
1650 SmuMetrics_legacy_t metrics;
1651 int ret = 0;
1652
1653 ret = smu_cmn_get_metrics_table(smu, &metrics, true);
1654 if (ret)
1655 return ret;
1656
1657 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 2);
1658
1659 gpu_metrics->temperature_gfx = metrics.GfxTemperature;
1660 gpu_metrics->temperature_soc = metrics.SocTemperature;
1661 memcpy(&gpu_metrics->temperature_core[0],
1662 &metrics.CoreTemperature[0],
1663 sizeof(uint16_t) * 4);
1664 gpu_metrics->temperature_l3[0] = metrics.L3Temperature[0];
1665
1666 gpu_metrics->average_gfx_activity = metrics.GfxActivity;
1667 gpu_metrics->average_mm_activity = metrics.UvdActivity;
1668
1669 gpu_metrics->average_socket_power = metrics.CurrentSocketPower;
1670 gpu_metrics->average_cpu_power = metrics.Power[0];
1671 gpu_metrics->average_soc_power = metrics.Power[1];
1672 gpu_metrics->average_gfx_power = metrics.Power[2];
1673 memcpy(&gpu_metrics->average_core_power[0],
1674 &metrics.CorePower[0],
1675 sizeof(uint16_t) * 4);
1676
1677 gpu_metrics->average_gfxclk_frequency = metrics.GfxclkFrequency;
1678 gpu_metrics->average_socclk_frequency = metrics.SocclkFrequency;
1679 gpu_metrics->average_uclk_frequency = metrics.MemclkFrequency;
1680 gpu_metrics->average_fclk_frequency = metrics.MemclkFrequency;
1681 gpu_metrics->average_vclk_frequency = metrics.VclkFrequency;
1682 gpu_metrics->average_dclk_frequency = metrics.DclkFrequency;
1683
1684 memcpy(&gpu_metrics->current_coreclk[0],
1685 &metrics.CoreFrequency[0],
1686 sizeof(uint16_t) * 4);
1687 gpu_metrics->current_l3clk[0] = metrics.L3Frequency[0];
1688
1689 gpu_metrics->throttle_status = metrics.ThrottlerStatus;
1690 gpu_metrics->indep_throttle_status =
1691 smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
1692 vangogh_throttler_map);
1693
1694 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
1695
1696 *table = (void *)gpu_metrics;
1697
1698 return sizeof(struct gpu_metrics_v2_2);
1699 }
1700
vangogh_get_gpu_metrics(struct smu_context * smu,void ** table)1701 static ssize_t vangogh_get_gpu_metrics(struct smu_context *smu,
1702 void **table)
1703 {
1704 struct smu_table_context *smu_table = &smu->smu_table;
1705 struct gpu_metrics_v2_2 *gpu_metrics =
1706 (struct gpu_metrics_v2_2 *)smu_table->gpu_metrics_table;
1707 SmuMetrics_t metrics;
1708 int ret = 0;
1709
1710 ret = smu_cmn_get_metrics_table(smu, &metrics, true);
1711 if (ret)
1712 return ret;
1713
1714 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 2);
1715
1716 gpu_metrics->temperature_gfx = metrics.Current.GfxTemperature;
1717 gpu_metrics->temperature_soc = metrics.Current.SocTemperature;
1718 memcpy(&gpu_metrics->temperature_core[0],
1719 &metrics.Current.CoreTemperature[0],
1720 sizeof(uint16_t) * 4);
1721 gpu_metrics->temperature_l3[0] = metrics.Current.L3Temperature[0];
1722
1723 gpu_metrics->average_gfx_activity = metrics.Current.GfxActivity;
1724 gpu_metrics->average_mm_activity = metrics.Current.UvdActivity;
1725
1726 gpu_metrics->average_socket_power = metrics.Current.CurrentSocketPower;
1727 gpu_metrics->average_cpu_power = metrics.Current.Power[0];
1728 gpu_metrics->average_soc_power = metrics.Current.Power[1];
1729 gpu_metrics->average_gfx_power = metrics.Current.Power[2];
1730 memcpy(&gpu_metrics->average_core_power[0],
1731 &metrics.Average.CorePower[0],
1732 sizeof(uint16_t) * 4);
1733
1734 gpu_metrics->average_gfxclk_frequency = metrics.Average.GfxclkFrequency;
1735 gpu_metrics->average_socclk_frequency = metrics.Average.SocclkFrequency;
1736 gpu_metrics->average_uclk_frequency = metrics.Average.MemclkFrequency;
1737 gpu_metrics->average_fclk_frequency = metrics.Average.MemclkFrequency;
1738 gpu_metrics->average_vclk_frequency = metrics.Average.VclkFrequency;
1739 gpu_metrics->average_dclk_frequency = metrics.Average.DclkFrequency;
1740
1741 gpu_metrics->current_gfxclk = metrics.Current.GfxclkFrequency;
1742 gpu_metrics->current_socclk = metrics.Current.SocclkFrequency;
1743 gpu_metrics->current_uclk = metrics.Current.MemclkFrequency;
1744 gpu_metrics->current_fclk = metrics.Current.MemclkFrequency;
1745 gpu_metrics->current_vclk = metrics.Current.VclkFrequency;
1746 gpu_metrics->current_dclk = metrics.Current.DclkFrequency;
1747
1748 memcpy(&gpu_metrics->current_coreclk[0],
1749 &metrics.Current.CoreFrequency[0],
1750 sizeof(uint16_t) * 4);
1751 gpu_metrics->current_l3clk[0] = metrics.Current.L3Frequency[0];
1752
1753 gpu_metrics->throttle_status = metrics.Current.ThrottlerStatus;
1754 gpu_metrics->indep_throttle_status =
1755 smu_cmn_get_indep_throttler_status(metrics.Current.ThrottlerStatus,
1756 vangogh_throttler_map);
1757
1758 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
1759
1760 *table = (void *)gpu_metrics;
1761
1762 return sizeof(struct gpu_metrics_v2_2);
1763 }
1764
vangogh_common_get_gpu_metrics(struct smu_context * smu,void ** table)1765 static ssize_t vangogh_common_get_gpu_metrics(struct smu_context *smu,
1766 void **table)
1767 {
1768 struct amdgpu_device *adev = smu->adev;
1769 uint32_t if_version;
1770 int ret = 0;
1771
1772 ret = smu_cmn_get_smc_version(smu, &if_version, NULL);
1773 if (ret) {
1774 dev_err(adev->dev, "Failed to get smu if version!\n");
1775 return ret;
1776 }
1777
1778 if (if_version < 0x3)
1779 ret = vangogh_get_legacy_gpu_metrics(smu, table);
1780 else
1781 ret = vangogh_get_gpu_metrics(smu, table);
1782
1783 return ret;
1784 }
1785
vangogh_od_edit_dpm_table(struct smu_context * smu,enum PP_OD_DPM_TABLE_COMMAND type,long input[],uint32_t size)1786 static int vangogh_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type,
1787 long input[], uint32_t size)
1788 {
1789 int ret = 0;
1790 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1791
1792 if (!(smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL)) {
1793 dev_warn(smu->adev->dev,
1794 "pp_od_clk_voltage is not accessible if power_dpm_force_performance_level is not in manual mode!\n");
1795 return -EINVAL;
1796 }
1797
1798 switch (type) {
1799 case PP_OD_EDIT_CCLK_VDDC_TABLE:
1800 if (size != 3) {
1801 dev_err(smu->adev->dev, "Input parameter number not correct (should be 4 for processor)\n");
1802 return -EINVAL;
1803 }
1804 if (input[0] >= smu->cpu_core_num) {
1805 dev_err(smu->adev->dev, "core index is overflow, should be less than %d\n",
1806 smu->cpu_core_num);
1807 }
1808 smu->cpu_core_id_select = input[0];
1809 if (input[1] == 0) {
1810 if (input[2] < smu->cpu_default_soft_min_freq) {
1811 dev_warn(smu->adev->dev, "Fine grain setting minimum cclk (%ld) MHz is less than the minimum allowed (%d) MHz\n",
1812 input[2], smu->cpu_default_soft_min_freq);
1813 return -EINVAL;
1814 }
1815 smu->cpu_actual_soft_min_freq = input[2];
1816 } else if (input[1] == 1) {
1817 if (input[2] > smu->cpu_default_soft_max_freq) {
1818 dev_warn(smu->adev->dev, "Fine grain setting maximum cclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n",
1819 input[2], smu->cpu_default_soft_max_freq);
1820 return -EINVAL;
1821 }
1822 smu->cpu_actual_soft_max_freq = input[2];
1823 } else {
1824 return -EINVAL;
1825 }
1826 break;
1827 case PP_OD_EDIT_SCLK_VDDC_TABLE:
1828 if (size != 2) {
1829 dev_err(smu->adev->dev, "Input parameter number not correct\n");
1830 return -EINVAL;
1831 }
1832
1833 if (input[0] == 0) {
1834 if (input[1] < smu->gfx_default_hard_min_freq) {
1835 dev_warn(smu->adev->dev,
1836 "Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n",
1837 input[1], smu->gfx_default_hard_min_freq);
1838 return -EINVAL;
1839 }
1840 smu->gfx_actual_hard_min_freq = input[1];
1841 } else if (input[0] == 1) {
1842 if (input[1] > smu->gfx_default_soft_max_freq) {
1843 dev_warn(smu->adev->dev,
1844 "Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n",
1845 input[1], smu->gfx_default_soft_max_freq);
1846 return -EINVAL;
1847 }
1848 smu->gfx_actual_soft_max_freq = input[1];
1849 } else {
1850 return -EINVAL;
1851 }
1852 break;
1853 case PP_OD_RESTORE_DEFAULT_TABLE:
1854 if (size != 0) {
1855 dev_err(smu->adev->dev, "Input parameter number not correct\n");
1856 return -EINVAL;
1857 } else {
1858 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
1859 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
1860 smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq;
1861 smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq;
1862 }
1863 break;
1864 case PP_OD_COMMIT_DPM_TABLE:
1865 if (size != 0) {
1866 dev_err(smu->adev->dev, "Input parameter number not correct\n");
1867 return -EINVAL;
1868 } else {
1869 if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) {
1870 dev_err(smu->adev->dev,
1871 "The setting minimum sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n",
1872 smu->gfx_actual_hard_min_freq,
1873 smu->gfx_actual_soft_max_freq);
1874 return -EINVAL;
1875 }
1876
1877 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk,
1878 smu->gfx_actual_hard_min_freq, NULL);
1879 if (ret) {
1880 dev_err(smu->adev->dev, "Set hard min sclk failed!");
1881 return ret;
1882 }
1883
1884 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
1885 smu->gfx_actual_soft_max_freq, NULL);
1886 if (ret) {
1887 dev_err(smu->adev->dev, "Set soft max sclk failed!");
1888 return ret;
1889 }
1890
1891 if (smu->adev->pm.fw_version < 0x43f1b00) {
1892 dev_warn(smu->adev->dev, "CPUSoftMax/CPUSoftMin are not supported, please update SBIOS!\n");
1893 break;
1894 }
1895
1896 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinCclk,
1897 ((smu->cpu_core_id_select << 20)
1898 | smu->cpu_actual_soft_min_freq),
1899 NULL);
1900 if (ret) {
1901 dev_err(smu->adev->dev, "Set hard min cclk failed!");
1902 return ret;
1903 }
1904
1905 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxCclk,
1906 ((smu->cpu_core_id_select << 20)
1907 | smu->cpu_actual_soft_max_freq),
1908 NULL);
1909 if (ret) {
1910 dev_err(smu->adev->dev, "Set soft max cclk failed!");
1911 return ret;
1912 }
1913 }
1914 break;
1915 default:
1916 return -ENOSYS;
1917 }
1918
1919 return ret;
1920 }
1921
vangogh_set_default_dpm_tables(struct smu_context * smu)1922 static int vangogh_set_default_dpm_tables(struct smu_context *smu)
1923 {
1924 struct smu_table_context *smu_table = &smu->smu_table;
1925
1926 return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0, smu_table->clocks_table, false);
1927 }
1928
vangogh_set_fine_grain_gfx_freq_parameters(struct smu_context * smu)1929 static int vangogh_set_fine_grain_gfx_freq_parameters(struct smu_context *smu)
1930 {
1931 DpmClocks_t *clk_table = smu->smu_table.clocks_table;
1932
1933 smu->gfx_default_hard_min_freq = clk_table->MinGfxClk;
1934 smu->gfx_default_soft_max_freq = clk_table->MaxGfxClk;
1935 smu->gfx_actual_hard_min_freq = 0;
1936 smu->gfx_actual_soft_max_freq = 0;
1937
1938 smu->cpu_default_soft_min_freq = 1400;
1939 smu->cpu_default_soft_max_freq = 3500;
1940 smu->cpu_actual_soft_min_freq = 0;
1941 smu->cpu_actual_soft_max_freq = 0;
1942
1943 return 0;
1944 }
1945
vangogh_get_dpm_clock_table(struct smu_context * smu,struct dpm_clocks * clock_table)1946 static int vangogh_get_dpm_clock_table(struct smu_context *smu, struct dpm_clocks *clock_table)
1947 {
1948 DpmClocks_t *table = smu->smu_table.clocks_table;
1949 int i;
1950
1951 if (!clock_table || !table)
1952 return -EINVAL;
1953
1954 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++) {
1955 clock_table->SocClocks[i].Freq = table->SocClocks[i];
1956 clock_table->SocClocks[i].Vol = table->SocVoltage[i];
1957 }
1958
1959 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) {
1960 clock_table->FClocks[i].Freq = table->DfPstateTable[i].fclk;
1961 clock_table->FClocks[i].Vol = table->DfPstateTable[i].voltage;
1962 }
1963
1964 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) {
1965 clock_table->MemClocks[i].Freq = table->DfPstateTable[i].memclk;
1966 clock_table->MemClocks[i].Vol = table->DfPstateTable[i].voltage;
1967 }
1968
1969 return 0;
1970 }
1971
1972
vangogh_system_features_control(struct smu_context * smu,bool en)1973 static int vangogh_system_features_control(struct smu_context *smu, bool en)
1974 {
1975 struct amdgpu_device *adev = smu->adev;
1976 struct smu_feature *feature = &smu->smu_feature;
1977 uint32_t feature_mask[2];
1978 int ret = 0;
1979
1980 if (adev->pm.fw_version >= 0x43f1700 && !en)
1981 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_RlcPowerNotify,
1982 RLC_STATUS_OFF, NULL);
1983
1984 bitmap_zero(feature->enabled, feature->feature_num);
1985 bitmap_zero(feature->supported, feature->feature_num);
1986
1987 if (!en)
1988 return ret;
1989
1990 ret = smu_cmn_get_enabled_32_bits_mask(smu, feature_mask, 2);
1991 if (ret)
1992 return ret;
1993
1994 bitmap_copy(feature->enabled, (unsigned long *)&feature_mask,
1995 feature->feature_num);
1996 bitmap_copy(feature->supported, (unsigned long *)&feature_mask,
1997 feature->feature_num);
1998
1999 return 0;
2000 }
2001
vangogh_post_smu_init(struct smu_context * smu)2002 static int vangogh_post_smu_init(struct smu_context *smu)
2003 {
2004 struct amdgpu_device *adev = smu->adev;
2005 uint32_t tmp;
2006 int ret = 0;
2007 uint8_t aon_bits = 0;
2008 /* Two CUs in one WGP */
2009 uint32_t req_active_wgps = adev->gfx.cu_info.number/2;
2010 uint32_t total_cu = adev->gfx.config.max_cu_per_sh *
2011 adev->gfx.config.max_sh_per_se * adev->gfx.config.max_shader_engines;
2012
2013 /* allow message will be sent after enable message on Vangogh*/
2014 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
2015 (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
2016 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_EnableGfxOff, NULL);
2017 if (ret) {
2018 dev_err(adev->dev, "Failed to Enable GfxOff!\n");
2019 return ret;
2020 }
2021 } else {
2022 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
2023 dev_info(adev->dev, "If GFX DPM or power gate disabled, disable GFXOFF\n");
2024 }
2025
2026 /* if all CUs are active, no need to power off any WGPs */
2027 if (total_cu == adev->gfx.cu_info.number)
2028 return 0;
2029
2030 /*
2031 * Calculate the total bits number of always on WGPs for all SA/SEs in
2032 * RLC_PG_ALWAYS_ON_WGP_MASK.
2033 */
2034 tmp = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_ALWAYS_ON_WGP_MASK));
2035 tmp &= RLC_PG_ALWAYS_ON_WGP_MASK__AON_WGP_MASK_MASK;
2036
2037 aon_bits = hweight32(tmp) * adev->gfx.config.max_sh_per_se * adev->gfx.config.max_shader_engines;
2038
2039 /* Do not request any WGPs less than set in the AON_WGP_MASK */
2040 if (aon_bits > req_active_wgps) {
2041 dev_info(adev->dev, "Number of always on WGPs greater than active WGPs: WGP power save not requested.\n");
2042 return 0;
2043 } else {
2044 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_RequestActiveWgp, req_active_wgps, NULL);
2045 }
2046 }
2047
vangogh_mode_reset(struct smu_context * smu,int type)2048 static int vangogh_mode_reset(struct smu_context *smu, int type)
2049 {
2050 int ret = 0, index = 0;
2051
2052 index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG,
2053 SMU_MSG_GfxDeviceDriverReset);
2054 if (index < 0)
2055 return index == -EACCES ? 0 : index;
2056
2057 mutex_lock(&smu->message_lock);
2058
2059 ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index, type);
2060
2061 mutex_unlock(&smu->message_lock);
2062
2063 mdelay(10);
2064
2065 return ret;
2066 }
2067
vangogh_mode2_reset(struct smu_context * smu)2068 static int vangogh_mode2_reset(struct smu_context *smu)
2069 {
2070 return vangogh_mode_reset(smu, SMU_RESET_MODE_2);
2071 }
2072
vangogh_get_power_limit(struct smu_context * smu,uint32_t * current_power_limit,uint32_t * default_power_limit,uint32_t * max_power_limit)2073 static int vangogh_get_power_limit(struct smu_context *smu,
2074 uint32_t *current_power_limit,
2075 uint32_t *default_power_limit,
2076 uint32_t *max_power_limit)
2077 {
2078 struct smu_11_5_power_context *power_context =
2079 smu->smu_power.power_context;
2080 uint32_t ppt_limit;
2081 int ret = 0;
2082
2083 if (smu->adev->pm.fw_version < 0x43f1e00)
2084 return ret;
2085
2086 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetSlowPPTLimit, &ppt_limit);
2087 if (ret) {
2088 dev_err(smu->adev->dev, "Get slow PPT limit failed!\n");
2089 return ret;
2090 }
2091 /* convert from milliwatt to watt */
2092 if (current_power_limit)
2093 *current_power_limit = ppt_limit / 1000;
2094 if (default_power_limit)
2095 *default_power_limit = ppt_limit / 1000;
2096 if (max_power_limit)
2097 *max_power_limit = 29;
2098
2099 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetFastPPTLimit, &ppt_limit);
2100 if (ret) {
2101 dev_err(smu->adev->dev, "Get fast PPT limit failed!\n");
2102 return ret;
2103 }
2104 /* convert from milliwatt to watt */
2105 power_context->current_fast_ppt_limit =
2106 power_context->default_fast_ppt_limit = ppt_limit / 1000;
2107 power_context->max_fast_ppt_limit = 30;
2108
2109 return ret;
2110 }
2111
vangogh_get_ppt_limit(struct smu_context * smu,uint32_t * ppt_limit,enum smu_ppt_limit_type type,enum smu_ppt_limit_level level)2112 static int vangogh_get_ppt_limit(struct smu_context *smu,
2113 uint32_t *ppt_limit,
2114 enum smu_ppt_limit_type type,
2115 enum smu_ppt_limit_level level)
2116 {
2117 struct smu_11_5_power_context *power_context =
2118 smu->smu_power.power_context;
2119
2120 if (!power_context)
2121 return -EOPNOTSUPP;
2122
2123 if (type == SMU_FAST_PPT_LIMIT) {
2124 switch (level) {
2125 case SMU_PPT_LIMIT_MAX:
2126 *ppt_limit = power_context->max_fast_ppt_limit;
2127 break;
2128 case SMU_PPT_LIMIT_CURRENT:
2129 *ppt_limit = power_context->current_fast_ppt_limit;
2130 break;
2131 case SMU_PPT_LIMIT_DEFAULT:
2132 *ppt_limit = power_context->default_fast_ppt_limit;
2133 break;
2134 default:
2135 break;
2136 }
2137 }
2138
2139 return 0;
2140 }
2141
vangogh_set_power_limit(struct smu_context * smu,enum smu_ppt_limit_type limit_type,uint32_t ppt_limit)2142 static int vangogh_set_power_limit(struct smu_context *smu,
2143 enum smu_ppt_limit_type limit_type,
2144 uint32_t ppt_limit)
2145 {
2146 struct smu_11_5_power_context *power_context =
2147 smu->smu_power.power_context;
2148 int ret = 0;
2149
2150 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
2151 dev_err(smu->adev->dev, "Setting new power limit is not supported!\n");
2152 return -EOPNOTSUPP;
2153 }
2154
2155 switch (limit_type) {
2156 case SMU_DEFAULT_PPT_LIMIT:
2157 ret = smu_cmn_send_smc_msg_with_param(smu,
2158 SMU_MSG_SetSlowPPTLimit,
2159 ppt_limit * 1000, /* convert from watt to milliwatt */
2160 NULL);
2161 if (ret)
2162 return ret;
2163
2164 smu->current_power_limit = ppt_limit;
2165 break;
2166 case SMU_FAST_PPT_LIMIT:
2167 ppt_limit &= ~(SMU_FAST_PPT_LIMIT << 24);
2168 if (ppt_limit > power_context->max_fast_ppt_limit) {
2169 dev_err(smu->adev->dev,
2170 "New power limit (%d) is over the max allowed %d\n",
2171 ppt_limit, power_context->max_fast_ppt_limit);
2172 return ret;
2173 }
2174
2175 ret = smu_cmn_send_smc_msg_with_param(smu,
2176 SMU_MSG_SetFastPPTLimit,
2177 ppt_limit * 1000, /* convert from watt to milliwatt */
2178 NULL);
2179 if (ret)
2180 return ret;
2181
2182 power_context->current_fast_ppt_limit = ppt_limit;
2183 break;
2184 default:
2185 return -EINVAL;
2186 }
2187
2188 return ret;
2189 }
2190
2191 static const struct pptable_funcs vangogh_ppt_funcs = {
2192
2193 .check_fw_status = smu_v11_0_check_fw_status,
2194 .check_fw_version = smu_v11_0_check_fw_version,
2195 .init_smc_tables = vangogh_init_smc_tables,
2196 .fini_smc_tables = smu_v11_0_fini_smc_tables,
2197 .init_power = smu_v11_0_init_power,
2198 .fini_power = smu_v11_0_fini_power,
2199 .register_irq_handler = smu_v11_0_register_irq_handler,
2200 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
2201 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
2202 .send_smc_msg = smu_cmn_send_smc_msg,
2203 .dpm_set_vcn_enable = vangogh_dpm_set_vcn_enable,
2204 .dpm_set_jpeg_enable = vangogh_dpm_set_jpeg_enable,
2205 .is_dpm_running = vangogh_is_dpm_running,
2206 .read_sensor = vangogh_read_sensor,
2207 .get_enabled_mask = smu_cmn_get_enabled_32_bits_mask,
2208 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
2209 .set_watermarks_table = vangogh_set_watermarks_table,
2210 .set_driver_table_location = smu_v11_0_set_driver_table_location,
2211 .interrupt_work = smu_v11_0_interrupt_work,
2212 .get_gpu_metrics = vangogh_common_get_gpu_metrics,
2213 .od_edit_dpm_table = vangogh_od_edit_dpm_table,
2214 .print_clk_levels = vangogh_common_print_clk_levels,
2215 .set_default_dpm_table = vangogh_set_default_dpm_tables,
2216 .set_fine_grain_gfx_freq_parameters = vangogh_set_fine_grain_gfx_freq_parameters,
2217 .system_features_control = vangogh_system_features_control,
2218 .feature_is_enabled = smu_cmn_feature_is_enabled,
2219 .set_power_profile_mode = vangogh_set_power_profile_mode,
2220 .get_power_profile_mode = vangogh_get_power_profile_mode,
2221 .get_dpm_clock_table = vangogh_get_dpm_clock_table,
2222 .force_clk_levels = vangogh_force_clk_levels,
2223 .set_performance_level = vangogh_set_performance_level,
2224 .post_init = vangogh_post_smu_init,
2225 .mode2_reset = vangogh_mode2_reset,
2226 .gfx_off_control = smu_v11_0_gfx_off_control,
2227 .get_ppt_limit = vangogh_get_ppt_limit,
2228 .get_power_limit = vangogh_get_power_limit,
2229 .set_power_limit = vangogh_set_power_limit,
2230 .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
2231 };
2232
vangogh_set_ppt_funcs(struct smu_context * smu)2233 void vangogh_set_ppt_funcs(struct smu_context *smu)
2234 {
2235 smu->ppt_funcs = &vangogh_ppt_funcs;
2236 smu->message_map = vangogh_message_map;
2237 smu->feature_map = vangogh_feature_mask_map;
2238 smu->table_map = vangogh_table_map;
2239 smu->workload_map = vangogh_workload_map;
2240 smu->is_apu = true;
2241 }
2242