1 #ifndef DSI_PHY_14NM_XML
2 #define DSI_PHY_14NM_XML
3
4 /* Autogenerated file, DO NOT EDIT manually!
5
6 This file was generated by the rules-ng-ng headergen tool in this git repository:
7 http://github.com/freedreno/envytools/
8 git clone https://github.com/freedreno/envytools.git
9
10 The rules-ng-ng source files this header was generated from are:
11 - /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 981 bytes, from 2021-06-05 21:37:42)
12 - /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
13 - /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2021-02-18 16:45:44)
14 - /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2021-02-18 16:45:44)
15 - /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2021-02-18 16:45:44)
16 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 15291 bytes, from 2021-06-15 22:36:13)
17 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2021-06-05 21:37:42)
18 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2021-05-21 19:18:08)
19 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2021-05-21 19:18:08)
20 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2021-05-21 19:18:08)
21 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2021-05-21 19:18:08)
22 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2021-05-21 19:18:08)
23 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 10953 bytes, from 2021-05-21 19:18:08)
24 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_5nm.xml ( 10900 bytes, from 2021-05-21 19:18:08)
25 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2021-02-18 16:45:44)
26 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2021-02-18 16:45:44)
27 - /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2021-02-18 16:45:44)
28 - /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 41874 bytes, from 2021-02-18 16:45:44)
29 - /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2021-02-18 16:45:44)
30
31 Copyright (C) 2013-2021 by the following authors:
32 - Rob Clark <robdclark@gmail.com> (robclark)
33 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
34
35 Permission is hereby granted, free of charge, to any person obtaining
36 a copy of this software and associated documentation files (the
37 "Software"), to deal in the Software without restriction, including
38 without limitation the rights to use, copy, modify, merge, publish,
39 distribute, sublicense, and/or sell copies of the Software, and to
40 permit persons to whom the Software is furnished to do so, subject to
41 the following conditions:
42
43 The above copyright notice and this permission notice (including the
44 next paragraph) shall be included in all copies or substantial
45 portions of the Software.
46
47 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
48 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
49 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
50 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
51 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
52 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
53 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
54 */
55
56
57 #define REG_DSI_14nm_PHY_CMN_REVISION_ID0 0x00000000
58
59 #define REG_DSI_14nm_PHY_CMN_REVISION_ID1 0x00000004
60
61 #define REG_DSI_14nm_PHY_CMN_REVISION_ID2 0x00000008
62
63 #define REG_DSI_14nm_PHY_CMN_REVISION_ID3 0x0000000c
64
65 #define REG_DSI_14nm_PHY_CMN_CLK_CFG0 0x00000010
66 #define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__MASK 0x000000f0
67 #define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__SHIFT 4
DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0(uint32_t val)68 static inline uint32_t DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0(uint32_t val)
69 {
70 return ((val) << DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__SHIFT) & DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__MASK;
71 }
72 #define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__MASK 0x000000f0
73 #define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__SHIFT 4
DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4(uint32_t val)74 static inline uint32_t DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4(uint32_t val)
75 {
76 return ((val) << DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__SHIFT) & DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__MASK;
77 }
78
79 #define REG_DSI_14nm_PHY_CMN_CLK_CFG1 0x00000014
80 #define DSI_14nm_PHY_CMN_CLK_CFG1_DSICLK_SEL 0x00000001
81
82 #define REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL 0x00000018
83 #define DSI_14nm_PHY_CMN_GLBL_TEST_CTRL_BITCLK_HS_SEL 0x00000004
84
85 #define REG_DSI_14nm_PHY_CMN_CTRL_0 0x0000001c
86
87 #define REG_DSI_14nm_PHY_CMN_CTRL_1 0x00000020
88
89 #define REG_DSI_14nm_PHY_CMN_HW_TRIGGER 0x00000024
90
91 #define REG_DSI_14nm_PHY_CMN_SW_CFG0 0x00000028
92
93 #define REG_DSI_14nm_PHY_CMN_SW_CFG1 0x0000002c
94
95 #define REG_DSI_14nm_PHY_CMN_SW_CFG2 0x00000030
96
97 #define REG_DSI_14nm_PHY_CMN_HW_CFG0 0x00000034
98
99 #define REG_DSI_14nm_PHY_CMN_HW_CFG1 0x00000038
100
101 #define REG_DSI_14nm_PHY_CMN_HW_CFG2 0x0000003c
102
103 #define REG_DSI_14nm_PHY_CMN_HW_CFG3 0x00000040
104
105 #define REG_DSI_14nm_PHY_CMN_HW_CFG4 0x00000044
106
107 #define REG_DSI_14nm_PHY_CMN_PLL_CNTRL 0x00000048
108 #define DSI_14nm_PHY_CMN_PLL_CNTRL_PLL_START 0x00000001
109
110 #define REG_DSI_14nm_PHY_CMN_LDO_CNTRL 0x0000004c
111 #define DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__MASK 0x0000003f
112 #define DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__SHIFT 0
DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL(uint32_t val)113 static inline uint32_t DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL(uint32_t val)
114 {
115 return ((val) << DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__SHIFT) & DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__MASK;
116 }
117
REG_DSI_14nm_PHY_LN(uint32_t i0)118 static inline uint32_t REG_DSI_14nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; }
119
REG_DSI_14nm_PHY_LN_CFG0(uint32_t i0)120 static inline uint32_t REG_DSI_14nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; }
121 #define DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__MASK 0x000000c0
122 #define DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__SHIFT 6
DSI_14nm_PHY_LN_CFG0_PREPARE_DLY(uint32_t val)123 static inline uint32_t DSI_14nm_PHY_LN_CFG0_PREPARE_DLY(uint32_t val)
124 {
125 return ((val) << DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__SHIFT) & DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__MASK;
126 }
127
REG_DSI_14nm_PHY_LN_CFG1(uint32_t i0)128 static inline uint32_t REG_DSI_14nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; }
129 #define DSI_14nm_PHY_LN_CFG1_HALFBYTECLK_EN 0x00000001
130
REG_DSI_14nm_PHY_LN_CFG2(uint32_t i0)131 static inline uint32_t REG_DSI_14nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; }
132
REG_DSI_14nm_PHY_LN_CFG3(uint32_t i0)133 static inline uint32_t REG_DSI_14nm_PHY_LN_CFG3(uint32_t i0) { return 0x0000000c + 0x80*i0; }
134
REG_DSI_14nm_PHY_LN_TEST_DATAPATH(uint32_t i0)135 static inline uint32_t REG_DSI_14nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000010 + 0x80*i0; }
136
REG_DSI_14nm_PHY_LN_TEST_STR(uint32_t i0)137 static inline uint32_t REG_DSI_14nm_PHY_LN_TEST_STR(uint32_t i0) { return 0x00000014 + 0x80*i0; }
138
REG_DSI_14nm_PHY_LN_TIMING_CTRL_4(uint32_t i0)139 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_4(uint32_t i0) { return 0x00000018 + 0x80*i0; }
140 #define DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff
141 #define DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__SHIFT 0
DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT(uint32_t val)142 static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT(uint32_t val)
143 {
144 return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__MASK;
145 }
146
REG_DSI_14nm_PHY_LN_TIMING_CTRL_5(uint32_t i0)147 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_5(uint32_t i0) { return 0x0000001c + 0x80*i0; }
148 #define DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff
149 #define DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__SHIFT 0
DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO(uint32_t val)150 static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO(uint32_t val)
151 {
152 return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__MASK;
153 }
154
REG_DSI_14nm_PHY_LN_TIMING_CTRL_6(uint32_t i0)155 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_6(uint32_t i0) { return 0x00000020 + 0x80*i0; }
156 #define DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff
157 #define DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__SHIFT 0
DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE(uint32_t val)158 static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE(uint32_t val)
159 {
160 return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__MASK;
161 }
162
REG_DSI_14nm_PHY_LN_TIMING_CTRL_7(uint32_t i0)163 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_7(uint32_t i0) { return 0x00000024 + 0x80*i0; }
164 #define DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff
165 #define DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__SHIFT 0
DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL(uint32_t val)166 static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL(uint32_t val)
167 {
168 return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__MASK;
169 }
170
REG_DSI_14nm_PHY_LN_TIMING_CTRL_8(uint32_t i0)171 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_8(uint32_t i0) { return 0x00000028 + 0x80*i0; }
172 #define DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff
173 #define DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__SHIFT 0
DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST(uint32_t val)174 static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST(uint32_t val)
175 {
176 return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__MASK;
177 }
178
REG_DSI_14nm_PHY_LN_TIMING_CTRL_9(uint32_t i0)179 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_9(uint32_t i0) { return 0x0000002c + 0x80*i0; }
180 #define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__MASK 0x00000007
181 #define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__SHIFT 0
DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO(uint32_t val)182 static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO(uint32_t val)
183 {
184 return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__MASK;
185 }
186 #define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__MASK 0x00000070
187 #define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__SHIFT 4
DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE(uint32_t val)188 static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE(uint32_t val)
189 {
190 return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__MASK;
191 }
192
REG_DSI_14nm_PHY_LN_TIMING_CTRL_10(uint32_t i0)193 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_10(uint32_t i0) { return 0x00000030 + 0x80*i0; }
194 #define DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__MASK 0x00000007
195 #define DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__SHIFT 0
DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET(uint32_t val)196 static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET(uint32_t val)
197 {
198 return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__MASK;
199 }
200
REG_DSI_14nm_PHY_LN_TIMING_CTRL_11(uint32_t i0)201 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_11(uint32_t i0) { return 0x00000034 + 0x80*i0; }
202 #define DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff
203 #define DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0
DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)204 static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)
205 {
206 return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__MASK;
207 }
208
REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_0(uint32_t i0)209 static inline uint32_t REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_0(uint32_t i0) { return 0x00000038 + 0x80*i0; }
210
REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_1(uint32_t i0)211 static inline uint32_t REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_1(uint32_t i0) { return 0x0000003c + 0x80*i0; }
212
REG_DSI_14nm_PHY_LN_VREG_CNTRL(uint32_t i0)213 static inline uint32_t REG_DSI_14nm_PHY_LN_VREG_CNTRL(uint32_t i0) { return 0x00000064 + 0x80*i0; }
214
215 #define REG_DSI_14nm_PHY_PLL_IE_TRIM 0x00000000
216
217 #define REG_DSI_14nm_PHY_PLL_IP_TRIM 0x00000004
218
219 #define REG_DSI_14nm_PHY_PLL_IPTAT_TRIM 0x00000010
220
221 #define REG_DSI_14nm_PHY_PLL_CLKBUFLR_EN 0x0000001c
222
223 #define REG_DSI_14nm_PHY_PLL_SYSCLK_EN_RESET 0x00000028
224
225 #define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL 0x0000002c
226
227 #define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL2 0x00000030
228
229 #define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL3 0x00000034
230
231 #define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL4 0x00000038
232
233 #define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL5 0x0000003c
234
235 #define REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF1 0x00000040
236
237 #define REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF2 0x00000044
238
239 #define REG_DSI_14nm_PHY_PLL_KVCO_COUNT1 0x00000048
240
241 #define REG_DSI_14nm_PHY_PLL_KVCO_COUNT2 0x0000004c
242
243 #define REG_DSI_14nm_PHY_PLL_VREF_CFG1 0x0000005c
244
245 #define REG_DSI_14nm_PHY_PLL_KVCO_CODE 0x00000058
246
247 #define REG_DSI_14nm_PHY_PLL_VCO_DIV_REF1 0x0000006c
248
249 #define REG_DSI_14nm_PHY_PLL_VCO_DIV_REF2 0x00000070
250
251 #define REG_DSI_14nm_PHY_PLL_VCO_COUNT1 0x00000074
252
253 #define REG_DSI_14nm_PHY_PLL_VCO_COUNT2 0x00000078
254
255 #define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP1 0x0000007c
256
257 #define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP2 0x00000080
258
259 #define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP3 0x00000084
260
261 #define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP_EN 0x00000088
262
263 #define REG_DSI_14nm_PHY_PLL_PLL_VCO_TUNE 0x0000008c
264
265 #define REG_DSI_14nm_PHY_PLL_DEC_START 0x00000090
266
267 #define REG_DSI_14nm_PHY_PLL_SSC_EN_CENTER 0x00000094
268
269 #define REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER1 0x00000098
270
271 #define REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER2 0x0000009c
272
273 #define REG_DSI_14nm_PHY_PLL_SSC_PER1 0x000000a0
274
275 #define REG_DSI_14nm_PHY_PLL_SSC_PER2 0x000000a4
276
277 #define REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE1 0x000000a8
278
279 #define REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE2 0x000000ac
280
281 #define REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1 0x000000b4
282
283 #define REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2 0x000000b8
284
285 #define REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3 0x000000bc
286
287 #define REG_DSI_14nm_PHY_PLL_TXCLK_EN 0x000000c0
288
289 #define REG_DSI_14nm_PHY_PLL_PLL_CRCTRL 0x000000c4
290
291 #define REG_DSI_14nm_PHY_PLL_RESET_SM_READY_STATUS 0x000000cc
292
293 #define REG_DSI_14nm_PHY_PLL_PLL_MISC1 0x000000e8
294
295 #define REG_DSI_14nm_PHY_PLL_CP_SET_CUR 0x000000f0
296
297 #define REG_DSI_14nm_PHY_PLL_PLL_ICPMSET 0x000000f4
298
299 #define REG_DSI_14nm_PHY_PLL_PLL_ICPCSET 0x000000f8
300
301 #define REG_DSI_14nm_PHY_PLL_PLL_ICP_SET 0x000000fc
302
303 #define REG_DSI_14nm_PHY_PLL_PLL_LPF1 0x00000100
304
305 #define REG_DSI_14nm_PHY_PLL_PLL_LPF2_POSTDIV 0x00000104
306
307 #define REG_DSI_14nm_PHY_PLL_PLL_BANDGAP 0x00000108
308
309
310 #endif /* DSI_PHY_14NM_XML */
311