1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
4 *
5 * Based on sun4i_backend.c, which is:
6 * Copyright (C) 2015 Free Electrons
7 * Copyright (C) 2015 NextThing Co
8 */
9
10 #include <linux/component.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/module.h>
13 #include <linux/of_device.h>
14 #include <linux/of_graph.h>
15 #include <linux/reset.h>
16
17 #include <drm/drm_atomic_helper.h>
18 #include <drm/drm_crtc.h>
19 #include <drm/drm_fb_cma_helper.h>
20 #include <drm/drm_gem_cma_helper.h>
21 #include <drm/drm_plane_helper.h>
22 #include <drm/drm_probe_helper.h>
23
24 #include "sun4i_drv.h"
25 #include "sun8i_mixer.h"
26 #include "sun8i_ui_layer.h"
27 #include "sun8i_vi_layer.h"
28 #include "sunxi_engine.h"
29
30 struct de2_fmt_info {
31 u32 drm_fmt;
32 u32 de2_fmt;
33 };
34
35 static const struct de2_fmt_info de2_formats[] = {
36 {
37 .drm_fmt = DRM_FORMAT_ARGB8888,
38 .de2_fmt = SUN8I_MIXER_FBFMT_ARGB8888,
39 },
40 {
41 .drm_fmt = DRM_FORMAT_ABGR8888,
42 .de2_fmt = SUN8I_MIXER_FBFMT_ABGR8888,
43 },
44 {
45 .drm_fmt = DRM_FORMAT_RGBA8888,
46 .de2_fmt = SUN8I_MIXER_FBFMT_RGBA8888,
47 },
48 {
49 .drm_fmt = DRM_FORMAT_BGRA8888,
50 .de2_fmt = SUN8I_MIXER_FBFMT_BGRA8888,
51 },
52 {
53 .drm_fmt = DRM_FORMAT_XRGB8888,
54 .de2_fmt = SUN8I_MIXER_FBFMT_XRGB8888,
55 },
56 {
57 .drm_fmt = DRM_FORMAT_XBGR8888,
58 .de2_fmt = SUN8I_MIXER_FBFMT_XBGR8888,
59 },
60 {
61 .drm_fmt = DRM_FORMAT_RGBX8888,
62 .de2_fmt = SUN8I_MIXER_FBFMT_RGBX8888,
63 },
64 {
65 .drm_fmt = DRM_FORMAT_BGRX8888,
66 .de2_fmt = SUN8I_MIXER_FBFMT_BGRX8888,
67 },
68 {
69 .drm_fmt = DRM_FORMAT_RGB888,
70 .de2_fmt = SUN8I_MIXER_FBFMT_RGB888,
71 },
72 {
73 .drm_fmt = DRM_FORMAT_BGR888,
74 .de2_fmt = SUN8I_MIXER_FBFMT_BGR888,
75 },
76 {
77 .drm_fmt = DRM_FORMAT_RGB565,
78 .de2_fmt = SUN8I_MIXER_FBFMT_RGB565,
79 },
80 {
81 .drm_fmt = DRM_FORMAT_BGR565,
82 .de2_fmt = SUN8I_MIXER_FBFMT_BGR565,
83 },
84 {
85 .drm_fmt = DRM_FORMAT_ARGB4444,
86 .de2_fmt = SUN8I_MIXER_FBFMT_ARGB4444,
87 },
88 {
89 /* for DE2 VI layer which ignores alpha */
90 .drm_fmt = DRM_FORMAT_XRGB4444,
91 .de2_fmt = SUN8I_MIXER_FBFMT_ARGB4444,
92 },
93 {
94 .drm_fmt = DRM_FORMAT_ABGR4444,
95 .de2_fmt = SUN8I_MIXER_FBFMT_ABGR4444,
96 },
97 {
98 /* for DE2 VI layer which ignores alpha */
99 .drm_fmt = DRM_FORMAT_XBGR4444,
100 .de2_fmt = SUN8I_MIXER_FBFMT_ABGR4444,
101 },
102 {
103 .drm_fmt = DRM_FORMAT_RGBA4444,
104 .de2_fmt = SUN8I_MIXER_FBFMT_RGBA4444,
105 },
106 {
107 /* for DE2 VI layer which ignores alpha */
108 .drm_fmt = DRM_FORMAT_RGBX4444,
109 .de2_fmt = SUN8I_MIXER_FBFMT_RGBA4444,
110 },
111 {
112 .drm_fmt = DRM_FORMAT_BGRA4444,
113 .de2_fmt = SUN8I_MIXER_FBFMT_BGRA4444,
114 },
115 {
116 /* for DE2 VI layer which ignores alpha */
117 .drm_fmt = DRM_FORMAT_BGRX4444,
118 .de2_fmt = SUN8I_MIXER_FBFMT_BGRA4444,
119 },
120 {
121 .drm_fmt = DRM_FORMAT_ARGB1555,
122 .de2_fmt = SUN8I_MIXER_FBFMT_ARGB1555,
123 },
124 {
125 /* for DE2 VI layer which ignores alpha */
126 .drm_fmt = DRM_FORMAT_XRGB1555,
127 .de2_fmt = SUN8I_MIXER_FBFMT_ARGB1555,
128 },
129 {
130 .drm_fmt = DRM_FORMAT_ABGR1555,
131 .de2_fmt = SUN8I_MIXER_FBFMT_ABGR1555,
132 },
133 {
134 /* for DE2 VI layer which ignores alpha */
135 .drm_fmt = DRM_FORMAT_XBGR1555,
136 .de2_fmt = SUN8I_MIXER_FBFMT_ABGR1555,
137 },
138 {
139 .drm_fmt = DRM_FORMAT_RGBA5551,
140 .de2_fmt = SUN8I_MIXER_FBFMT_RGBA5551,
141 },
142 {
143 /* for DE2 VI layer which ignores alpha */
144 .drm_fmt = DRM_FORMAT_RGBX5551,
145 .de2_fmt = SUN8I_MIXER_FBFMT_RGBA5551,
146 },
147 {
148 .drm_fmt = DRM_FORMAT_BGRA5551,
149 .de2_fmt = SUN8I_MIXER_FBFMT_BGRA5551,
150 },
151 {
152 /* for DE2 VI layer which ignores alpha */
153 .drm_fmt = DRM_FORMAT_BGRX5551,
154 .de2_fmt = SUN8I_MIXER_FBFMT_BGRA5551,
155 },
156 {
157 .drm_fmt = DRM_FORMAT_ARGB2101010,
158 .de2_fmt = SUN8I_MIXER_FBFMT_ARGB2101010,
159 },
160 {
161 .drm_fmt = DRM_FORMAT_ABGR2101010,
162 .de2_fmt = SUN8I_MIXER_FBFMT_ABGR2101010,
163 },
164 {
165 .drm_fmt = DRM_FORMAT_RGBA1010102,
166 .de2_fmt = SUN8I_MIXER_FBFMT_RGBA1010102,
167 },
168 {
169 .drm_fmt = DRM_FORMAT_BGRA1010102,
170 .de2_fmt = SUN8I_MIXER_FBFMT_BGRA1010102,
171 },
172 {
173 .drm_fmt = DRM_FORMAT_UYVY,
174 .de2_fmt = SUN8I_MIXER_FBFMT_UYVY,
175 },
176 {
177 .drm_fmt = DRM_FORMAT_VYUY,
178 .de2_fmt = SUN8I_MIXER_FBFMT_VYUY,
179 },
180 {
181 .drm_fmt = DRM_FORMAT_YUYV,
182 .de2_fmt = SUN8I_MIXER_FBFMT_YUYV,
183 },
184 {
185 .drm_fmt = DRM_FORMAT_YVYU,
186 .de2_fmt = SUN8I_MIXER_FBFMT_YVYU,
187 },
188 {
189 .drm_fmt = DRM_FORMAT_NV16,
190 .de2_fmt = SUN8I_MIXER_FBFMT_NV16,
191 },
192 {
193 .drm_fmt = DRM_FORMAT_NV61,
194 .de2_fmt = SUN8I_MIXER_FBFMT_NV61,
195 },
196 {
197 .drm_fmt = DRM_FORMAT_NV12,
198 .de2_fmt = SUN8I_MIXER_FBFMT_NV12,
199 },
200 {
201 .drm_fmt = DRM_FORMAT_NV21,
202 .de2_fmt = SUN8I_MIXER_FBFMT_NV21,
203 },
204 {
205 .drm_fmt = DRM_FORMAT_YUV422,
206 .de2_fmt = SUN8I_MIXER_FBFMT_YUV422,
207 },
208 {
209 .drm_fmt = DRM_FORMAT_YUV420,
210 .de2_fmt = SUN8I_MIXER_FBFMT_YUV420,
211 },
212 {
213 .drm_fmt = DRM_FORMAT_YUV411,
214 .de2_fmt = SUN8I_MIXER_FBFMT_YUV411,
215 },
216 {
217 .drm_fmt = DRM_FORMAT_YVU422,
218 .de2_fmt = SUN8I_MIXER_FBFMT_YUV422,
219 },
220 {
221 .drm_fmt = DRM_FORMAT_YVU420,
222 .de2_fmt = SUN8I_MIXER_FBFMT_YUV420,
223 },
224 {
225 .drm_fmt = DRM_FORMAT_YVU411,
226 .de2_fmt = SUN8I_MIXER_FBFMT_YUV411,
227 },
228 {
229 .drm_fmt = DRM_FORMAT_P010,
230 .de2_fmt = SUN8I_MIXER_FBFMT_P010_YUV,
231 },
232 {
233 .drm_fmt = DRM_FORMAT_P210,
234 .de2_fmt = SUN8I_MIXER_FBFMT_P210_YUV,
235 },
236 };
237
sun8i_mixer_drm_format_to_hw(u32 format,u32 * hw_format)238 int sun8i_mixer_drm_format_to_hw(u32 format, u32 *hw_format)
239 {
240 unsigned int i;
241
242 for (i = 0; i < ARRAY_SIZE(de2_formats); ++i)
243 if (de2_formats[i].drm_fmt == format) {
244 *hw_format = de2_formats[i].de2_fmt;
245 return 0;
246 }
247
248 return -EINVAL;
249 }
250
sun8i_mixer_commit(struct sunxi_engine * engine)251 static void sun8i_mixer_commit(struct sunxi_engine *engine)
252 {
253 DRM_DEBUG_DRIVER("Committing changes\n");
254
255 regmap_write(engine->regs, SUN8I_MIXER_GLOBAL_DBUFF,
256 SUN8I_MIXER_GLOBAL_DBUFF_ENABLE);
257 }
258
sun8i_layers_init(struct drm_device * drm,struct sunxi_engine * engine)259 static struct drm_plane **sun8i_layers_init(struct drm_device *drm,
260 struct sunxi_engine *engine)
261 {
262 struct drm_plane **planes;
263 struct sun8i_mixer *mixer = engine_to_sun8i_mixer(engine);
264 int i;
265
266 planes = devm_kcalloc(drm->dev,
267 mixer->cfg->vi_num + mixer->cfg->ui_num + 1,
268 sizeof(*planes), GFP_KERNEL);
269 if (!planes)
270 return ERR_PTR(-ENOMEM);
271
272 for (i = 0; i < mixer->cfg->vi_num; i++) {
273 struct sun8i_vi_layer *layer;
274
275 layer = sun8i_vi_layer_init_one(drm, mixer, i);
276 if (IS_ERR(layer)) {
277 dev_err(drm->dev,
278 "Couldn't initialize overlay plane\n");
279 return ERR_CAST(layer);
280 }
281
282 planes[i] = &layer->plane;
283 }
284
285 for (i = 0; i < mixer->cfg->ui_num; i++) {
286 struct sun8i_ui_layer *layer;
287
288 layer = sun8i_ui_layer_init_one(drm, mixer, i);
289 if (IS_ERR(layer)) {
290 dev_err(drm->dev, "Couldn't initialize %s plane\n",
291 i ? "overlay" : "primary");
292 return ERR_CAST(layer);
293 }
294
295 planes[mixer->cfg->vi_num + i] = &layer->plane;
296 }
297
298 return planes;
299 }
300
301 static const struct sunxi_engine_ops sun8i_engine_ops = {
302 .commit = sun8i_mixer_commit,
303 .layers_init = sun8i_layers_init,
304 };
305
306 static const struct regmap_config sun8i_mixer_regmap_config = {
307 .reg_bits = 32,
308 .val_bits = 32,
309 .reg_stride = 4,
310 .max_register = 0xffffc, /* guessed */
311 };
312
sun8i_mixer_of_get_id(struct device_node * node)313 static int sun8i_mixer_of_get_id(struct device_node *node)
314 {
315 struct device_node *ep, *remote;
316 struct of_endpoint of_ep;
317
318 /* Output port is 1, and we want the first endpoint. */
319 ep = of_graph_get_endpoint_by_regs(node, 1, -1);
320 if (!ep)
321 return -EINVAL;
322
323 remote = of_graph_get_remote_endpoint(ep);
324 of_node_put(ep);
325 if (!remote)
326 return -EINVAL;
327
328 of_graph_parse_endpoint(remote, &of_ep);
329 of_node_put(remote);
330 return of_ep.id;
331 }
332
sun8i_mixer_bind(struct device * dev,struct device * master,void * data)333 static int sun8i_mixer_bind(struct device *dev, struct device *master,
334 void *data)
335 {
336 struct platform_device *pdev = to_platform_device(dev);
337 struct drm_device *drm = data;
338 struct sun4i_drv *drv = drm->dev_private;
339 struct sun8i_mixer *mixer;
340 void __iomem *regs;
341 unsigned int base;
342 int plane_cnt;
343 int i, ret;
344
345 /*
346 * The mixer uses single 32-bit register to store memory
347 * addresses, so that it cannot deal with 64-bit memory
348 * addresses.
349 * Restrict the DMA mask so that the mixer won't be
350 * allocated some memory that is too high.
351 */
352 ret = dma_set_mask(dev, DMA_BIT_MASK(32));
353 if (ret) {
354 dev_err(dev, "Cannot do 32-bit DMA.\n");
355 return ret;
356 }
357
358 mixer = devm_kzalloc(dev, sizeof(*mixer), GFP_KERNEL);
359 if (!mixer)
360 return -ENOMEM;
361 dev_set_drvdata(dev, mixer);
362 mixer->engine.ops = &sun8i_engine_ops;
363 mixer->engine.node = dev->of_node;
364
365 if (of_find_property(dev->of_node, "iommus", NULL)) {
366 /*
367 * This assume we have the same DMA constraints for
368 * all our the mixers in our pipeline. This sounds
369 * bad, but it has always been the case for us, and
370 * DRM doesn't do per-device allocation either, so we
371 * would need to fix DRM first...
372 */
373 ret = of_dma_configure(drm->dev, dev->of_node, true);
374 if (ret)
375 return ret;
376 }
377
378 /*
379 * While this function can fail, we shouldn't do anything
380 * if this happens. Some early DE2 DT entries don't provide
381 * mixer id but work nevertheless because matching between
382 * TCON and mixer is done by comparing node pointers (old
383 * way) instead comparing ids. If this function fails and
384 * id is needed, it will fail during id matching anyway.
385 */
386 mixer->engine.id = sun8i_mixer_of_get_id(dev->of_node);
387
388 mixer->cfg = of_device_get_match_data(dev);
389 if (!mixer->cfg)
390 return -EINVAL;
391
392 regs = devm_platform_ioremap_resource(pdev, 0);
393 if (IS_ERR(regs))
394 return PTR_ERR(regs);
395
396 mixer->engine.regs = devm_regmap_init_mmio(dev, regs,
397 &sun8i_mixer_regmap_config);
398 if (IS_ERR(mixer->engine.regs)) {
399 dev_err(dev, "Couldn't create the mixer regmap\n");
400 return PTR_ERR(mixer->engine.regs);
401 }
402
403 mixer->reset = devm_reset_control_get(dev, NULL);
404 if (IS_ERR(mixer->reset)) {
405 dev_err(dev, "Couldn't get our reset line\n");
406 return PTR_ERR(mixer->reset);
407 }
408
409 ret = reset_control_deassert(mixer->reset);
410 if (ret) {
411 dev_err(dev, "Couldn't deassert our reset line\n");
412 return ret;
413 }
414
415 mixer->bus_clk = devm_clk_get(dev, "bus");
416 if (IS_ERR(mixer->bus_clk)) {
417 dev_err(dev, "Couldn't get the mixer bus clock\n");
418 ret = PTR_ERR(mixer->bus_clk);
419 goto err_assert_reset;
420 }
421 clk_prepare_enable(mixer->bus_clk);
422
423 mixer->mod_clk = devm_clk_get(dev, "mod");
424 if (IS_ERR(mixer->mod_clk)) {
425 dev_err(dev, "Couldn't get the mixer module clock\n");
426 ret = PTR_ERR(mixer->mod_clk);
427 goto err_disable_bus_clk;
428 }
429
430 /*
431 * It seems that we need to enforce that rate for whatever
432 * reason for the mixer to be functional. Make sure it's the
433 * case.
434 */
435 if (mixer->cfg->mod_rate)
436 clk_set_rate(mixer->mod_clk, mixer->cfg->mod_rate);
437
438 clk_prepare_enable(mixer->mod_clk);
439
440 list_add_tail(&mixer->engine.list, &drv->engine_list);
441
442 base = sun8i_blender_base(mixer);
443
444 /* Reset registers and disable unused sub-engines */
445 if (mixer->cfg->is_de3) {
446 for (i = 0; i < DE3_MIXER_UNIT_SIZE; i += 4)
447 regmap_write(mixer->engine.regs, i, 0);
448
449 regmap_write(mixer->engine.regs, SUN50I_MIXER_FCE_EN, 0);
450 regmap_write(mixer->engine.regs, SUN50I_MIXER_PEAK_EN, 0);
451 regmap_write(mixer->engine.regs, SUN50I_MIXER_LCTI_EN, 0);
452 regmap_write(mixer->engine.regs, SUN50I_MIXER_BLS_EN, 0);
453 regmap_write(mixer->engine.regs, SUN50I_MIXER_FCC_EN, 0);
454 regmap_write(mixer->engine.regs, SUN50I_MIXER_DNS_EN, 0);
455 regmap_write(mixer->engine.regs, SUN50I_MIXER_DRC_EN, 0);
456 regmap_write(mixer->engine.regs, SUN50I_MIXER_FMT_EN, 0);
457 regmap_write(mixer->engine.regs, SUN50I_MIXER_CDC0_EN, 0);
458 regmap_write(mixer->engine.regs, SUN50I_MIXER_CDC1_EN, 0);
459 } else {
460 for (i = 0; i < DE2_MIXER_UNIT_SIZE; i += 4)
461 regmap_write(mixer->engine.regs, i, 0);
462
463 regmap_write(mixer->engine.regs, SUN8I_MIXER_FCE_EN, 0);
464 regmap_write(mixer->engine.regs, SUN8I_MIXER_BWS_EN, 0);
465 regmap_write(mixer->engine.regs, SUN8I_MIXER_LTI_EN, 0);
466 regmap_write(mixer->engine.regs, SUN8I_MIXER_PEAK_EN, 0);
467 regmap_write(mixer->engine.regs, SUN8I_MIXER_ASE_EN, 0);
468 regmap_write(mixer->engine.regs, SUN8I_MIXER_FCC_EN, 0);
469 regmap_write(mixer->engine.regs, SUN8I_MIXER_DCSC_EN, 0);
470 }
471
472 /* Enable the mixer */
473 regmap_write(mixer->engine.regs, SUN8I_MIXER_GLOBAL_CTL,
474 SUN8I_MIXER_GLOBAL_CTL_RT_EN);
475
476 /* Set background color to black */
477 regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_BKCOLOR(base),
478 SUN8I_MIXER_BLEND_COLOR_BLACK);
479
480 /*
481 * Set fill color of bottom plane to black. Generally not needed
482 * except when VI plane is at bottom (zpos = 0) and enabled.
483 */
484 regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_PIPE_CTL(base),
485 SUN8I_MIXER_BLEND_PIPE_CTL_FC_EN(0));
486 regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_ATTR_FCOLOR(base, 0),
487 SUN8I_MIXER_BLEND_COLOR_BLACK);
488
489 plane_cnt = mixer->cfg->vi_num + mixer->cfg->ui_num;
490 for (i = 0; i < plane_cnt; i++)
491 regmap_write(mixer->engine.regs,
492 SUN8I_MIXER_BLEND_MODE(base, i),
493 SUN8I_MIXER_BLEND_MODE_DEF);
494
495 regmap_update_bits(mixer->engine.regs, SUN8I_MIXER_BLEND_PIPE_CTL(base),
496 SUN8I_MIXER_BLEND_PIPE_CTL_EN_MSK, 0);
497
498 return 0;
499
500 err_disable_bus_clk:
501 clk_disable_unprepare(mixer->bus_clk);
502 err_assert_reset:
503 reset_control_assert(mixer->reset);
504 return ret;
505 }
506
sun8i_mixer_unbind(struct device * dev,struct device * master,void * data)507 static void sun8i_mixer_unbind(struct device *dev, struct device *master,
508 void *data)
509 {
510 struct sun8i_mixer *mixer = dev_get_drvdata(dev);
511
512 list_del(&mixer->engine.list);
513
514 clk_disable_unprepare(mixer->mod_clk);
515 clk_disable_unprepare(mixer->bus_clk);
516 reset_control_assert(mixer->reset);
517 }
518
519 static const struct component_ops sun8i_mixer_ops = {
520 .bind = sun8i_mixer_bind,
521 .unbind = sun8i_mixer_unbind,
522 };
523
sun8i_mixer_probe(struct platform_device * pdev)524 static int sun8i_mixer_probe(struct platform_device *pdev)
525 {
526 return component_add(&pdev->dev, &sun8i_mixer_ops);
527 }
528
sun8i_mixer_remove(struct platform_device * pdev)529 static int sun8i_mixer_remove(struct platform_device *pdev)
530 {
531 component_del(&pdev->dev, &sun8i_mixer_ops);
532
533 return 0;
534 }
535
536 static const struct sun8i_mixer_cfg sun8i_a83t_mixer0_cfg = {
537 .ccsc = 0,
538 .scaler_mask = 0xf,
539 .scanline_yuv = 2048,
540 .ui_num = 3,
541 .vi_num = 1,
542 };
543
544 static const struct sun8i_mixer_cfg sun8i_a83t_mixer1_cfg = {
545 .ccsc = 1,
546 .scaler_mask = 0x3,
547 .scanline_yuv = 2048,
548 .ui_num = 1,
549 .vi_num = 1,
550 };
551
552 static const struct sun8i_mixer_cfg sun8i_h3_mixer0_cfg = {
553 .ccsc = 0,
554 .mod_rate = 432000000,
555 .scaler_mask = 0xf,
556 .scanline_yuv = 2048,
557 .ui_num = 3,
558 .vi_num = 1,
559 };
560
561 static const struct sun8i_mixer_cfg sun8i_r40_mixer0_cfg = {
562 .ccsc = 0,
563 .mod_rate = 297000000,
564 .scaler_mask = 0xf,
565 .scanline_yuv = 2048,
566 .ui_num = 3,
567 .vi_num = 1,
568 };
569
570 static const struct sun8i_mixer_cfg sun8i_r40_mixer1_cfg = {
571 .ccsc = 1,
572 .mod_rate = 297000000,
573 .scaler_mask = 0x3,
574 .scanline_yuv = 2048,
575 .ui_num = 1,
576 .vi_num = 1,
577 };
578
579 static const struct sun8i_mixer_cfg sun8i_v3s_mixer_cfg = {
580 .vi_num = 2,
581 .ui_num = 1,
582 .scaler_mask = 0x3,
583 .scanline_yuv = 2048,
584 .ccsc = 0,
585 .mod_rate = 150000000,
586 };
587
588 static const struct sun8i_mixer_cfg sun50i_a64_mixer0_cfg = {
589 .ccsc = 0,
590 .mod_rate = 297000000,
591 .scaler_mask = 0xf,
592 .scanline_yuv = 4096,
593 .ui_num = 3,
594 .vi_num = 1,
595 };
596
597 static const struct sun8i_mixer_cfg sun50i_a64_mixer1_cfg = {
598 .ccsc = 1,
599 .mod_rate = 297000000,
600 .scaler_mask = 0x3,
601 .scanline_yuv = 2048,
602 .ui_num = 1,
603 .vi_num = 1,
604 };
605
606 static const struct sun8i_mixer_cfg sun50i_h6_mixer0_cfg = {
607 .ccsc = 0,
608 .is_de3 = true,
609 .mod_rate = 600000000,
610 .scaler_mask = 0xf,
611 .scanline_yuv = 4096,
612 .ui_num = 3,
613 .vi_num = 1,
614 };
615
616 static const struct of_device_id sun8i_mixer_of_table[] = {
617 {
618 .compatible = "allwinner,sun8i-a83t-de2-mixer-0",
619 .data = &sun8i_a83t_mixer0_cfg,
620 },
621 {
622 .compatible = "allwinner,sun8i-a83t-de2-mixer-1",
623 .data = &sun8i_a83t_mixer1_cfg,
624 },
625 {
626 .compatible = "allwinner,sun8i-h3-de2-mixer-0",
627 .data = &sun8i_h3_mixer0_cfg,
628 },
629 {
630 .compatible = "allwinner,sun8i-r40-de2-mixer-0",
631 .data = &sun8i_r40_mixer0_cfg,
632 },
633 {
634 .compatible = "allwinner,sun8i-r40-de2-mixer-1",
635 .data = &sun8i_r40_mixer1_cfg,
636 },
637 {
638 .compatible = "allwinner,sun8i-v3s-de2-mixer",
639 .data = &sun8i_v3s_mixer_cfg,
640 },
641 {
642 .compatible = "allwinner,sun50i-a64-de2-mixer-0",
643 .data = &sun50i_a64_mixer0_cfg,
644 },
645 {
646 .compatible = "allwinner,sun50i-a64-de2-mixer-1",
647 .data = &sun50i_a64_mixer1_cfg,
648 },
649 {
650 .compatible = "allwinner,sun50i-h6-de3-mixer-0",
651 .data = &sun50i_h6_mixer0_cfg,
652 },
653 { }
654 };
655 MODULE_DEVICE_TABLE(of, sun8i_mixer_of_table);
656
657 static struct platform_driver sun8i_mixer_platform_driver = {
658 .probe = sun8i_mixer_probe,
659 .remove = sun8i_mixer_remove,
660 .driver = {
661 .name = "sun8i-mixer",
662 .of_match_table = sun8i_mixer_of_table,
663 },
664 };
665 module_platform_driver(sun8i_mixer_platform_driver);
666
667 MODULE_AUTHOR("Icenowy Zheng <icenowy@aosc.io>");
668 MODULE_DESCRIPTION("Allwinner DE2 Mixer driver");
669 MODULE_LICENSE("GPL");
670