1 /*
2 * Copyright (C) 2014 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation version 2.
7 *
8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9 * kind, whether express or implied; without even the implied warranty
10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14 #include <linux/delay.h>
15 #include <linux/i2c.h>
16 #include <linux/interrupt.h>
17 #include <linux/io.h>
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/of_device.h>
21 #include <linux/platform_device.h>
22 #include <linux/slab.h>
23
24 #define IDM_CTRL_DIRECT_OFFSET 0x00
25 #define CFG_OFFSET 0x00
26 #define CFG_RESET_SHIFT 31
27 #define CFG_EN_SHIFT 30
28 #define CFG_SLAVE_ADDR_0_SHIFT 28
29 #define CFG_M_RETRY_CNT_SHIFT 16
30 #define CFG_M_RETRY_CNT_MASK 0x0f
31
32 #define TIM_CFG_OFFSET 0x04
33 #define TIM_CFG_MODE_400_SHIFT 31
34 #define TIM_RAND_SLAVE_STRETCH_SHIFT 24
35 #define TIM_RAND_SLAVE_STRETCH_MASK 0x7f
36 #define TIM_PERIODIC_SLAVE_STRETCH_SHIFT 16
37 #define TIM_PERIODIC_SLAVE_STRETCH_MASK 0x7f
38
39 #define S_CFG_SMBUS_ADDR_OFFSET 0x08
40 #define S_CFG_EN_NIC_SMB_ADDR3_SHIFT 31
41 #define S_CFG_NIC_SMB_ADDR3_SHIFT 24
42 #define S_CFG_NIC_SMB_ADDR3_MASK 0x7f
43 #define S_CFG_EN_NIC_SMB_ADDR2_SHIFT 23
44 #define S_CFG_NIC_SMB_ADDR2_SHIFT 16
45 #define S_CFG_NIC_SMB_ADDR2_MASK 0x7f
46 #define S_CFG_EN_NIC_SMB_ADDR1_SHIFT 15
47 #define S_CFG_NIC_SMB_ADDR1_SHIFT 8
48 #define S_CFG_NIC_SMB_ADDR1_MASK 0x7f
49 #define S_CFG_EN_NIC_SMB_ADDR0_SHIFT 7
50 #define S_CFG_NIC_SMB_ADDR0_SHIFT 0
51 #define S_CFG_NIC_SMB_ADDR0_MASK 0x7f
52
53 #define M_FIFO_CTRL_OFFSET 0x0c
54 #define M_FIFO_RX_FLUSH_SHIFT 31
55 #define M_FIFO_TX_FLUSH_SHIFT 30
56 #define M_FIFO_RX_CNT_SHIFT 16
57 #define M_FIFO_RX_CNT_MASK 0x7f
58 #define M_FIFO_RX_THLD_SHIFT 8
59 #define M_FIFO_RX_THLD_MASK 0x3f
60
61 #define S_FIFO_CTRL_OFFSET 0x10
62 #define S_FIFO_RX_FLUSH_SHIFT 31
63 #define S_FIFO_TX_FLUSH_SHIFT 30
64 #define S_FIFO_RX_CNT_SHIFT 16
65 #define S_FIFO_RX_CNT_MASK 0x7f
66 #define S_FIFO_RX_THLD_SHIFT 8
67 #define S_FIFO_RX_THLD_MASK 0x3f
68
69 #define M_CMD_OFFSET 0x30
70 #define M_CMD_START_BUSY_SHIFT 31
71 #define M_CMD_STATUS_SHIFT 25
72 #define M_CMD_STATUS_MASK 0x07
73 #define M_CMD_STATUS_SUCCESS 0x0
74 #define M_CMD_STATUS_LOST_ARB 0x1
75 #define M_CMD_STATUS_NACK_ADDR 0x2
76 #define M_CMD_STATUS_NACK_DATA 0x3
77 #define M_CMD_STATUS_TIMEOUT 0x4
78 #define M_CMD_STATUS_FIFO_UNDERRUN 0x5
79 #define M_CMD_STATUS_RX_FIFO_FULL 0x6
80 #define M_CMD_PROTOCOL_SHIFT 9
81 #define M_CMD_PROTOCOL_MASK 0xf
82 #define M_CMD_PROTOCOL_QUICK 0x0
83 #define M_CMD_PROTOCOL_BLK_WR 0x7
84 #define M_CMD_PROTOCOL_BLK_RD 0x8
85 #define M_CMD_PROTOCOL_PROCESS 0xa
86 #define M_CMD_PEC_SHIFT 8
87 #define M_CMD_RD_CNT_SHIFT 0
88 #define M_CMD_RD_CNT_MASK 0xff
89
90 #define S_CMD_OFFSET 0x34
91 #define S_CMD_START_BUSY_SHIFT 31
92 #define S_CMD_STATUS_SHIFT 23
93 #define S_CMD_STATUS_MASK 0x07
94 #define S_CMD_STATUS_SUCCESS 0x0
95 #define S_CMD_STATUS_TIMEOUT 0x5
96 #define S_CMD_STATUS_MASTER_ABORT 0x7
97
98 #define IE_OFFSET 0x38
99 #define IE_M_RX_FIFO_FULL_SHIFT 31
100 #define IE_M_RX_THLD_SHIFT 30
101 #define IE_M_START_BUSY_SHIFT 28
102 #define IE_M_TX_UNDERRUN_SHIFT 27
103 #define IE_S_RX_FIFO_FULL_SHIFT 26
104 #define IE_S_RX_THLD_SHIFT 25
105 #define IE_S_RX_EVENT_SHIFT 24
106 #define IE_S_START_BUSY_SHIFT 23
107 #define IE_S_TX_UNDERRUN_SHIFT 22
108 #define IE_S_RD_EVENT_SHIFT 21
109
110 #define IS_OFFSET 0x3c
111 #define IS_M_RX_FIFO_FULL_SHIFT 31
112 #define IS_M_RX_THLD_SHIFT 30
113 #define IS_M_START_BUSY_SHIFT 28
114 #define IS_M_TX_UNDERRUN_SHIFT 27
115 #define IS_S_RX_FIFO_FULL_SHIFT 26
116 #define IS_S_RX_THLD_SHIFT 25
117 #define IS_S_RX_EVENT_SHIFT 24
118 #define IS_S_START_BUSY_SHIFT 23
119 #define IS_S_TX_UNDERRUN_SHIFT 22
120 #define IS_S_RD_EVENT_SHIFT 21
121
122 #define M_TX_OFFSET 0x40
123 #define M_TX_WR_STATUS_SHIFT 31
124 #define M_TX_DATA_SHIFT 0
125 #define M_TX_DATA_MASK 0xff
126
127 #define M_RX_OFFSET 0x44
128 #define M_RX_STATUS_SHIFT 30
129 #define M_RX_STATUS_MASK 0x03
130 #define M_RX_PEC_ERR_SHIFT 29
131 #define M_RX_DATA_SHIFT 0
132 #define M_RX_DATA_MASK 0xff
133
134 #define S_TX_OFFSET 0x48
135 #define S_TX_WR_STATUS_SHIFT 31
136 #define S_TX_DATA_SHIFT 0
137 #define S_TX_DATA_MASK 0xff
138
139 #define S_RX_OFFSET 0x4c
140 #define S_RX_STATUS_SHIFT 30
141 #define S_RX_STATUS_MASK 0x03
142 #define S_RX_PEC_ERR_SHIFT 29
143 #define S_RX_DATA_SHIFT 0
144 #define S_RX_DATA_MASK 0xff
145
146 #define I2C_TIMEOUT_MSEC 50000
147 #define M_TX_RX_FIFO_SIZE 64
148 #define M_RX_FIFO_MAX_THLD_VALUE (M_TX_RX_FIFO_SIZE - 1)
149
150 #define M_RX_MAX_READ_LEN 255
151 #define M_RX_FIFO_THLD_VALUE 50
152
153 #define IE_M_ALL_INTERRUPT_SHIFT 27
154 #define IE_M_ALL_INTERRUPT_MASK 0x1e
155
156 #define SLAVE_READ_WRITE_BIT_MASK 0x1
157 #define SLAVE_READ_WRITE_BIT_SHIFT 0x1
158 #define SLAVE_MAX_SIZE_TRANSACTION 64
159 #define SLAVE_CLOCK_STRETCH_TIME 25
160
161 #define IE_S_ALL_INTERRUPT_SHIFT 21
162 #define IE_S_ALL_INTERRUPT_MASK 0x3f
163 /*
164 * It takes ~18us to reading 10bytes of data, hence to keep tasklet
165 * running for less time, max slave read per tasklet is set to 10 bytes.
166 */
167 #define MAX_SLAVE_RX_PER_INT 10
168
169 enum i2c_slave_read_status {
170 I2C_SLAVE_RX_FIFO_EMPTY = 0,
171 I2C_SLAVE_RX_START,
172 I2C_SLAVE_RX_DATA,
173 I2C_SLAVE_RX_END,
174 };
175
176 enum bus_speed_index {
177 I2C_SPD_100K = 0,
178 I2C_SPD_400K,
179 };
180
181 enum bcm_iproc_i2c_type {
182 IPROC_I2C,
183 IPROC_I2C_NIC
184 };
185
186 struct bcm_iproc_i2c_dev {
187 struct device *device;
188 enum bcm_iproc_i2c_type type;
189 int irq;
190
191 void __iomem *base;
192 void __iomem *idm_base;
193
194 u32 ape_addr_mask;
195
196 /* lock for indirect access through IDM */
197 spinlock_t idm_lock;
198
199 struct i2c_adapter adapter;
200 unsigned int bus_speed;
201
202 struct completion done;
203 int xfer_is_done;
204
205 struct i2c_msg *msg;
206
207 struct i2c_client *slave;
208
209 /* bytes that have been transferred */
210 unsigned int tx_bytes;
211 /* bytes that have been read */
212 unsigned int rx_bytes;
213 unsigned int thld_bytes;
214
215 bool slave_rx_only;
216 bool rx_start_rcvd;
217 bool slave_read_complete;
218 u32 tx_underrun;
219 u32 slave_int_mask;
220 struct tasklet_struct slave_rx_tasklet;
221 };
222
223 /* tasklet to process slave rx data */
224 static void slave_rx_tasklet_fn(unsigned long);
225
226 /*
227 * Can be expanded in the future if more interrupt status bits are utilized
228 */
229 #define ISR_MASK (BIT(IS_M_START_BUSY_SHIFT) | BIT(IS_M_TX_UNDERRUN_SHIFT)\
230 | BIT(IS_M_RX_THLD_SHIFT))
231
232 #define ISR_MASK_SLAVE (BIT(IS_S_START_BUSY_SHIFT)\
233 | BIT(IS_S_RX_EVENT_SHIFT) | BIT(IS_S_RD_EVENT_SHIFT)\
234 | BIT(IS_S_TX_UNDERRUN_SHIFT) | BIT(IS_S_RX_FIFO_FULL_SHIFT)\
235 | BIT(IS_S_RX_THLD_SHIFT))
236
237 static int bcm_iproc_i2c_reg_slave(struct i2c_client *slave);
238 static int bcm_iproc_i2c_unreg_slave(struct i2c_client *slave);
239 static void bcm_iproc_i2c_enable_disable(struct bcm_iproc_i2c_dev *iproc_i2c,
240 bool enable);
241
iproc_i2c_rd_reg(struct bcm_iproc_i2c_dev * iproc_i2c,u32 offset)242 static inline u32 iproc_i2c_rd_reg(struct bcm_iproc_i2c_dev *iproc_i2c,
243 u32 offset)
244 {
245 u32 val;
246
247 if (iproc_i2c->idm_base) {
248 spin_lock(&iproc_i2c->idm_lock);
249 writel(iproc_i2c->ape_addr_mask,
250 iproc_i2c->idm_base + IDM_CTRL_DIRECT_OFFSET);
251 val = readl(iproc_i2c->base + offset);
252 spin_unlock(&iproc_i2c->idm_lock);
253 } else {
254 val = readl(iproc_i2c->base + offset);
255 }
256
257 return val;
258 }
259
iproc_i2c_wr_reg(struct bcm_iproc_i2c_dev * iproc_i2c,u32 offset,u32 val)260 static inline void iproc_i2c_wr_reg(struct bcm_iproc_i2c_dev *iproc_i2c,
261 u32 offset, u32 val)
262 {
263 if (iproc_i2c->idm_base) {
264 spin_lock(&iproc_i2c->idm_lock);
265 writel(iproc_i2c->ape_addr_mask,
266 iproc_i2c->idm_base + IDM_CTRL_DIRECT_OFFSET);
267 writel(val, iproc_i2c->base + offset);
268 spin_unlock(&iproc_i2c->idm_lock);
269 } else {
270 writel(val, iproc_i2c->base + offset);
271 }
272 }
273
bcm_iproc_i2c_slave_init(struct bcm_iproc_i2c_dev * iproc_i2c,bool need_reset)274 static void bcm_iproc_i2c_slave_init(
275 struct bcm_iproc_i2c_dev *iproc_i2c, bool need_reset)
276 {
277 u32 val;
278
279 iproc_i2c->tx_underrun = 0;
280 if (need_reset) {
281 /* put controller in reset */
282 val = iproc_i2c_rd_reg(iproc_i2c, CFG_OFFSET);
283 val |= BIT(CFG_RESET_SHIFT);
284 iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
285
286 /* wait 100 usec per spec */
287 udelay(100);
288
289 /* bring controller out of reset */
290 val &= ~(BIT(CFG_RESET_SHIFT));
291 iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
292 }
293
294 /* flush TX/RX FIFOs */
295 val = (BIT(S_FIFO_RX_FLUSH_SHIFT) | BIT(S_FIFO_TX_FLUSH_SHIFT));
296 iproc_i2c_wr_reg(iproc_i2c, S_FIFO_CTRL_OFFSET, val);
297
298 /* Maximum slave stretch time */
299 val = iproc_i2c_rd_reg(iproc_i2c, TIM_CFG_OFFSET);
300 val &= ~(TIM_RAND_SLAVE_STRETCH_MASK << TIM_RAND_SLAVE_STRETCH_SHIFT);
301 val |= (SLAVE_CLOCK_STRETCH_TIME << TIM_RAND_SLAVE_STRETCH_SHIFT);
302 iproc_i2c_wr_reg(iproc_i2c, TIM_CFG_OFFSET, val);
303
304 /* Configure the slave address */
305 val = iproc_i2c_rd_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET);
306 val |= BIT(S_CFG_EN_NIC_SMB_ADDR3_SHIFT);
307 val &= ~(S_CFG_NIC_SMB_ADDR3_MASK << S_CFG_NIC_SMB_ADDR3_SHIFT);
308 val |= (iproc_i2c->slave->addr << S_CFG_NIC_SMB_ADDR3_SHIFT);
309 iproc_i2c_wr_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET, val);
310
311 /* clear all pending slave interrupts */
312 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, ISR_MASK_SLAVE);
313
314 /* Enable interrupt register to indicate a valid byte in receive fifo */
315 val = BIT(IE_S_RX_EVENT_SHIFT);
316 /* Enable interrupt register to indicate Slave Rx FIFO Full */
317 val |= BIT(IE_S_RX_FIFO_FULL_SHIFT);
318 /* Enable interrupt register to indicate a Master read transaction */
319 val |= BIT(IE_S_RD_EVENT_SHIFT);
320 /* Enable interrupt register for the Slave BUSY command */
321 val |= BIT(IE_S_START_BUSY_SHIFT);
322 iproc_i2c->slave_int_mask = val;
323 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
324 }
325
bcm_iproc_i2c_check_slave_status(struct bcm_iproc_i2c_dev * iproc_i2c)326 static void bcm_iproc_i2c_check_slave_status(
327 struct bcm_iproc_i2c_dev *iproc_i2c)
328 {
329 u32 val;
330
331 val = iproc_i2c_rd_reg(iproc_i2c, S_CMD_OFFSET);
332 /* status is valid only when START_BUSY is cleared after it was set */
333 if (val & BIT(S_CMD_START_BUSY_SHIFT))
334 return;
335
336 val = (val >> S_CMD_STATUS_SHIFT) & S_CMD_STATUS_MASK;
337 if (val == S_CMD_STATUS_TIMEOUT || val == S_CMD_STATUS_MASTER_ABORT) {
338 dev_err(iproc_i2c->device, (val == S_CMD_STATUS_TIMEOUT) ?
339 "slave random stretch time timeout\n" :
340 "Master aborted read transaction\n");
341 /* re-initialize i2c for recovery */
342 bcm_iproc_i2c_enable_disable(iproc_i2c, false);
343 bcm_iproc_i2c_slave_init(iproc_i2c, true);
344 bcm_iproc_i2c_enable_disable(iproc_i2c, true);
345 }
346 }
347
bcm_iproc_i2c_slave_read(struct bcm_iproc_i2c_dev * iproc_i2c)348 static void bcm_iproc_i2c_slave_read(struct bcm_iproc_i2c_dev *iproc_i2c)
349 {
350 u8 rx_data, rx_status;
351 u32 rx_bytes = 0;
352 u32 val;
353
354 while (rx_bytes < MAX_SLAVE_RX_PER_INT) {
355 val = iproc_i2c_rd_reg(iproc_i2c, S_RX_OFFSET);
356 rx_status = (val >> S_RX_STATUS_SHIFT) & S_RX_STATUS_MASK;
357 rx_data = ((val >> S_RX_DATA_SHIFT) & S_RX_DATA_MASK);
358
359 if (rx_status == I2C_SLAVE_RX_START) {
360 /* Start of SMBUS Master write */
361 i2c_slave_event(iproc_i2c->slave,
362 I2C_SLAVE_WRITE_REQUESTED, &rx_data);
363 iproc_i2c->rx_start_rcvd = true;
364 iproc_i2c->slave_read_complete = false;
365 } else if (rx_status == I2C_SLAVE_RX_DATA &&
366 iproc_i2c->rx_start_rcvd) {
367 /* Middle of SMBUS Master write */
368 i2c_slave_event(iproc_i2c->slave,
369 I2C_SLAVE_WRITE_RECEIVED, &rx_data);
370 } else if (rx_status == I2C_SLAVE_RX_END &&
371 iproc_i2c->rx_start_rcvd) {
372 /* End of SMBUS Master write */
373 if (iproc_i2c->slave_rx_only)
374 i2c_slave_event(iproc_i2c->slave,
375 I2C_SLAVE_WRITE_RECEIVED,
376 &rx_data);
377
378 i2c_slave_event(iproc_i2c->slave, I2C_SLAVE_STOP,
379 &rx_data);
380 } else if (rx_status == I2C_SLAVE_RX_FIFO_EMPTY) {
381 iproc_i2c->rx_start_rcvd = false;
382 iproc_i2c->slave_read_complete = true;
383 break;
384 }
385
386 rx_bytes++;
387 }
388 }
389
slave_rx_tasklet_fn(unsigned long data)390 static void slave_rx_tasklet_fn(unsigned long data)
391 {
392 struct bcm_iproc_i2c_dev *iproc_i2c = (struct bcm_iproc_i2c_dev *)data;
393 u32 int_clr;
394
395 bcm_iproc_i2c_slave_read(iproc_i2c);
396
397 /* clear pending IS_S_RX_EVENT_SHIFT interrupt */
398 int_clr = BIT(IS_S_RX_EVENT_SHIFT);
399
400 if (!iproc_i2c->slave_rx_only && iproc_i2c->slave_read_complete) {
401 /*
402 * In case of single byte master-read request,
403 * IS_S_TX_UNDERRUN_SHIFT event is generated before
404 * IS_S_START_BUSY_SHIFT event. Hence start slave data send
405 * from first IS_S_TX_UNDERRUN_SHIFT event.
406 *
407 * This means don't send any data from slave when
408 * IS_S_RD_EVENT_SHIFT event is generated else it will increment
409 * eeprom or other backend slave driver read pointer twice.
410 */
411 iproc_i2c->tx_underrun = 0;
412 iproc_i2c->slave_int_mask |= BIT(IE_S_TX_UNDERRUN_SHIFT);
413
414 /* clear IS_S_RD_EVENT_SHIFT interrupt */
415 int_clr |= BIT(IS_S_RD_EVENT_SHIFT);
416 }
417
418 /* clear slave interrupt */
419 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, int_clr);
420 /* enable slave interrupts */
421 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, iproc_i2c->slave_int_mask);
422 }
423
bcm_iproc_i2c_slave_isr(struct bcm_iproc_i2c_dev * iproc_i2c,u32 status)424 static bool bcm_iproc_i2c_slave_isr(struct bcm_iproc_i2c_dev *iproc_i2c,
425 u32 status)
426 {
427 u32 val;
428 u8 value;
429
430 /*
431 * Slave events in case of master-write, master-write-read and,
432 * master-read
433 *
434 * Master-write : only IS_S_RX_EVENT_SHIFT event
435 * Master-write-read: both IS_S_RX_EVENT_SHIFT and IS_S_RD_EVENT_SHIFT
436 * events
437 * Master-read : both IS_S_RX_EVENT_SHIFT and IS_S_RD_EVENT_SHIFT
438 * events or only IS_S_RD_EVENT_SHIFT
439 *
440 * iproc has a slave rx fifo size of 64 bytes. Rx fifo full interrupt
441 * (IS_S_RX_FIFO_FULL_SHIFT) will be generated when RX fifo becomes
442 * full. This can happen if Master issues write requests of more than
443 * 64 bytes.
444 */
445 if (status & BIT(IS_S_RX_EVENT_SHIFT) ||
446 status & BIT(IS_S_RD_EVENT_SHIFT) ||
447 status & BIT(IS_S_RX_FIFO_FULL_SHIFT)) {
448 /* disable slave interrupts */
449 val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
450 val &= ~iproc_i2c->slave_int_mask;
451 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
452
453 if (status & BIT(IS_S_RD_EVENT_SHIFT))
454 /* Master-write-read request */
455 iproc_i2c->slave_rx_only = false;
456 else
457 /* Master-write request only */
458 iproc_i2c->slave_rx_only = true;
459
460 /* schedule tasklet to read data later */
461 tasklet_schedule(&iproc_i2c->slave_rx_tasklet);
462
463 /*
464 * clear only IS_S_RX_EVENT_SHIFT and
465 * IS_S_RX_FIFO_FULL_SHIFT interrupt.
466 */
467 val = BIT(IS_S_RX_EVENT_SHIFT);
468 if (status & BIT(IS_S_RX_FIFO_FULL_SHIFT))
469 val |= BIT(IS_S_RX_FIFO_FULL_SHIFT);
470 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, val);
471 }
472
473 if (status & BIT(IS_S_TX_UNDERRUN_SHIFT)) {
474 iproc_i2c->tx_underrun++;
475 if (iproc_i2c->tx_underrun == 1)
476 /* Start of SMBUS for Master Read */
477 i2c_slave_event(iproc_i2c->slave,
478 I2C_SLAVE_READ_REQUESTED,
479 &value);
480 else
481 /* Master read other than start */
482 i2c_slave_event(iproc_i2c->slave,
483 I2C_SLAVE_READ_PROCESSED,
484 &value);
485
486 iproc_i2c_wr_reg(iproc_i2c, S_TX_OFFSET, value);
487 /* start transfer */
488 val = BIT(S_CMD_START_BUSY_SHIFT);
489 iproc_i2c_wr_reg(iproc_i2c, S_CMD_OFFSET, val);
490
491 /* clear interrupt */
492 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET,
493 BIT(IS_S_TX_UNDERRUN_SHIFT));
494 }
495
496 /* Stop received from master in case of master read transaction */
497 if (status & BIT(IS_S_START_BUSY_SHIFT)) {
498 /*
499 * Disable interrupt for TX FIFO becomes empty and
500 * less than PKT_LENGTH bytes were output on the SMBUS
501 */
502 iproc_i2c->slave_int_mask &= ~BIT(IE_S_TX_UNDERRUN_SHIFT);
503 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET,
504 iproc_i2c->slave_int_mask);
505
506 /* End of SMBUS for Master Read */
507 val = BIT(S_TX_WR_STATUS_SHIFT);
508 iproc_i2c_wr_reg(iproc_i2c, S_TX_OFFSET, val);
509
510 val = BIT(S_CMD_START_BUSY_SHIFT);
511 iproc_i2c_wr_reg(iproc_i2c, S_CMD_OFFSET, val);
512
513 /* flush TX FIFOs */
514 val = iproc_i2c_rd_reg(iproc_i2c, S_FIFO_CTRL_OFFSET);
515 val |= (BIT(S_FIFO_TX_FLUSH_SHIFT));
516 iproc_i2c_wr_reg(iproc_i2c, S_FIFO_CTRL_OFFSET, val);
517
518 i2c_slave_event(iproc_i2c->slave, I2C_SLAVE_STOP, &value);
519
520 /* clear interrupt */
521 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET,
522 BIT(IS_S_START_BUSY_SHIFT));
523 }
524
525 /* check slave transmit status only if slave is transmitting */
526 if (!iproc_i2c->slave_rx_only)
527 bcm_iproc_i2c_check_slave_status(iproc_i2c);
528
529 return true;
530 }
531
bcm_iproc_i2c_read_valid_bytes(struct bcm_iproc_i2c_dev * iproc_i2c)532 static void bcm_iproc_i2c_read_valid_bytes(struct bcm_iproc_i2c_dev *iproc_i2c)
533 {
534 struct i2c_msg *msg = iproc_i2c->msg;
535 uint32_t val;
536
537 /* Read valid data from RX FIFO */
538 while (iproc_i2c->rx_bytes < msg->len) {
539 val = iproc_i2c_rd_reg(iproc_i2c, M_RX_OFFSET);
540
541 /* rx fifo empty */
542 if (!((val >> M_RX_STATUS_SHIFT) & M_RX_STATUS_MASK))
543 break;
544
545 msg->buf[iproc_i2c->rx_bytes] =
546 (val >> M_RX_DATA_SHIFT) & M_RX_DATA_MASK;
547 iproc_i2c->rx_bytes++;
548 }
549 }
550
bcm_iproc_i2c_send(struct bcm_iproc_i2c_dev * iproc_i2c)551 static void bcm_iproc_i2c_send(struct bcm_iproc_i2c_dev *iproc_i2c)
552 {
553 struct i2c_msg *msg = iproc_i2c->msg;
554 unsigned int tx_bytes = msg->len - iproc_i2c->tx_bytes;
555 unsigned int i;
556 u32 val;
557
558 /* can only fill up to the FIFO size */
559 tx_bytes = min_t(unsigned int, tx_bytes, M_TX_RX_FIFO_SIZE);
560 for (i = 0; i < tx_bytes; i++) {
561 /* start from where we left over */
562 unsigned int idx = iproc_i2c->tx_bytes + i;
563
564 val = msg->buf[idx];
565
566 /* mark the last byte */
567 if (idx == msg->len - 1) {
568 val |= BIT(M_TX_WR_STATUS_SHIFT);
569
570 if (iproc_i2c->irq) {
571 u32 tmp;
572
573 /*
574 * Since this is the last byte, we should now
575 * disable TX FIFO underrun interrupt
576 */
577 tmp = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
578 tmp &= ~BIT(IE_M_TX_UNDERRUN_SHIFT);
579 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET,
580 tmp);
581 }
582 }
583
584 /* load data into TX FIFO */
585 iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, val);
586 }
587
588 /* update number of transferred bytes */
589 iproc_i2c->tx_bytes += tx_bytes;
590 }
591
bcm_iproc_i2c_read(struct bcm_iproc_i2c_dev * iproc_i2c)592 static void bcm_iproc_i2c_read(struct bcm_iproc_i2c_dev *iproc_i2c)
593 {
594 struct i2c_msg *msg = iproc_i2c->msg;
595 u32 bytes_left, val;
596
597 bcm_iproc_i2c_read_valid_bytes(iproc_i2c);
598 bytes_left = msg->len - iproc_i2c->rx_bytes;
599 if (bytes_left == 0) {
600 if (iproc_i2c->irq) {
601 /* finished reading all data, disable rx thld event */
602 val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
603 val &= ~BIT(IS_M_RX_THLD_SHIFT);
604 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
605 }
606 } else if (bytes_left < iproc_i2c->thld_bytes) {
607 /* set bytes left as threshold */
608 val = iproc_i2c_rd_reg(iproc_i2c, M_FIFO_CTRL_OFFSET);
609 val &= ~(M_FIFO_RX_THLD_MASK << M_FIFO_RX_THLD_SHIFT);
610 val |= (bytes_left << M_FIFO_RX_THLD_SHIFT);
611 iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val);
612 iproc_i2c->thld_bytes = bytes_left;
613 }
614 /*
615 * bytes_left >= iproc_i2c->thld_bytes,
616 * hence no need to change the THRESHOLD SET.
617 * It will remain as iproc_i2c->thld_bytes itself
618 */
619 }
620
bcm_iproc_i2c_process_m_event(struct bcm_iproc_i2c_dev * iproc_i2c,u32 status)621 static void bcm_iproc_i2c_process_m_event(struct bcm_iproc_i2c_dev *iproc_i2c,
622 u32 status)
623 {
624 /* TX FIFO is empty and we have more data to send */
625 if (status & BIT(IS_M_TX_UNDERRUN_SHIFT))
626 bcm_iproc_i2c_send(iproc_i2c);
627
628 /* RX FIFO threshold is reached and data needs to be read out */
629 if (status & BIT(IS_M_RX_THLD_SHIFT))
630 bcm_iproc_i2c_read(iproc_i2c);
631
632 /* transfer is done */
633 if (status & BIT(IS_M_START_BUSY_SHIFT)) {
634 iproc_i2c->xfer_is_done = 1;
635 if (iproc_i2c->irq)
636 complete(&iproc_i2c->done);
637 }
638 }
639
bcm_iproc_i2c_isr(int irq,void * data)640 static irqreturn_t bcm_iproc_i2c_isr(int irq, void *data)
641 {
642 struct bcm_iproc_i2c_dev *iproc_i2c = data;
643 u32 slave_status;
644 u32 status;
645 bool ret;
646
647 status = iproc_i2c_rd_reg(iproc_i2c, IS_OFFSET);
648 /* process only slave interrupt which are enabled */
649 slave_status = status & iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET) &
650 ISR_MASK_SLAVE;
651
652 if (slave_status) {
653 ret = bcm_iproc_i2c_slave_isr(iproc_i2c, slave_status);
654 if (ret)
655 return IRQ_HANDLED;
656 else
657 return IRQ_NONE;
658 }
659
660 status &= ISR_MASK;
661 if (!status)
662 return IRQ_NONE;
663
664 /* process all master based events */
665 bcm_iproc_i2c_process_m_event(iproc_i2c, status);
666 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, status);
667
668 return IRQ_HANDLED;
669 }
670
bcm_iproc_i2c_init(struct bcm_iproc_i2c_dev * iproc_i2c)671 static int bcm_iproc_i2c_init(struct bcm_iproc_i2c_dev *iproc_i2c)
672 {
673 u32 val;
674
675 /* put controller in reset */
676 val = iproc_i2c_rd_reg(iproc_i2c, CFG_OFFSET);
677 val |= BIT(CFG_RESET_SHIFT);
678 val &= ~(BIT(CFG_EN_SHIFT));
679 iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
680
681 /* wait 100 usec per spec */
682 udelay(100);
683
684 /* bring controller out of reset */
685 val &= ~(BIT(CFG_RESET_SHIFT));
686 iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
687
688 /* flush TX/RX FIFOs and set RX FIFO threshold to zero */
689 val = (BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT));
690 iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val);
691 /* disable all interrupts */
692 val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
693 val &= ~(IE_M_ALL_INTERRUPT_MASK <<
694 IE_M_ALL_INTERRUPT_SHIFT);
695 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
696
697 /* clear all pending interrupts */
698 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, 0xffffffff);
699
700 return 0;
701 }
702
bcm_iproc_i2c_enable_disable(struct bcm_iproc_i2c_dev * iproc_i2c,bool enable)703 static void bcm_iproc_i2c_enable_disable(struct bcm_iproc_i2c_dev *iproc_i2c,
704 bool enable)
705 {
706 u32 val;
707
708 val = iproc_i2c_rd_reg(iproc_i2c, CFG_OFFSET);
709 if (enable)
710 val |= BIT(CFG_EN_SHIFT);
711 else
712 val &= ~BIT(CFG_EN_SHIFT);
713 iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
714 }
715
bcm_iproc_i2c_check_status(struct bcm_iproc_i2c_dev * iproc_i2c,struct i2c_msg * msg)716 static int bcm_iproc_i2c_check_status(struct bcm_iproc_i2c_dev *iproc_i2c,
717 struct i2c_msg *msg)
718 {
719 u32 val;
720
721 val = iproc_i2c_rd_reg(iproc_i2c, M_CMD_OFFSET);
722 val = (val >> M_CMD_STATUS_SHIFT) & M_CMD_STATUS_MASK;
723
724 switch (val) {
725 case M_CMD_STATUS_SUCCESS:
726 return 0;
727
728 case M_CMD_STATUS_LOST_ARB:
729 dev_dbg(iproc_i2c->device, "lost bus arbitration\n");
730 return -EAGAIN;
731
732 case M_CMD_STATUS_NACK_ADDR:
733 dev_dbg(iproc_i2c->device, "NAK addr:0x%02x\n", msg->addr);
734 return -ENXIO;
735
736 case M_CMD_STATUS_NACK_DATA:
737 dev_dbg(iproc_i2c->device, "NAK data\n");
738 return -ENXIO;
739
740 case M_CMD_STATUS_TIMEOUT:
741 dev_dbg(iproc_i2c->device, "bus timeout\n");
742 return -ETIMEDOUT;
743
744 case M_CMD_STATUS_FIFO_UNDERRUN:
745 dev_dbg(iproc_i2c->device, "FIFO under-run\n");
746 return -ENXIO;
747
748 case M_CMD_STATUS_RX_FIFO_FULL:
749 dev_dbg(iproc_i2c->device, "RX FIFO full\n");
750 return -ETIMEDOUT;
751
752 default:
753 dev_dbg(iproc_i2c->device, "unknown error code=%d\n", val);
754
755 /* re-initialize i2c for recovery */
756 bcm_iproc_i2c_enable_disable(iproc_i2c, false);
757 bcm_iproc_i2c_init(iproc_i2c);
758 bcm_iproc_i2c_enable_disable(iproc_i2c, true);
759
760 return -EIO;
761 }
762 }
763
bcm_iproc_i2c_xfer_wait(struct bcm_iproc_i2c_dev * iproc_i2c,struct i2c_msg * msg,u32 cmd)764 static int bcm_iproc_i2c_xfer_wait(struct bcm_iproc_i2c_dev *iproc_i2c,
765 struct i2c_msg *msg,
766 u32 cmd)
767 {
768 unsigned long time_left = msecs_to_jiffies(I2C_TIMEOUT_MSEC);
769 u32 val, status;
770 int ret;
771
772 iproc_i2c_wr_reg(iproc_i2c, M_CMD_OFFSET, cmd);
773
774 if (iproc_i2c->irq) {
775 time_left = wait_for_completion_timeout(&iproc_i2c->done,
776 time_left);
777 /* disable all interrupts */
778 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, 0);
779 /* read it back to flush the write */
780 iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
781 /* make sure the interrupt handler isn't running */
782 synchronize_irq(iproc_i2c->irq);
783
784 } else { /* polling mode */
785 unsigned long timeout = jiffies + time_left;
786
787 do {
788 status = iproc_i2c_rd_reg(iproc_i2c,
789 IS_OFFSET) & ISR_MASK;
790 bcm_iproc_i2c_process_m_event(iproc_i2c, status);
791 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, status);
792
793 if (time_after(jiffies, timeout)) {
794 time_left = 0;
795 break;
796 }
797
798 cpu_relax();
799 cond_resched();
800 } while (!iproc_i2c->xfer_is_done);
801 }
802
803 if (!time_left && !iproc_i2c->xfer_is_done) {
804 dev_err(iproc_i2c->device, "transaction timed out\n");
805
806 /* flush both TX/RX FIFOs */
807 val = BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT);
808 iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val);
809 return -ETIMEDOUT;
810 }
811
812 ret = bcm_iproc_i2c_check_status(iproc_i2c, msg);
813 if (ret) {
814 /* flush both TX/RX FIFOs */
815 val = BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT);
816 iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val);
817 return ret;
818 }
819
820 return 0;
821 }
822
823 /*
824 * If 'process_call' is true, then this is a multi-msg transfer that requires
825 * a repeated start between the messages.
826 * More specifically, it must be a write (reg) followed by a read (data).
827 * The i2c quirks are set to enforce this rule.
828 */
bcm_iproc_i2c_xfer_internal(struct bcm_iproc_i2c_dev * iproc_i2c,struct i2c_msg * msgs,bool process_call)829 static int bcm_iproc_i2c_xfer_internal(struct bcm_iproc_i2c_dev *iproc_i2c,
830 struct i2c_msg *msgs, bool process_call)
831 {
832 int i;
833 u8 addr;
834 u32 val, tmp, val_intr_en;
835 unsigned int tx_bytes;
836 struct i2c_msg *msg = &msgs[0];
837
838 /* check if bus is busy */
839 if (!!(iproc_i2c_rd_reg(iproc_i2c,
840 M_CMD_OFFSET) & BIT(M_CMD_START_BUSY_SHIFT))) {
841 dev_warn(iproc_i2c->device, "bus is busy\n");
842 return -EBUSY;
843 }
844
845 iproc_i2c->msg = msg;
846
847 /* format and load slave address into the TX FIFO */
848 addr = i2c_8bit_addr_from_msg(msg);
849 iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, addr);
850
851 /*
852 * For a write transaction, load data into the TX FIFO. Only allow
853 * loading up to TX FIFO size - 1 bytes of data since the first byte
854 * has been used up by the slave address
855 */
856 tx_bytes = min_t(unsigned int, msg->len, M_TX_RX_FIFO_SIZE - 1);
857 if (!(msg->flags & I2C_M_RD)) {
858 for (i = 0; i < tx_bytes; i++) {
859 val = msg->buf[i];
860
861 /* mark the last byte */
862 if (!process_call && (i == msg->len - 1))
863 val |= BIT(M_TX_WR_STATUS_SHIFT);
864
865 iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, val);
866 }
867 iproc_i2c->tx_bytes = tx_bytes;
868 }
869
870 /* Process the read message if this is process call */
871 if (process_call) {
872 msg++;
873 iproc_i2c->msg = msg; /* point to second msg */
874
875 /*
876 * The last byte to be sent out should be a slave
877 * address with read operation
878 */
879 addr = i2c_8bit_addr_from_msg(msg);
880 /* mark it the last byte out */
881 val = addr | BIT(M_TX_WR_STATUS_SHIFT);
882 iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, val);
883 }
884
885 /* mark as incomplete before starting the transaction */
886 if (iproc_i2c->irq)
887 reinit_completion(&iproc_i2c->done);
888
889 iproc_i2c->xfer_is_done = 0;
890
891 /*
892 * Enable the "start busy" interrupt, which will be triggered after the
893 * transaction is done, i.e., the internal start_busy bit, transitions
894 * from 1 to 0.
895 */
896 val_intr_en = BIT(IE_M_START_BUSY_SHIFT);
897
898 /*
899 * If TX data size is larger than the TX FIFO, need to enable TX
900 * underrun interrupt, which will be triggerred when the TX FIFO is
901 * empty. When that happens we can then pump more data into the FIFO
902 */
903 if (!process_call && !(msg->flags & I2C_M_RD) &&
904 msg->len > iproc_i2c->tx_bytes)
905 val_intr_en |= BIT(IE_M_TX_UNDERRUN_SHIFT);
906
907 /*
908 * Now we can activate the transfer. For a read operation, specify the
909 * number of bytes to read
910 */
911 val = BIT(M_CMD_START_BUSY_SHIFT);
912
913 if (msg->len == 0) {
914 /* SMBUS QUICK Command (Read/Write) */
915 val |= (M_CMD_PROTOCOL_QUICK << M_CMD_PROTOCOL_SHIFT);
916 } else if (msg->flags & I2C_M_RD) {
917 u32 protocol;
918
919 iproc_i2c->rx_bytes = 0;
920 if (msg->len > M_RX_FIFO_MAX_THLD_VALUE)
921 iproc_i2c->thld_bytes = M_RX_FIFO_THLD_VALUE;
922 else
923 iproc_i2c->thld_bytes = msg->len;
924
925 /* set threshold value */
926 tmp = iproc_i2c_rd_reg(iproc_i2c, M_FIFO_CTRL_OFFSET);
927 tmp &= ~(M_FIFO_RX_THLD_MASK << M_FIFO_RX_THLD_SHIFT);
928 tmp |= iproc_i2c->thld_bytes << M_FIFO_RX_THLD_SHIFT;
929 iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, tmp);
930
931 /* enable the RX threshold interrupt */
932 val_intr_en |= BIT(IE_M_RX_THLD_SHIFT);
933
934 protocol = process_call ?
935 M_CMD_PROTOCOL_PROCESS : M_CMD_PROTOCOL_BLK_RD;
936
937 val |= (protocol << M_CMD_PROTOCOL_SHIFT) |
938 (msg->len << M_CMD_RD_CNT_SHIFT);
939 } else {
940 val |= (M_CMD_PROTOCOL_BLK_WR << M_CMD_PROTOCOL_SHIFT);
941 }
942
943 if (iproc_i2c->irq)
944 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val_intr_en);
945
946 return bcm_iproc_i2c_xfer_wait(iproc_i2c, msg, val);
947 }
948
bcm_iproc_i2c_xfer(struct i2c_adapter * adapter,struct i2c_msg msgs[],int num)949 static int bcm_iproc_i2c_xfer(struct i2c_adapter *adapter,
950 struct i2c_msg msgs[], int num)
951 {
952 struct bcm_iproc_i2c_dev *iproc_i2c = i2c_get_adapdata(adapter);
953 bool process_call = false;
954 int ret;
955
956 if (num == 2) {
957 /* Repeated start, use process call */
958 process_call = true;
959 if (msgs[1].flags & I2C_M_NOSTART) {
960 dev_err(iproc_i2c->device, "Invalid repeated start\n");
961 return -EOPNOTSUPP;
962 }
963 }
964
965 ret = bcm_iproc_i2c_xfer_internal(iproc_i2c, msgs, process_call);
966 if (ret) {
967 dev_dbg(iproc_i2c->device, "xfer failed\n");
968 return ret;
969 }
970
971 return num;
972 }
973
bcm_iproc_i2c_functionality(struct i2c_adapter * adap)974 static uint32_t bcm_iproc_i2c_functionality(struct i2c_adapter *adap)
975 {
976 u32 val;
977
978 val = I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
979
980 if (adap->algo->reg_slave)
981 val |= I2C_FUNC_SLAVE;
982
983 return val;
984 }
985
986 static struct i2c_algorithm bcm_iproc_algo = {
987 .master_xfer = bcm_iproc_i2c_xfer,
988 .functionality = bcm_iproc_i2c_functionality,
989 .reg_slave = bcm_iproc_i2c_reg_slave,
990 .unreg_slave = bcm_iproc_i2c_unreg_slave,
991 };
992
993 static const struct i2c_adapter_quirks bcm_iproc_i2c_quirks = {
994 .flags = I2C_AQ_COMB_WRITE_THEN_READ,
995 .max_comb_1st_msg_len = M_TX_RX_FIFO_SIZE,
996 .max_read_len = M_RX_MAX_READ_LEN,
997 };
998
bcm_iproc_i2c_cfg_speed(struct bcm_iproc_i2c_dev * iproc_i2c)999 static int bcm_iproc_i2c_cfg_speed(struct bcm_iproc_i2c_dev *iproc_i2c)
1000 {
1001 unsigned int bus_speed;
1002 u32 val;
1003 int ret = of_property_read_u32(iproc_i2c->device->of_node,
1004 "clock-frequency", &bus_speed);
1005 if (ret < 0) {
1006 dev_info(iproc_i2c->device,
1007 "unable to interpret clock-frequency DT property\n");
1008 bus_speed = I2C_MAX_STANDARD_MODE_FREQ;
1009 }
1010
1011 if (bus_speed < I2C_MAX_STANDARD_MODE_FREQ) {
1012 dev_err(iproc_i2c->device, "%d Hz bus speed not supported\n",
1013 bus_speed);
1014 dev_err(iproc_i2c->device,
1015 "valid speeds are 100khz and 400khz\n");
1016 return -EINVAL;
1017 } else if (bus_speed < I2C_MAX_FAST_MODE_FREQ) {
1018 bus_speed = I2C_MAX_STANDARD_MODE_FREQ;
1019 } else {
1020 bus_speed = I2C_MAX_FAST_MODE_FREQ;
1021 }
1022
1023 iproc_i2c->bus_speed = bus_speed;
1024 val = iproc_i2c_rd_reg(iproc_i2c, TIM_CFG_OFFSET);
1025 val &= ~BIT(TIM_CFG_MODE_400_SHIFT);
1026 val |= (bus_speed == I2C_MAX_FAST_MODE_FREQ) << TIM_CFG_MODE_400_SHIFT;
1027 iproc_i2c_wr_reg(iproc_i2c, TIM_CFG_OFFSET, val);
1028
1029 dev_info(iproc_i2c->device, "bus set to %u Hz\n", bus_speed);
1030
1031 return 0;
1032 }
1033
bcm_iproc_i2c_probe(struct platform_device * pdev)1034 static int bcm_iproc_i2c_probe(struct platform_device *pdev)
1035 {
1036 int irq, ret = 0;
1037 struct bcm_iproc_i2c_dev *iproc_i2c;
1038 struct i2c_adapter *adap;
1039 struct resource *res;
1040
1041 iproc_i2c = devm_kzalloc(&pdev->dev, sizeof(*iproc_i2c),
1042 GFP_KERNEL);
1043 if (!iproc_i2c)
1044 return -ENOMEM;
1045
1046 platform_set_drvdata(pdev, iproc_i2c);
1047 iproc_i2c->device = &pdev->dev;
1048 iproc_i2c->type =
1049 (enum bcm_iproc_i2c_type)of_device_get_match_data(&pdev->dev);
1050 init_completion(&iproc_i2c->done);
1051
1052 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1053 iproc_i2c->base = devm_ioremap_resource(iproc_i2c->device, res);
1054 if (IS_ERR(iproc_i2c->base))
1055 return PTR_ERR(iproc_i2c->base);
1056
1057 if (iproc_i2c->type == IPROC_I2C_NIC) {
1058 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1059 iproc_i2c->idm_base = devm_ioremap_resource(iproc_i2c->device,
1060 res);
1061 if (IS_ERR(iproc_i2c->idm_base))
1062 return PTR_ERR(iproc_i2c->idm_base);
1063
1064 ret = of_property_read_u32(iproc_i2c->device->of_node,
1065 "brcm,ape-hsls-addr-mask",
1066 &iproc_i2c->ape_addr_mask);
1067 if (ret < 0) {
1068 dev_err(iproc_i2c->device,
1069 "'brcm,ape-hsls-addr-mask' missing\n");
1070 return -EINVAL;
1071 }
1072
1073 spin_lock_init(&iproc_i2c->idm_lock);
1074
1075 /* no slave support */
1076 bcm_iproc_algo.reg_slave = NULL;
1077 bcm_iproc_algo.unreg_slave = NULL;
1078 }
1079
1080 ret = bcm_iproc_i2c_init(iproc_i2c);
1081 if (ret)
1082 return ret;
1083
1084 ret = bcm_iproc_i2c_cfg_speed(iproc_i2c);
1085 if (ret)
1086 return ret;
1087
1088 irq = platform_get_irq(pdev, 0);
1089 if (irq > 0) {
1090 ret = devm_request_irq(iproc_i2c->device, irq,
1091 bcm_iproc_i2c_isr, 0, pdev->name,
1092 iproc_i2c);
1093 if (ret < 0) {
1094 dev_err(iproc_i2c->device,
1095 "unable to request irq %i\n", irq);
1096 return ret;
1097 }
1098
1099 iproc_i2c->irq = irq;
1100 } else {
1101 dev_warn(iproc_i2c->device,
1102 "no irq resource, falling back to poll mode\n");
1103 }
1104
1105 bcm_iproc_i2c_enable_disable(iproc_i2c, true);
1106
1107 adap = &iproc_i2c->adapter;
1108 i2c_set_adapdata(adap, iproc_i2c);
1109 snprintf(adap->name, sizeof(adap->name),
1110 "Broadcom iProc (%s)",
1111 of_node_full_name(iproc_i2c->device->of_node));
1112 adap->algo = &bcm_iproc_algo;
1113 adap->quirks = &bcm_iproc_i2c_quirks;
1114 adap->dev.parent = &pdev->dev;
1115 adap->dev.of_node = pdev->dev.of_node;
1116
1117 return i2c_add_adapter(adap);
1118 }
1119
bcm_iproc_i2c_remove(struct platform_device * pdev)1120 static int bcm_iproc_i2c_remove(struct platform_device *pdev)
1121 {
1122 struct bcm_iproc_i2c_dev *iproc_i2c = platform_get_drvdata(pdev);
1123
1124 if (iproc_i2c->irq) {
1125 /*
1126 * Make sure there's no pending interrupt when we remove the
1127 * adapter
1128 */
1129 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, 0);
1130 iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
1131 synchronize_irq(iproc_i2c->irq);
1132 }
1133
1134 i2c_del_adapter(&iproc_i2c->adapter);
1135 bcm_iproc_i2c_enable_disable(iproc_i2c, false);
1136
1137 return 0;
1138 }
1139
1140 #ifdef CONFIG_PM_SLEEP
1141
bcm_iproc_i2c_suspend(struct device * dev)1142 static int bcm_iproc_i2c_suspend(struct device *dev)
1143 {
1144 struct bcm_iproc_i2c_dev *iproc_i2c = dev_get_drvdata(dev);
1145
1146 if (iproc_i2c->irq) {
1147 /*
1148 * Make sure there's no pending interrupt when we go into
1149 * suspend
1150 */
1151 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, 0);
1152 iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
1153 synchronize_irq(iproc_i2c->irq);
1154 }
1155
1156 /* now disable the controller */
1157 bcm_iproc_i2c_enable_disable(iproc_i2c, false);
1158
1159 return 0;
1160 }
1161
bcm_iproc_i2c_resume(struct device * dev)1162 static int bcm_iproc_i2c_resume(struct device *dev)
1163 {
1164 struct bcm_iproc_i2c_dev *iproc_i2c = dev_get_drvdata(dev);
1165 int ret;
1166 u32 val;
1167
1168 /*
1169 * Power domain could have been shut off completely in system deep
1170 * sleep, so re-initialize the block here
1171 */
1172 ret = bcm_iproc_i2c_init(iproc_i2c);
1173 if (ret)
1174 return ret;
1175
1176 /* configure to the desired bus speed */
1177 val = iproc_i2c_rd_reg(iproc_i2c, TIM_CFG_OFFSET);
1178 val &= ~BIT(TIM_CFG_MODE_400_SHIFT);
1179 val |= (iproc_i2c->bus_speed == I2C_MAX_FAST_MODE_FREQ) << TIM_CFG_MODE_400_SHIFT;
1180 iproc_i2c_wr_reg(iproc_i2c, TIM_CFG_OFFSET, val);
1181
1182 bcm_iproc_i2c_enable_disable(iproc_i2c, true);
1183
1184 return 0;
1185 }
1186
1187 static const struct dev_pm_ops bcm_iproc_i2c_pm_ops = {
1188 .suspend_late = &bcm_iproc_i2c_suspend,
1189 .resume_early = &bcm_iproc_i2c_resume
1190 };
1191
1192 #define BCM_IPROC_I2C_PM_OPS (&bcm_iproc_i2c_pm_ops)
1193 #else
1194 #define BCM_IPROC_I2C_PM_OPS NULL
1195 #endif /* CONFIG_PM_SLEEP */
1196
1197
bcm_iproc_i2c_reg_slave(struct i2c_client * slave)1198 static int bcm_iproc_i2c_reg_slave(struct i2c_client *slave)
1199 {
1200 struct bcm_iproc_i2c_dev *iproc_i2c = i2c_get_adapdata(slave->adapter);
1201
1202 if (iproc_i2c->slave)
1203 return -EBUSY;
1204
1205 if (slave->flags & I2C_CLIENT_TEN)
1206 return -EAFNOSUPPORT;
1207
1208 iproc_i2c->slave = slave;
1209
1210 tasklet_init(&iproc_i2c->slave_rx_tasklet, slave_rx_tasklet_fn,
1211 (unsigned long)iproc_i2c);
1212
1213 bcm_iproc_i2c_slave_init(iproc_i2c, false);
1214 return 0;
1215 }
1216
bcm_iproc_i2c_unreg_slave(struct i2c_client * slave)1217 static int bcm_iproc_i2c_unreg_slave(struct i2c_client *slave)
1218 {
1219 u32 tmp;
1220 struct bcm_iproc_i2c_dev *iproc_i2c = i2c_get_adapdata(slave->adapter);
1221
1222 if (!iproc_i2c->slave)
1223 return -EINVAL;
1224
1225 disable_irq(iproc_i2c->irq);
1226
1227 tasklet_kill(&iproc_i2c->slave_rx_tasklet);
1228
1229 /* disable all slave interrupts */
1230 tmp = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
1231 tmp &= ~(IE_S_ALL_INTERRUPT_MASK <<
1232 IE_S_ALL_INTERRUPT_SHIFT);
1233 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, tmp);
1234
1235 /* Erase the slave address programmed */
1236 tmp = iproc_i2c_rd_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET);
1237 tmp &= ~BIT(S_CFG_EN_NIC_SMB_ADDR3_SHIFT);
1238 iproc_i2c_wr_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET, tmp);
1239
1240 /* flush TX/RX FIFOs */
1241 tmp = (BIT(S_FIFO_RX_FLUSH_SHIFT) | BIT(S_FIFO_TX_FLUSH_SHIFT));
1242 iproc_i2c_wr_reg(iproc_i2c, S_FIFO_CTRL_OFFSET, tmp);
1243
1244 /* clear all pending slave interrupts */
1245 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, ISR_MASK_SLAVE);
1246
1247 iproc_i2c->slave = NULL;
1248
1249 enable_irq(iproc_i2c->irq);
1250
1251 return 0;
1252 }
1253
1254 static const struct of_device_id bcm_iproc_i2c_of_match[] = {
1255 {
1256 .compatible = "brcm,iproc-i2c",
1257 .data = (int *)IPROC_I2C,
1258 }, {
1259 .compatible = "brcm,iproc-nic-i2c",
1260 .data = (int *)IPROC_I2C_NIC,
1261 },
1262 { /* sentinel */ }
1263 };
1264 MODULE_DEVICE_TABLE(of, bcm_iproc_i2c_of_match);
1265
1266 static struct platform_driver bcm_iproc_i2c_driver = {
1267 .driver = {
1268 .name = "bcm-iproc-i2c",
1269 .of_match_table = bcm_iproc_i2c_of_match,
1270 .pm = BCM_IPROC_I2C_PM_OPS,
1271 },
1272 .probe = bcm_iproc_i2c_probe,
1273 .remove = bcm_iproc_i2c_remove,
1274 };
1275 module_platform_driver(bcm_iproc_i2c_driver);
1276
1277 MODULE_AUTHOR("Ray Jui <rjui@broadcom.com>");
1278 MODULE_DESCRIPTION("Broadcom iProc I2C Driver");
1279 MODULE_LICENSE("GPL v2");
1280