1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>,
4 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
5 <mdsxyz123@yahoo.com>
6 Copyright (C) 2007 - 2014 Jean Delvare <jdelvare@suse.de>
7 Copyright (C) 2010 Intel Corporation,
8 David Woodhouse <dwmw2@infradead.org>
9
10 */
11
12 /*
13 * Supports the following Intel I/O Controller Hubs (ICH):
14 *
15 * I/O Block I2C
16 * region SMBus Block proc. block
17 * Chip name PCI ID size PEC buffer call read
18 * ---------------------------------------------------------------------------
19 * 82801AA (ICH) 0x2413 16 no no no no
20 * 82801AB (ICH0) 0x2423 16 no no no no
21 * 82801BA (ICH2) 0x2443 16 no no no no
22 * 82801CA (ICH3) 0x2483 32 soft no no no
23 * 82801DB (ICH4) 0x24c3 32 hard yes no no
24 * 82801E (ICH5) 0x24d3 32 hard yes yes yes
25 * 6300ESB 0x25a4 32 hard yes yes yes
26 * 82801F (ICH6) 0x266a 32 hard yes yes yes
27 * 6310ESB/6320ESB 0x269b 32 hard yes yes yes
28 * 82801G (ICH7) 0x27da 32 hard yes yes yes
29 * 82801H (ICH8) 0x283e 32 hard yes yes yes
30 * 82801I (ICH9) 0x2930 32 hard yes yes yes
31 * EP80579 (Tolapai) 0x5032 32 hard yes yes yes
32 * ICH10 0x3a30 32 hard yes yes yes
33 * ICH10 0x3a60 32 hard yes yes yes
34 * 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes
35 * 6 Series (PCH) 0x1c22 32 hard yes yes yes
36 * Patsburg (PCH) 0x1d22 32 hard yes yes yes
37 * Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes
38 * Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes
39 * Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes
40 * DH89xxCC (PCH) 0x2330 32 hard yes yes yes
41 * Panther Point (PCH) 0x1e22 32 hard yes yes yes
42 * Lynx Point (PCH) 0x8c22 32 hard yes yes yes
43 * Lynx Point-LP (PCH) 0x9c22 32 hard yes yes yes
44 * Avoton (SOC) 0x1f3c 32 hard yes yes yes
45 * Wellsburg (PCH) 0x8d22 32 hard yes yes yes
46 * Wellsburg (PCH) MS 0x8d7d 32 hard yes yes yes
47 * Wellsburg (PCH) MS 0x8d7e 32 hard yes yes yes
48 * Wellsburg (PCH) MS 0x8d7f 32 hard yes yes yes
49 * Coleto Creek (PCH) 0x23b0 32 hard yes yes yes
50 * Wildcat Point (PCH) 0x8ca2 32 hard yes yes yes
51 * Wildcat Point-LP (PCH) 0x9ca2 32 hard yes yes yes
52 * BayTrail (SOC) 0x0f12 32 hard yes yes yes
53 * Braswell (SOC) 0x2292 32 hard yes yes yes
54 * Sunrise Point-H (PCH) 0xa123 32 hard yes yes yes
55 * Sunrise Point-LP (PCH) 0x9d23 32 hard yes yes yes
56 * DNV (SOC) 0x19df 32 hard yes yes yes
57 * Emmitsburg (PCH) 0x1bc9 32 hard yes yes yes
58 * Broxton (SOC) 0x5ad4 32 hard yes yes yes
59 * Lewisburg (PCH) 0xa1a3 32 hard yes yes yes
60 * Lewisburg Supersku (PCH) 0xa223 32 hard yes yes yes
61 * Kaby Lake PCH-H (PCH) 0xa2a3 32 hard yes yes yes
62 * Gemini Lake (SOC) 0x31d4 32 hard yes yes yes
63 * Cannon Lake-H (PCH) 0xa323 32 hard yes yes yes
64 * Cannon Lake-LP (PCH) 0x9da3 32 hard yes yes yes
65 * Cedar Fork (PCH) 0x18df 32 hard yes yes yes
66 * Ice Lake-LP (PCH) 0x34a3 32 hard yes yes yes
67 * Ice Lake-N (PCH) 0x38a3 32 hard yes yes yes
68 * Comet Lake (PCH) 0x02a3 32 hard yes yes yes
69 * Comet Lake-H (PCH) 0x06a3 32 hard yes yes yes
70 * Elkhart Lake (PCH) 0x4b23 32 hard yes yes yes
71 * Tiger Lake-LP (PCH) 0xa0a3 32 hard yes yes yes
72 * Tiger Lake-H (PCH) 0x43a3 32 hard yes yes yes
73 * Jasper Lake (SOC) 0x4da3 32 hard yes yes yes
74 * Comet Lake-V (PCH) 0xa3a3 32 hard yes yes yes
75 * Alder Lake-S (PCH) 0x7aa3 32 hard yes yes yes
76 * Alder Lake-P (PCH) 0x51a3 32 hard yes yes yes
77 * Alder Lake-M (PCH) 0x54a3 32 hard yes yes yes
78 *
79 * Features supported by this driver:
80 * Software PEC no
81 * Hardware PEC yes
82 * Block buffer yes
83 * Block process call transaction yes
84 * I2C block read transaction yes (doesn't use the block buffer)
85 * Slave mode no
86 * SMBus Host Notify yes
87 * Interrupt processing yes
88 *
89 * See the file Documentation/i2c/busses/i2c-i801.rst for details.
90 */
91
92 #define DRV_NAME "i801_smbus"
93
94 #include <linux/interrupt.h>
95 #include <linux/module.h>
96 #include <linux/pci.h>
97 #include <linux/kernel.h>
98 #include <linux/stddef.h>
99 #include <linux/delay.h>
100 #include <linux/ioport.h>
101 #include <linux/init.h>
102 #include <linux/i2c.h>
103 #include <linux/i2c-smbus.h>
104 #include <linux/acpi.h>
105 #include <linux/io.h>
106 #include <linux/dmi.h>
107 #include <linux/slab.h>
108 #include <linux/string.h>
109 #include <linux/completion.h>
110 #include <linux/err.h>
111 #include <linux/platform_device.h>
112 #include <linux/platform_data/itco_wdt.h>
113 #include <linux/pm_runtime.h>
114 #include <linux/mutex.h>
115
116 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
117 #include <linux/gpio/machine.h>
118 #include <linux/platform_data/i2c-mux-gpio.h>
119 #endif
120
121 /* I801 SMBus address offsets */
122 #define SMBHSTSTS(p) (0 + (p)->smba)
123 #define SMBHSTCNT(p) (2 + (p)->smba)
124 #define SMBHSTCMD(p) (3 + (p)->smba)
125 #define SMBHSTADD(p) (4 + (p)->smba)
126 #define SMBHSTDAT0(p) (5 + (p)->smba)
127 #define SMBHSTDAT1(p) (6 + (p)->smba)
128 #define SMBBLKDAT(p) (7 + (p)->smba)
129 #define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */
130 #define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */
131 #define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */
132 #define SMBSLVSTS(p) (16 + (p)->smba) /* ICH3 and later */
133 #define SMBSLVCMD(p) (17 + (p)->smba) /* ICH3 and later */
134 #define SMBNTFDADD(p) (20 + (p)->smba) /* ICH3 and later */
135
136 /* PCI Address Constants */
137 #define SMBBAR 4
138 #define SMBHSTCFG 0x040
139 #define TCOBASE 0x050
140 #define TCOCTL 0x054
141
142 #define SBREG_BAR 0x10
143 #define SBREG_SMBCTRL 0xc6000c
144 #define SBREG_SMBCTRL_DNV 0xcf000c
145
146 /* Host configuration bits for SMBHSTCFG */
147 #define SMBHSTCFG_HST_EN BIT(0)
148 #define SMBHSTCFG_SMB_SMI_EN BIT(1)
149 #define SMBHSTCFG_I2C_EN BIT(2)
150 #define SMBHSTCFG_SPD_WD BIT(4)
151
152 /* TCO configuration bits for TCOCTL */
153 #define TCOCTL_EN BIT(8)
154
155 /* Auxiliary status register bits, ICH4+ only */
156 #define SMBAUXSTS_CRCE BIT(0)
157 #define SMBAUXSTS_STCO BIT(1)
158
159 /* Auxiliary control register bits, ICH4+ only */
160 #define SMBAUXCTL_CRC BIT(0)
161 #define SMBAUXCTL_E32B BIT(1)
162
163 /* I801 command constants */
164 #define I801_QUICK 0x00
165 #define I801_BYTE 0x04
166 #define I801_BYTE_DATA 0x08
167 #define I801_WORD_DATA 0x0C
168 #define I801_PROC_CALL 0x10 /* unimplemented */
169 #define I801_BLOCK_DATA 0x14
170 #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */
171 #define I801_BLOCK_PROC_CALL 0x1C
172
173 /* I801 Host Control register bits */
174 #define SMBHSTCNT_INTREN BIT(0)
175 #define SMBHSTCNT_KILL BIT(1)
176 #define SMBHSTCNT_LAST_BYTE BIT(5)
177 #define SMBHSTCNT_START BIT(6)
178 #define SMBHSTCNT_PEC_EN BIT(7) /* ICH3 and later */
179
180 /* I801 Hosts Status register bits */
181 #define SMBHSTSTS_BYTE_DONE BIT(7)
182 #define SMBHSTSTS_INUSE_STS BIT(6)
183 #define SMBHSTSTS_SMBALERT_STS BIT(5)
184 #define SMBHSTSTS_FAILED BIT(4)
185 #define SMBHSTSTS_BUS_ERR BIT(3)
186 #define SMBHSTSTS_DEV_ERR BIT(2)
187 #define SMBHSTSTS_INTR BIT(1)
188 #define SMBHSTSTS_HOST_BUSY BIT(0)
189
190 /* Host Notify Status register bits */
191 #define SMBSLVSTS_HST_NTFY_STS BIT(0)
192
193 /* Host Notify Command register bits */
194 #define SMBSLVCMD_SMBALERT_DISABLE BIT(2)
195 #define SMBSLVCMD_HST_NTFY_INTREN BIT(0)
196
197 #define STATUS_ERROR_FLAGS (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \
198 SMBHSTSTS_DEV_ERR)
199
200 #define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \
201 STATUS_ERROR_FLAGS)
202
203 /* Older devices have their ID defined in <linux/pci_ids.h> */
204 #define PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS 0x02a3
205 #define PCI_DEVICE_ID_INTEL_COMETLAKE_H_SMBUS 0x06a3
206 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS 0x0f12
207 #define PCI_DEVICE_ID_INTEL_CDF_SMBUS 0x18df
208 #define PCI_DEVICE_ID_INTEL_DNV_SMBUS 0x19df
209 #define PCI_DEVICE_ID_INTEL_EBG_SMBUS 0x1bc9
210 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22
211 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22
212 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */
213 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70
214 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71
215 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72
216 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22
217 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS 0x1f3c
218 #define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS 0x2292
219 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330
220 #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS 0x23b0
221 #define PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS 0x31d4
222 #define PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS 0x34a3
223 #define PCI_DEVICE_ID_INTEL_ICELAKE_N_SMBUS 0x38a3
224 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30
225 #define PCI_DEVICE_ID_INTEL_TIGERLAKE_H_SMBUS 0x43a3
226 #define PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS 0x4b23
227 #define PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS 0x4da3
228 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_P_SMBUS 0x51a3
229 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_M_SMBUS 0x54a3
230 #define PCI_DEVICE_ID_INTEL_BROXTON_SMBUS 0x5ad4
231 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_S_SMBUS 0x7aa3
232 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22
233 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS 0x8ca2
234 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS 0x8d22
235 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0 0x8d7d
236 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1 0x8d7e
237 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2 0x8d7f
238 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS 0x9c22
239 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS 0x9ca2
240 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS 0x9d23
241 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS 0x9da3
242 #define PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS 0xa0a3
243 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS 0xa123
244 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS 0xa1a3
245 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS 0xa223
246 #define PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS 0xa2a3
247 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS 0xa323
248 #define PCI_DEVICE_ID_INTEL_COMETLAKE_V_SMBUS 0xa3a3
249
250 struct i801_mux_config {
251 char *gpio_chip;
252 unsigned values[3];
253 int n_values;
254 unsigned classes[3];
255 unsigned gpios[2]; /* Relative to gpio_chip->base */
256 int n_gpios;
257 };
258
259 struct i801_priv {
260 struct i2c_adapter adapter;
261 unsigned long smba;
262 unsigned char original_hstcfg;
263 unsigned char original_hstcnt;
264 unsigned char original_slvcmd;
265 struct pci_dev *pci_dev;
266 unsigned int features;
267
268 /* isr processing */
269 struct completion done;
270 u8 status;
271
272 /* Command state used by isr for byte-by-byte block transactions */
273 u8 cmd;
274 bool is_read;
275 int count;
276 int len;
277 u8 *data;
278
279 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
280 const struct i801_mux_config *mux_drvdata;
281 struct platform_device *mux_pdev;
282 struct gpiod_lookup_table *lookup;
283 #endif
284 struct platform_device *tco_pdev;
285
286 /*
287 * If set to true the host controller registers are reserved for
288 * ACPI AML use. Protected by acpi_lock.
289 */
290 bool acpi_reserved;
291 struct mutex acpi_lock;
292 };
293
294 #define FEATURE_SMBUS_PEC BIT(0)
295 #define FEATURE_BLOCK_BUFFER BIT(1)
296 #define FEATURE_BLOCK_PROC BIT(2)
297 #define FEATURE_I2C_BLOCK_READ BIT(3)
298 #define FEATURE_IRQ BIT(4)
299 #define FEATURE_HOST_NOTIFY BIT(5)
300 /* Not really a feature, but it's convenient to handle it as such */
301 #define FEATURE_IDF BIT(15)
302 #define FEATURE_TCO_SPT BIT(16)
303 #define FEATURE_TCO_CNL BIT(17)
304
305 static const char *i801_feature_names[] = {
306 "SMBus PEC",
307 "Block buffer",
308 "Block process call",
309 "I2C block read",
310 "Interrupt",
311 "SMBus Host Notify",
312 };
313
314 static unsigned int disable_features;
315 module_param(disable_features, uint, S_IRUGO | S_IWUSR);
316 MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n"
317 "\t\t 0x01 disable SMBus PEC\n"
318 "\t\t 0x02 disable the block buffer\n"
319 "\t\t 0x08 disable the I2C block read functionality\n"
320 "\t\t 0x10 don't use interrupts\n"
321 "\t\t 0x20 disable SMBus Host Notify ");
322
323 /* Make sure the SMBus host is ready to start transmitting.
324 Return 0 if it is, -EBUSY if it is not. */
i801_check_pre(struct i801_priv * priv)325 static int i801_check_pre(struct i801_priv *priv)
326 {
327 int status;
328
329 status = inb_p(SMBHSTSTS(priv));
330 if (status & SMBHSTSTS_HOST_BUSY) {
331 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n");
332 return -EBUSY;
333 }
334
335 status &= STATUS_FLAGS;
336 if (status) {
337 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n",
338 status);
339 outb_p(status, SMBHSTSTS(priv));
340 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
341 if (status) {
342 dev_err(&priv->pci_dev->dev,
343 "Failed clearing status flags (%02x)\n",
344 status);
345 return -EBUSY;
346 }
347 }
348
349 /*
350 * Clear CRC status if needed.
351 * During normal operation, i801_check_post() takes care
352 * of it after every operation. We do it here only in case
353 * the hardware was already in this state when the driver
354 * started.
355 */
356 if (priv->features & FEATURE_SMBUS_PEC) {
357 status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE;
358 if (status) {
359 dev_dbg(&priv->pci_dev->dev,
360 "Clearing aux status flags (%02x)\n", status);
361 outb_p(status, SMBAUXSTS(priv));
362 status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE;
363 if (status) {
364 dev_err(&priv->pci_dev->dev,
365 "Failed clearing aux status flags (%02x)\n",
366 status);
367 return -EBUSY;
368 }
369 }
370 }
371
372 return 0;
373 }
374
375 /*
376 * Convert the status register to an error code, and clear it.
377 * Note that status only contains the bits we want to clear, not the
378 * actual register value.
379 */
i801_check_post(struct i801_priv * priv,int status)380 static int i801_check_post(struct i801_priv *priv, int status)
381 {
382 int result = 0;
383
384 /*
385 * If the SMBus is still busy, we give up
386 * Note: This timeout condition only happens when using polling
387 * transactions. For interrupt operation, NAK/timeout is indicated by
388 * DEV_ERR.
389 */
390 if (unlikely(status < 0)) {
391 dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
392 /* try to stop the current command */
393 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
394 outb_p(SMBHSTCNT_KILL, SMBHSTCNT(priv));
395 usleep_range(1000, 2000);
396 outb_p(0, SMBHSTCNT(priv));
397
398 /* Check if it worked */
399 status = inb_p(SMBHSTSTS(priv));
400 if ((status & SMBHSTSTS_HOST_BUSY) ||
401 !(status & SMBHSTSTS_FAILED))
402 dev_err(&priv->pci_dev->dev,
403 "Failed terminating the transaction\n");
404 outb_p(STATUS_FLAGS, SMBHSTSTS(priv));
405 return -ETIMEDOUT;
406 }
407
408 if (status & SMBHSTSTS_FAILED) {
409 result = -EIO;
410 dev_err(&priv->pci_dev->dev, "Transaction failed\n");
411 }
412 if (status & SMBHSTSTS_DEV_ERR) {
413 /*
414 * This may be a PEC error, check and clear it.
415 *
416 * AUXSTS is handled differently from HSTSTS.
417 * For HSTSTS, i801_isr() or i801_wait_intr()
418 * has already cleared the error bits in hardware,
419 * and we are passed a copy of the original value
420 * in "status".
421 * For AUXSTS, the hardware register is left
422 * for us to handle here.
423 * This is asymmetric, slightly iffy, but safe,
424 * since all this code is serialized and the CRCE
425 * bit is harmless as long as it's cleared before
426 * the next operation.
427 */
428 if ((priv->features & FEATURE_SMBUS_PEC) &&
429 (inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE)) {
430 outb_p(SMBAUXSTS_CRCE, SMBAUXSTS(priv));
431 result = -EBADMSG;
432 dev_dbg(&priv->pci_dev->dev, "PEC error\n");
433 } else {
434 result = -ENXIO;
435 dev_dbg(&priv->pci_dev->dev, "No response\n");
436 }
437 }
438 if (status & SMBHSTSTS_BUS_ERR) {
439 result = -EAGAIN;
440 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
441 }
442
443 /* Clear status flags except BYTE_DONE, to be cleared by caller */
444 outb_p(status, SMBHSTSTS(priv));
445
446 return result;
447 }
448
449 /* Wait for BUSY being cleared and either INTR or an error flag being set */
i801_wait_intr(struct i801_priv * priv)450 static int i801_wait_intr(struct i801_priv *priv)
451 {
452 unsigned long timeout = jiffies + priv->adapter.timeout;
453 int status, busy;
454
455 do {
456 usleep_range(250, 500);
457 status = inb_p(SMBHSTSTS(priv));
458 busy = status & SMBHSTSTS_HOST_BUSY;
459 status &= STATUS_ERROR_FLAGS | SMBHSTSTS_INTR;
460 if (!busy && status)
461 return status;
462 } while (time_is_after_eq_jiffies(timeout));
463
464 return -ETIMEDOUT;
465 }
466
467 /* Wait for either BYTE_DONE or an error flag being set */
i801_wait_byte_done(struct i801_priv * priv)468 static int i801_wait_byte_done(struct i801_priv *priv)
469 {
470 unsigned long timeout = jiffies + priv->adapter.timeout;
471 int status;
472
473 do {
474 usleep_range(250, 500);
475 status = inb_p(SMBHSTSTS(priv));
476 if (status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE))
477 return status & STATUS_ERROR_FLAGS;
478 } while (time_is_after_eq_jiffies(timeout));
479
480 return -ETIMEDOUT;
481 }
482
i801_transaction(struct i801_priv * priv,int xact)483 static int i801_transaction(struct i801_priv *priv, int xact)
484 {
485 int status;
486 unsigned long result;
487 const struct i2c_adapter *adap = &priv->adapter;
488
489 status = i801_check_pre(priv);
490 if (status < 0)
491 return status;
492
493 if (priv->features & FEATURE_IRQ) {
494 reinit_completion(&priv->done);
495 outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START,
496 SMBHSTCNT(priv));
497 result = wait_for_completion_timeout(&priv->done, adap->timeout);
498 return i801_check_post(priv, result ? priv->status : -ETIMEDOUT);
499 }
500
501 /* the current contents of SMBHSTCNT can be overwritten, since PEC,
502 * SMBSCMD are passed in xact */
503 outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv));
504
505 status = i801_wait_intr(priv);
506 return i801_check_post(priv, status);
507 }
508
i801_block_transaction_by_block(struct i801_priv * priv,union i2c_smbus_data * data,char read_write,int command)509 static int i801_block_transaction_by_block(struct i801_priv *priv,
510 union i2c_smbus_data *data,
511 char read_write, int command)
512 {
513 int i, len, status, xact;
514
515 switch (command) {
516 case I2C_SMBUS_BLOCK_PROC_CALL:
517 xact = I801_BLOCK_PROC_CALL;
518 break;
519 case I2C_SMBUS_BLOCK_DATA:
520 xact = I801_BLOCK_DATA;
521 break;
522 default:
523 return -EOPNOTSUPP;
524 }
525
526 inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
527
528 /* Use 32-byte buffer to process this transaction */
529 if (read_write == I2C_SMBUS_WRITE) {
530 len = data->block[0];
531 outb_p(len, SMBHSTDAT0(priv));
532 for (i = 0; i < len; i++)
533 outb_p(data->block[i+1], SMBBLKDAT(priv));
534 }
535
536 status = i801_transaction(priv, xact);
537 if (status)
538 return status;
539
540 if (read_write == I2C_SMBUS_READ ||
541 command == I2C_SMBUS_BLOCK_PROC_CALL) {
542 len = inb_p(SMBHSTDAT0(priv));
543 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
544 return -EPROTO;
545
546 data->block[0] = len;
547 for (i = 0; i < len; i++)
548 data->block[i + 1] = inb_p(SMBBLKDAT(priv));
549 }
550 return 0;
551 }
552
i801_isr_byte_done(struct i801_priv * priv)553 static void i801_isr_byte_done(struct i801_priv *priv)
554 {
555 if (priv->is_read) {
556 /* For SMBus block reads, length is received with first byte */
557 if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) &&
558 (priv->count == 0)) {
559 priv->len = inb_p(SMBHSTDAT0(priv));
560 if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) {
561 dev_err(&priv->pci_dev->dev,
562 "Illegal SMBus block read size %d\n",
563 priv->len);
564 /* FIXME: Recover */
565 priv->len = I2C_SMBUS_BLOCK_MAX;
566 }
567 priv->data[-1] = priv->len;
568 }
569
570 /* Read next byte */
571 if (priv->count < priv->len)
572 priv->data[priv->count++] = inb(SMBBLKDAT(priv));
573 else
574 dev_dbg(&priv->pci_dev->dev,
575 "Discarding extra byte on block read\n");
576
577 /* Set LAST_BYTE for last byte of read transaction */
578 if (priv->count == priv->len - 1)
579 outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE,
580 SMBHSTCNT(priv));
581 } else if (priv->count < priv->len - 1) {
582 /* Write next byte, except for IRQ after last byte */
583 outb_p(priv->data[++priv->count], SMBBLKDAT(priv));
584 }
585
586 /* Clear BYTE_DONE to continue with next byte */
587 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
588 }
589
i801_host_notify_isr(struct i801_priv * priv)590 static irqreturn_t i801_host_notify_isr(struct i801_priv *priv)
591 {
592 unsigned short addr;
593
594 addr = inb_p(SMBNTFDADD(priv)) >> 1;
595
596 /*
597 * With the tested platforms, reading SMBNTFDDAT (22 + (p)->smba)
598 * always returns 0. Our current implementation doesn't provide
599 * data, so we just ignore it.
600 */
601 i2c_handle_smbus_host_notify(&priv->adapter, addr);
602
603 /* clear Host Notify bit and return */
604 outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv));
605 return IRQ_HANDLED;
606 }
607
608 /*
609 * There are three kinds of interrupts:
610 *
611 * 1) i801 signals transaction completion with one of these interrupts:
612 * INTR - Success
613 * DEV_ERR - Invalid command, NAK or communication timeout
614 * BUS_ERR - SMI# transaction collision
615 * FAILED - transaction was canceled due to a KILL request
616 * When any of these occur, update ->status and signal completion.
617 * ->status must be cleared before kicking off the next transaction.
618 *
619 * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt
620 * occurs for each byte of a byte-by-byte to prepare the next byte.
621 *
622 * 3) Host Notify interrupts
623 */
i801_isr(int irq,void * dev_id)624 static irqreturn_t i801_isr(int irq, void *dev_id)
625 {
626 struct i801_priv *priv = dev_id;
627 u16 pcists;
628 u8 status;
629
630 /* Confirm this is our interrupt */
631 pci_read_config_word(priv->pci_dev, PCI_STATUS, &pcists);
632 if (!(pcists & PCI_STATUS_INTERRUPT))
633 return IRQ_NONE;
634
635 if (priv->features & FEATURE_HOST_NOTIFY) {
636 status = inb_p(SMBSLVSTS(priv));
637 if (status & SMBSLVSTS_HST_NTFY_STS)
638 return i801_host_notify_isr(priv);
639 }
640
641 status = inb_p(SMBHSTSTS(priv));
642 if (status & SMBHSTSTS_BYTE_DONE)
643 i801_isr_byte_done(priv);
644
645 /*
646 * Clear remaining IRQ sources: Completion of last command, errors
647 * and the SMB_ALERT signal. SMB_ALERT status is set after signal
648 * assertion independently of the interrupt generation being blocked
649 * or not so clear it always when the status is set.
650 */
651 status &= SMBHSTSTS_INTR | STATUS_ERROR_FLAGS | SMBHSTSTS_SMBALERT_STS;
652 if (status)
653 outb_p(status, SMBHSTSTS(priv));
654 status &= ~SMBHSTSTS_SMBALERT_STS; /* SMB_ALERT not reported */
655 /*
656 * Report transaction result.
657 * ->status must be cleared before the next transaction is started.
658 */
659 if (status) {
660 priv->status = status;
661 complete(&priv->done);
662 }
663
664 return IRQ_HANDLED;
665 }
666
667 /*
668 * For "byte-by-byte" block transactions:
669 * I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1
670 * I2C read uses cmd=I801_I2C_BLOCK_DATA
671 */
i801_block_transaction_byte_by_byte(struct i801_priv * priv,union i2c_smbus_data * data,char read_write,int command)672 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
673 union i2c_smbus_data *data,
674 char read_write, int command)
675 {
676 int i, len;
677 int smbcmd;
678 int status;
679 unsigned long result;
680 const struct i2c_adapter *adap = &priv->adapter;
681
682 if (command == I2C_SMBUS_BLOCK_PROC_CALL)
683 return -EOPNOTSUPP;
684
685 status = i801_check_pre(priv);
686 if (status < 0)
687 return status;
688
689 len = data->block[0];
690
691 if (read_write == I2C_SMBUS_WRITE) {
692 outb_p(len, SMBHSTDAT0(priv));
693 outb_p(data->block[1], SMBBLKDAT(priv));
694 }
695
696 if (command == I2C_SMBUS_I2C_BLOCK_DATA &&
697 read_write == I2C_SMBUS_READ)
698 smbcmd = I801_I2C_BLOCK_DATA;
699 else
700 smbcmd = I801_BLOCK_DATA;
701
702 if (priv->features & FEATURE_IRQ) {
703 priv->is_read = (read_write == I2C_SMBUS_READ);
704 if (len == 1 && priv->is_read)
705 smbcmd |= SMBHSTCNT_LAST_BYTE;
706 priv->cmd = smbcmd | SMBHSTCNT_INTREN;
707 priv->len = len;
708 priv->count = 0;
709 priv->data = &data->block[1];
710
711 reinit_completion(&priv->done);
712 outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv));
713 result = wait_for_completion_timeout(&priv->done, adap->timeout);
714 return i801_check_post(priv, result ? priv->status : -ETIMEDOUT);
715 }
716
717 for (i = 1; i <= len; i++) {
718 if (i == len && read_write == I2C_SMBUS_READ)
719 smbcmd |= SMBHSTCNT_LAST_BYTE;
720 outb_p(smbcmd, SMBHSTCNT(priv));
721
722 if (i == 1)
723 outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START,
724 SMBHSTCNT(priv));
725
726 status = i801_wait_byte_done(priv);
727 if (status)
728 goto exit;
729
730 if (i == 1 && read_write == I2C_SMBUS_READ
731 && command != I2C_SMBUS_I2C_BLOCK_DATA) {
732 len = inb_p(SMBHSTDAT0(priv));
733 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
734 dev_err(&priv->pci_dev->dev,
735 "Illegal SMBus block read size %d\n",
736 len);
737 /* Recover */
738 while (inb_p(SMBHSTSTS(priv)) &
739 SMBHSTSTS_HOST_BUSY)
740 outb_p(SMBHSTSTS_BYTE_DONE,
741 SMBHSTSTS(priv));
742 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
743 return -EPROTO;
744 }
745 data->block[0] = len;
746 }
747
748 /* Retrieve/store value in SMBBLKDAT */
749 if (read_write == I2C_SMBUS_READ)
750 data->block[i] = inb_p(SMBBLKDAT(priv));
751 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
752 outb_p(data->block[i+1], SMBBLKDAT(priv));
753
754 /* signals SMBBLKDAT ready */
755 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
756 }
757
758 status = i801_wait_intr(priv);
759 exit:
760 return i801_check_post(priv, status);
761 }
762
i801_set_block_buffer_mode(struct i801_priv * priv)763 static int i801_set_block_buffer_mode(struct i801_priv *priv)
764 {
765 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
766 if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0)
767 return -EIO;
768 return 0;
769 }
770
771 /* Block transaction function */
i801_block_transaction(struct i801_priv * priv,union i2c_smbus_data * data,char read_write,int command)772 static int i801_block_transaction(struct i801_priv *priv, union i2c_smbus_data *data,
773 char read_write, int command)
774 {
775 int result = 0;
776 unsigned char hostc;
777
778 if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
779 if (read_write == I2C_SMBUS_WRITE) {
780 /* set I2C_EN bit in configuration register */
781 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
782 pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
783 hostc | SMBHSTCFG_I2C_EN);
784 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
785 dev_err(&priv->pci_dev->dev,
786 "I2C block read is unsupported!\n");
787 return -EOPNOTSUPP;
788 }
789 }
790
791 if (read_write == I2C_SMBUS_WRITE
792 || command == I2C_SMBUS_I2C_BLOCK_DATA) {
793 if (data->block[0] < 1)
794 data->block[0] = 1;
795 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
796 data->block[0] = I2C_SMBUS_BLOCK_MAX;
797 } else {
798 data->block[0] = 32; /* max for SMBus block reads */
799 }
800
801 /* Experience has shown that the block buffer can only be used for
802 SMBus (not I2C) block transactions, even though the datasheet
803 doesn't mention this limitation. */
804 if ((priv->features & FEATURE_BLOCK_BUFFER)
805 && command != I2C_SMBUS_I2C_BLOCK_DATA
806 && i801_set_block_buffer_mode(priv) == 0)
807 result = i801_block_transaction_by_block(priv, data,
808 read_write,
809 command);
810 else
811 result = i801_block_transaction_byte_by_byte(priv, data,
812 read_write,
813 command);
814
815 if (command == I2C_SMBUS_I2C_BLOCK_DATA
816 && read_write == I2C_SMBUS_WRITE) {
817 /* restore saved configuration register value */
818 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
819 }
820 return result;
821 }
822
823 /* Return negative errno on error. */
i801_access(struct i2c_adapter * adap,u16 addr,unsigned short flags,char read_write,u8 command,int size,union i2c_smbus_data * data)824 static s32 i801_access(struct i2c_adapter *adap, u16 addr,
825 unsigned short flags, char read_write, u8 command,
826 int size, union i2c_smbus_data *data)
827 {
828 int hwpec;
829 int block = 0;
830 int ret = 0, xact = 0;
831 struct i801_priv *priv = i2c_get_adapdata(adap);
832
833 mutex_lock(&priv->acpi_lock);
834 if (priv->acpi_reserved) {
835 mutex_unlock(&priv->acpi_lock);
836 return -EBUSY;
837 }
838
839 pm_runtime_get_sync(&priv->pci_dev->dev);
840
841 hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
842 && size != I2C_SMBUS_QUICK
843 && size != I2C_SMBUS_I2C_BLOCK_DATA;
844
845 switch (size) {
846 case I2C_SMBUS_QUICK:
847 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
848 SMBHSTADD(priv));
849 xact = I801_QUICK;
850 break;
851 case I2C_SMBUS_BYTE:
852 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
853 SMBHSTADD(priv));
854 if (read_write == I2C_SMBUS_WRITE)
855 outb_p(command, SMBHSTCMD(priv));
856 xact = I801_BYTE;
857 break;
858 case I2C_SMBUS_BYTE_DATA:
859 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
860 SMBHSTADD(priv));
861 outb_p(command, SMBHSTCMD(priv));
862 if (read_write == I2C_SMBUS_WRITE)
863 outb_p(data->byte, SMBHSTDAT0(priv));
864 xact = I801_BYTE_DATA;
865 break;
866 case I2C_SMBUS_WORD_DATA:
867 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
868 SMBHSTADD(priv));
869 outb_p(command, SMBHSTCMD(priv));
870 if (read_write == I2C_SMBUS_WRITE) {
871 outb_p(data->word & 0xff, SMBHSTDAT0(priv));
872 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
873 }
874 xact = I801_WORD_DATA;
875 break;
876 case I2C_SMBUS_BLOCK_DATA:
877 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
878 SMBHSTADD(priv));
879 outb_p(command, SMBHSTCMD(priv));
880 block = 1;
881 break;
882 case I2C_SMBUS_I2C_BLOCK_DATA:
883 /*
884 * NB: page 240 of ICH5 datasheet shows that the R/#W
885 * bit should be cleared here, even when reading.
886 * However if SPD Write Disable is set (Lynx Point and later),
887 * the read will fail if we don't set the R/#W bit.
888 */
889 outb_p(((addr & 0x7f) << 1) |
890 ((priv->original_hstcfg & SMBHSTCFG_SPD_WD) ?
891 (read_write & 0x01) : 0),
892 SMBHSTADD(priv));
893 if (read_write == I2C_SMBUS_READ) {
894 /* NB: page 240 of ICH5 datasheet also shows
895 * that DATA1 is the cmd field when reading */
896 outb_p(command, SMBHSTDAT1(priv));
897 } else
898 outb_p(command, SMBHSTCMD(priv));
899 block = 1;
900 break;
901 case I2C_SMBUS_BLOCK_PROC_CALL:
902 /*
903 * Bit 0 of the slave address register always indicate a write
904 * command.
905 */
906 outb_p((addr & 0x7f) << 1, SMBHSTADD(priv));
907 outb_p(command, SMBHSTCMD(priv));
908 block = 1;
909 break;
910 default:
911 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n",
912 size);
913 ret = -EOPNOTSUPP;
914 goto out;
915 }
916
917 if (hwpec) /* enable/disable hardware PEC */
918 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
919 else
920 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
921 SMBAUXCTL(priv));
922
923 if (block)
924 ret = i801_block_transaction(priv, data, read_write, size);
925 else
926 ret = i801_transaction(priv, xact);
927
928 /* Some BIOSes don't like it when PEC is enabled at reboot or resume
929 time, so we forcibly disable it after every transaction. Turn off
930 E32B for the same reason. */
931 if (hwpec || block)
932 outb_p(inb_p(SMBAUXCTL(priv)) &
933 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
934
935 if (block)
936 goto out;
937 if (ret)
938 goto out;
939 if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
940 goto out;
941
942 switch (xact & 0x7f) {
943 case I801_BYTE: /* Result put in SMBHSTDAT0 */
944 case I801_BYTE_DATA:
945 data->byte = inb_p(SMBHSTDAT0(priv));
946 break;
947 case I801_WORD_DATA:
948 data->word = inb_p(SMBHSTDAT0(priv)) +
949 (inb_p(SMBHSTDAT1(priv)) << 8);
950 break;
951 }
952
953 out:
954 /* Unlock the SMBus device for use by BIOS/ACPI */
955 outb_p(SMBHSTSTS_INUSE_STS, SMBHSTSTS(priv));
956
957 pm_runtime_mark_last_busy(&priv->pci_dev->dev);
958 pm_runtime_put_autosuspend(&priv->pci_dev->dev);
959 mutex_unlock(&priv->acpi_lock);
960 return ret;
961 }
962
963
i801_func(struct i2c_adapter * adapter)964 static u32 i801_func(struct i2c_adapter *adapter)
965 {
966 struct i801_priv *priv = i2c_get_adapdata(adapter);
967
968 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
969 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
970 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
971 ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
972 ((priv->features & FEATURE_BLOCK_PROC) ?
973 I2C_FUNC_SMBUS_BLOCK_PROC_CALL : 0) |
974 ((priv->features & FEATURE_I2C_BLOCK_READ) ?
975 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0) |
976 ((priv->features & FEATURE_HOST_NOTIFY) ?
977 I2C_FUNC_SMBUS_HOST_NOTIFY : 0);
978 }
979
i801_enable_host_notify(struct i2c_adapter * adapter)980 static void i801_enable_host_notify(struct i2c_adapter *adapter)
981 {
982 struct i801_priv *priv = i2c_get_adapdata(adapter);
983
984 if (!(priv->features & FEATURE_HOST_NOTIFY))
985 return;
986
987 /*
988 * Enable host notify interrupt and block the generation of interrupt
989 * from the SMB_ALERT signal because the driver does not support
990 * SMBus Alert.
991 */
992 outb_p(SMBSLVCMD_HST_NTFY_INTREN | SMBSLVCMD_SMBALERT_DISABLE |
993 priv->original_slvcmd, SMBSLVCMD(priv));
994
995 /* clear Host Notify bit to allow a new notification */
996 outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv));
997 }
998
i801_disable_host_notify(struct i801_priv * priv)999 static void i801_disable_host_notify(struct i801_priv *priv)
1000 {
1001 if (!(priv->features & FEATURE_HOST_NOTIFY))
1002 return;
1003
1004 outb_p(priv->original_slvcmd, SMBSLVCMD(priv));
1005 }
1006
1007 static const struct i2c_algorithm smbus_algorithm = {
1008 .smbus_xfer = i801_access,
1009 .functionality = i801_func,
1010 };
1011
1012 static const struct pci_device_id i801_ids[] = {
1013 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
1014 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
1015 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
1016 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
1017 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
1018 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
1019 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
1020 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
1021 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
1022 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
1023 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
1024 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
1025 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) },
1026 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
1027 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
1028 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) },
1029 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) },
1030 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) },
1031 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) },
1032 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) },
1033 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) },
1034 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) },
1035 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) },
1036 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) },
1037 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) },
1038 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMBUS) },
1039 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS) },
1040 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0) },
1041 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) },
1042 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) },
1043 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS) },
1044 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS) },
1045 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS) },
1046 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS) },
1047 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS) },
1048 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS) },
1049 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS) },
1050 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS) },
1051 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CDF_SMBUS) },
1052 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_SMBUS) },
1053 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EBG_SMBUS) },
1054 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BROXTON_SMBUS) },
1055 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS) },
1056 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS) },
1057 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS) },
1058 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS) },
1059 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS) },
1060 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS) },
1061 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICELAKE_N_SMBUS) },
1062 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS) },
1063 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COMETLAKE_H_SMBUS) },
1064 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COMETLAKE_V_SMBUS) },
1065 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS) },
1066 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS) },
1067 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TIGERLAKE_H_SMBUS) },
1068 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS) },
1069 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ALDER_LAKE_S_SMBUS) },
1070 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ALDER_LAKE_P_SMBUS) },
1071 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ALDER_LAKE_M_SMBUS) },
1072 { 0, }
1073 };
1074
1075 MODULE_DEVICE_TABLE(pci, i801_ids);
1076
1077 #if defined CONFIG_X86 && defined CONFIG_DMI
1078 static unsigned char apanel_addr;
1079
1080 /* Scan the system ROM for the signature "FJKEYINF" */
bios_signature(const void __iomem * bios)1081 static __init const void __iomem *bios_signature(const void __iomem *bios)
1082 {
1083 ssize_t offset;
1084 const unsigned char signature[] = "FJKEYINF";
1085
1086 for (offset = 0; offset < 0x10000; offset += 0x10) {
1087 if (check_signature(bios + offset, signature,
1088 sizeof(signature)-1))
1089 return bios + offset;
1090 }
1091 return NULL;
1092 }
1093
input_apanel_init(void)1094 static void __init input_apanel_init(void)
1095 {
1096 void __iomem *bios;
1097 const void __iomem *p;
1098
1099 bios = ioremap(0xF0000, 0x10000); /* Can't fail */
1100 p = bios_signature(bios);
1101 if (p) {
1102 /* just use the first address */
1103 apanel_addr = readb(p + 8 + 3) >> 1;
1104 }
1105 iounmap(bios);
1106 }
1107
1108 struct dmi_onboard_device_info {
1109 const char *name;
1110 u8 type;
1111 unsigned short i2c_addr;
1112 const char *i2c_type;
1113 };
1114
1115 static const struct dmi_onboard_device_info dmi_devices[] = {
1116 { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
1117 { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
1118 { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
1119 };
1120
dmi_check_onboard_device(u8 type,const char * name,struct i2c_adapter * adap)1121 static void dmi_check_onboard_device(u8 type, const char *name,
1122 struct i2c_adapter *adap)
1123 {
1124 int i;
1125 struct i2c_board_info info;
1126
1127 for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
1128 /* & ~0x80, ignore enabled/disabled bit */
1129 if ((type & ~0x80) != dmi_devices[i].type)
1130 continue;
1131 if (strcasecmp(name, dmi_devices[i].name))
1132 continue;
1133
1134 memset(&info, 0, sizeof(struct i2c_board_info));
1135 info.addr = dmi_devices[i].i2c_addr;
1136 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
1137 i2c_new_client_device(adap, &info);
1138 break;
1139 }
1140 }
1141
1142 /* We use our own function to check for onboard devices instead of
1143 dmi_find_device() as some buggy BIOS's have the devices we are interested
1144 in marked as disabled */
dmi_check_onboard_devices(const struct dmi_header * dm,void * adap)1145 static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap)
1146 {
1147 int i, count;
1148
1149 if (dm->type != 10)
1150 return;
1151
1152 count = (dm->length - sizeof(struct dmi_header)) / 2;
1153 for (i = 0; i < count; i++) {
1154 const u8 *d = (char *)(dm + 1) + (i * 2);
1155 const char *name = ((char *) dm) + dm->length;
1156 u8 type = d[0];
1157 u8 s = d[1];
1158
1159 if (!s)
1160 continue;
1161 s--;
1162 while (s > 0 && name[0]) {
1163 name += strlen(name) + 1;
1164 s--;
1165 }
1166 if (name[0] == 0) /* Bogus string reference */
1167 continue;
1168
1169 dmi_check_onboard_device(type, name, adap);
1170 }
1171 }
1172
1173 /* NOTE: Keep this list in sync with drivers/platform/x86/dell-smo8800.c */
1174 static const char *const acpi_smo8800_ids[] = {
1175 "SMO8800",
1176 "SMO8801",
1177 "SMO8810",
1178 "SMO8811",
1179 "SMO8820",
1180 "SMO8821",
1181 "SMO8830",
1182 "SMO8831",
1183 };
1184
check_acpi_smo88xx_device(acpi_handle obj_handle,u32 nesting_level,void * context,void ** return_value)1185 static acpi_status check_acpi_smo88xx_device(acpi_handle obj_handle,
1186 u32 nesting_level,
1187 void *context,
1188 void **return_value)
1189 {
1190 struct acpi_device_info *info;
1191 acpi_status status;
1192 char *hid;
1193 int i;
1194
1195 status = acpi_get_object_info(obj_handle, &info);
1196 if (ACPI_FAILURE(status))
1197 return AE_OK;
1198
1199 if (!(info->valid & ACPI_VALID_HID))
1200 goto smo88xx_not_found;
1201
1202 hid = info->hardware_id.string;
1203 if (!hid)
1204 goto smo88xx_not_found;
1205
1206 i = match_string(acpi_smo8800_ids, ARRAY_SIZE(acpi_smo8800_ids), hid);
1207 if (i < 0)
1208 goto smo88xx_not_found;
1209
1210 kfree(info);
1211
1212 *return_value = NULL;
1213 return AE_CTRL_TERMINATE;
1214
1215 smo88xx_not_found:
1216 kfree(info);
1217 return AE_OK;
1218 }
1219
is_dell_system_with_lis3lv02d(void)1220 static bool is_dell_system_with_lis3lv02d(void)
1221 {
1222 void *err = ERR_PTR(-ENOENT);
1223
1224 if (!dmi_match(DMI_SYS_VENDOR, "Dell Inc."))
1225 return false;
1226
1227 /*
1228 * Check that ACPI device SMO88xx is present and is functioning.
1229 * Function acpi_get_devices() already filters all ACPI devices
1230 * which are not present or are not functioning.
1231 * ACPI device SMO88xx represents our ST microelectronics lis3lv02d
1232 * accelerometer but unfortunately ACPI does not provide any other
1233 * information (like I2C address).
1234 */
1235 acpi_get_devices(NULL, check_acpi_smo88xx_device, NULL, &err);
1236
1237 return !IS_ERR(err);
1238 }
1239
1240 /*
1241 * Accelerometer's I2C address is not specified in DMI nor ACPI,
1242 * so it is needed to define mapping table based on DMI product names.
1243 */
1244 static const struct {
1245 const char *dmi_product_name;
1246 unsigned short i2c_addr;
1247 } dell_lis3lv02d_devices[] = {
1248 /*
1249 * Dell platform team told us that these Latitude devices have
1250 * ST microelectronics accelerometer at I2C address 0x29.
1251 */
1252 { "Latitude E5250", 0x29 },
1253 { "Latitude E5450", 0x29 },
1254 { "Latitude E5550", 0x29 },
1255 { "Latitude E6440", 0x29 },
1256 { "Latitude E6440 ATG", 0x29 },
1257 { "Latitude E6540", 0x29 },
1258 /*
1259 * Additional individual entries were added after verification.
1260 */
1261 { "Latitude 5480", 0x29 },
1262 { "Vostro V131", 0x1d },
1263 };
1264
register_dell_lis3lv02d_i2c_device(struct i801_priv * priv)1265 static void register_dell_lis3lv02d_i2c_device(struct i801_priv *priv)
1266 {
1267 struct i2c_board_info info;
1268 const char *dmi_product_name;
1269 int i;
1270
1271 dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
1272 for (i = 0; i < ARRAY_SIZE(dell_lis3lv02d_devices); ++i) {
1273 if (strcmp(dmi_product_name,
1274 dell_lis3lv02d_devices[i].dmi_product_name) == 0)
1275 break;
1276 }
1277
1278 if (i == ARRAY_SIZE(dell_lis3lv02d_devices)) {
1279 dev_warn(&priv->pci_dev->dev,
1280 "Accelerometer lis3lv02d is present on SMBus but its"
1281 " address is unknown, skipping registration\n");
1282 return;
1283 }
1284
1285 memset(&info, 0, sizeof(struct i2c_board_info));
1286 info.addr = dell_lis3lv02d_devices[i].i2c_addr;
1287 strlcpy(info.type, "lis3lv02d", I2C_NAME_SIZE);
1288 i2c_new_client_device(&priv->adapter, &info);
1289 }
1290
1291 /* Register optional slaves */
i801_probe_optional_slaves(struct i801_priv * priv)1292 static void i801_probe_optional_slaves(struct i801_priv *priv)
1293 {
1294 /* Only register slaves on main SMBus channel */
1295 if (priv->features & FEATURE_IDF)
1296 return;
1297
1298 if (apanel_addr) {
1299 struct i2c_board_info info = {
1300 .addr = apanel_addr,
1301 .type = "fujitsu_apanel",
1302 };
1303
1304 i2c_new_client_device(&priv->adapter, &info);
1305 }
1306
1307 if (dmi_name_in_vendors("FUJITSU"))
1308 dmi_walk(dmi_check_onboard_devices, &priv->adapter);
1309
1310 if (is_dell_system_with_lis3lv02d())
1311 register_dell_lis3lv02d_i2c_device(priv);
1312
1313 /* Instantiate SPD EEPROMs unless the SMBus is multiplexed */
1314 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO)
1315 if (!priv->mux_drvdata)
1316 #endif
1317 i2c_register_spd(&priv->adapter);
1318 }
1319 #else
input_apanel_init(void)1320 static void __init input_apanel_init(void) {}
i801_probe_optional_slaves(struct i801_priv * priv)1321 static void i801_probe_optional_slaves(struct i801_priv *priv) {}
1322 #endif /* CONFIG_X86 && CONFIG_DMI */
1323
1324 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
1325 static struct i801_mux_config i801_mux_config_asus_z8_d12 = {
1326 .gpio_chip = "gpio_ich",
1327 .values = { 0x02, 0x03 },
1328 .n_values = 2,
1329 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD },
1330 .gpios = { 52, 53 },
1331 .n_gpios = 2,
1332 };
1333
1334 static struct i801_mux_config i801_mux_config_asus_z8_d18 = {
1335 .gpio_chip = "gpio_ich",
1336 .values = { 0x02, 0x03, 0x01 },
1337 .n_values = 3,
1338 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD },
1339 .gpios = { 52, 53 },
1340 .n_gpios = 2,
1341 };
1342
1343 static const struct dmi_system_id mux_dmi_table[] = {
1344 {
1345 .matches = {
1346 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1347 DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"),
1348 },
1349 .driver_data = &i801_mux_config_asus_z8_d12,
1350 },
1351 {
1352 .matches = {
1353 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1354 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"),
1355 },
1356 .driver_data = &i801_mux_config_asus_z8_d12,
1357 },
1358 {
1359 .matches = {
1360 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1361 DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"),
1362 },
1363 .driver_data = &i801_mux_config_asus_z8_d12,
1364 },
1365 {
1366 .matches = {
1367 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1368 DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"),
1369 },
1370 .driver_data = &i801_mux_config_asus_z8_d12,
1371 },
1372 {
1373 .matches = {
1374 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1375 DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"),
1376 },
1377 .driver_data = &i801_mux_config_asus_z8_d12,
1378 },
1379 {
1380 .matches = {
1381 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1382 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"),
1383 },
1384 .driver_data = &i801_mux_config_asus_z8_d12,
1385 },
1386 {
1387 .matches = {
1388 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1389 DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"),
1390 },
1391 .driver_data = &i801_mux_config_asus_z8_d18,
1392 },
1393 {
1394 .matches = {
1395 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1396 DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"),
1397 },
1398 .driver_data = &i801_mux_config_asus_z8_d18,
1399 },
1400 {
1401 .matches = {
1402 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1403 DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"),
1404 },
1405 .driver_data = &i801_mux_config_asus_z8_d12,
1406 },
1407 { }
1408 };
1409
1410 /* Setup multiplexing if needed */
i801_add_mux(struct i801_priv * priv)1411 static void i801_add_mux(struct i801_priv *priv)
1412 {
1413 struct device *dev = &priv->adapter.dev;
1414 const struct i801_mux_config *mux_config;
1415 struct i2c_mux_gpio_platform_data gpio_data;
1416 struct gpiod_lookup_table *lookup;
1417 int i;
1418
1419 if (!priv->mux_drvdata)
1420 return;
1421 mux_config = priv->mux_drvdata;
1422
1423 /* Prepare the platform data */
1424 memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data));
1425 gpio_data.parent = priv->adapter.nr;
1426 gpio_data.values = mux_config->values;
1427 gpio_data.n_values = mux_config->n_values;
1428 gpio_data.classes = mux_config->classes;
1429 gpio_data.idle = I2C_MUX_GPIO_NO_IDLE;
1430
1431 /* Register GPIO descriptor lookup table */
1432 lookup = devm_kzalloc(dev,
1433 struct_size(lookup, table, mux_config->n_gpios + 1),
1434 GFP_KERNEL);
1435 if (!lookup)
1436 return;
1437 lookup->dev_id = "i2c-mux-gpio";
1438 for (i = 0; i < mux_config->n_gpios; i++)
1439 lookup->table[i] = GPIO_LOOKUP(mux_config->gpio_chip,
1440 mux_config->gpios[i], "mux", 0);
1441 gpiod_add_lookup_table(lookup);
1442 priv->lookup = lookup;
1443
1444 /*
1445 * Register the mux device, we use PLATFORM_DEVID_NONE here
1446 * because since we are referring to the GPIO chip by name we are
1447 * anyways in deep trouble if there is more than one of these
1448 * devices, and there should likely only be one platform controller
1449 * hub.
1450 */
1451 priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio",
1452 PLATFORM_DEVID_NONE, &gpio_data,
1453 sizeof(struct i2c_mux_gpio_platform_data));
1454 if (IS_ERR(priv->mux_pdev)) {
1455 gpiod_remove_lookup_table(lookup);
1456 dev_err(dev, "Failed to register i2c-mux-gpio device\n");
1457 }
1458 }
1459
i801_del_mux(struct i801_priv * priv)1460 static void i801_del_mux(struct i801_priv *priv)
1461 {
1462 platform_device_unregister(priv->mux_pdev);
1463 gpiod_remove_lookup_table(priv->lookup);
1464 }
1465
i801_get_adapter_class(struct i801_priv * priv)1466 static unsigned int i801_get_adapter_class(struct i801_priv *priv)
1467 {
1468 const struct dmi_system_id *id;
1469 const struct i801_mux_config *mux_config;
1470 unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
1471 int i;
1472
1473 id = dmi_first_match(mux_dmi_table);
1474 if (id) {
1475 /* Remove branch classes from trunk */
1476 mux_config = id->driver_data;
1477 for (i = 0; i < mux_config->n_values; i++)
1478 class &= ~mux_config->classes[i];
1479
1480 /* Remember for later */
1481 priv->mux_drvdata = mux_config;
1482 }
1483
1484 return class;
1485 }
1486 #else
i801_add_mux(struct i801_priv * priv)1487 static inline void i801_add_mux(struct i801_priv *priv) { }
i801_del_mux(struct i801_priv * priv)1488 static inline void i801_del_mux(struct i801_priv *priv) { }
1489
i801_get_adapter_class(struct i801_priv * priv)1490 static inline unsigned int i801_get_adapter_class(struct i801_priv *priv)
1491 {
1492 return I2C_CLASS_HWMON | I2C_CLASS_SPD;
1493 }
1494 #endif
1495
1496 static const struct itco_wdt_platform_data spt_tco_platform_data = {
1497 .name = "Intel PCH",
1498 .version = 4,
1499 };
1500
1501 static struct platform_device *
i801_add_tco_spt(struct i801_priv * priv,struct pci_dev * pci_dev,struct resource * tco_res)1502 i801_add_tco_spt(struct i801_priv *priv, struct pci_dev *pci_dev,
1503 struct resource *tco_res)
1504 {
1505 struct resource *res;
1506 unsigned int devfn;
1507 u64 base64_addr;
1508 u32 base_addr;
1509 u8 hidden;
1510
1511 /*
1512 * We must access the NO_REBOOT bit over the Primary to Sideband
1513 * bridge (P2SB). The BIOS prevents the P2SB device from being
1514 * enumerated by the PCI subsystem, so we need to unhide/hide it
1515 * to lookup the P2SB BAR.
1516 */
1517 pci_lock_rescan_remove();
1518
1519 devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 1);
1520
1521 /* Unhide the P2SB device, if it is hidden */
1522 pci_bus_read_config_byte(pci_dev->bus, devfn, 0xe1, &hidden);
1523 if (hidden)
1524 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x0);
1525
1526 pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR, &base_addr);
1527 base64_addr = base_addr & 0xfffffff0;
1528
1529 pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR + 0x4, &base_addr);
1530 base64_addr |= (u64)base_addr << 32;
1531
1532 /* Hide the P2SB device, if it was hidden before */
1533 if (hidden)
1534 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, hidden);
1535 pci_unlock_rescan_remove();
1536
1537 res = &tco_res[1];
1538 if (pci_dev->device == PCI_DEVICE_ID_INTEL_DNV_SMBUS)
1539 res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL_DNV;
1540 else
1541 res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL;
1542
1543 res->end = res->start + 3;
1544 res->flags = IORESOURCE_MEM;
1545
1546 return platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1,
1547 tco_res, 2, &spt_tco_platform_data,
1548 sizeof(spt_tco_platform_data));
1549 }
1550
1551 static const struct itco_wdt_platform_data cnl_tco_platform_data = {
1552 .name = "Intel PCH",
1553 .version = 6,
1554 };
1555
1556 static struct platform_device *
i801_add_tco_cnl(struct i801_priv * priv,struct pci_dev * pci_dev,struct resource * tco_res)1557 i801_add_tco_cnl(struct i801_priv *priv, struct pci_dev *pci_dev,
1558 struct resource *tco_res)
1559 {
1560 return platform_device_register_resndata(&pci_dev->dev,
1561 "iTCO_wdt", -1, tco_res, 1, &cnl_tco_platform_data,
1562 sizeof(cnl_tco_platform_data));
1563 }
1564
i801_add_tco(struct i801_priv * priv)1565 static void i801_add_tco(struct i801_priv *priv)
1566 {
1567 struct pci_dev *pci_dev = priv->pci_dev;
1568 struct resource tco_res[2], *res;
1569 u32 tco_base, tco_ctl;
1570
1571 /* If we have ACPI based watchdog use that instead */
1572 if (acpi_has_watchdog())
1573 return;
1574
1575 if (!(priv->features & (FEATURE_TCO_SPT | FEATURE_TCO_CNL)))
1576 return;
1577
1578 pci_read_config_dword(pci_dev, TCOBASE, &tco_base);
1579 pci_read_config_dword(pci_dev, TCOCTL, &tco_ctl);
1580 if (!(tco_ctl & TCOCTL_EN))
1581 return;
1582
1583 memset(tco_res, 0, sizeof(tco_res));
1584 /*
1585 * Always populate the main iTCO IO resource here. The second entry
1586 * for NO_REBOOT MMIO is filled by the SPT specific function.
1587 */
1588 res = &tco_res[0];
1589 res->start = tco_base & ~1;
1590 res->end = res->start + 32 - 1;
1591 res->flags = IORESOURCE_IO;
1592
1593 if (priv->features & FEATURE_TCO_CNL)
1594 priv->tco_pdev = i801_add_tco_cnl(priv, pci_dev, tco_res);
1595 else
1596 priv->tco_pdev = i801_add_tco_spt(priv, pci_dev, tco_res);
1597
1598 if (IS_ERR(priv->tco_pdev))
1599 dev_warn(&pci_dev->dev, "failed to create iTCO device\n");
1600 }
1601
1602 #ifdef CONFIG_ACPI
i801_acpi_is_smbus_ioport(const struct i801_priv * priv,acpi_physical_address address)1603 static bool i801_acpi_is_smbus_ioport(const struct i801_priv *priv,
1604 acpi_physical_address address)
1605 {
1606 return address >= priv->smba &&
1607 address <= pci_resource_end(priv->pci_dev, SMBBAR);
1608 }
1609
1610 static acpi_status
i801_acpi_io_handler(u32 function,acpi_physical_address address,u32 bits,u64 * value,void * handler_context,void * region_context)1611 i801_acpi_io_handler(u32 function, acpi_physical_address address, u32 bits,
1612 u64 *value, void *handler_context, void *region_context)
1613 {
1614 struct i801_priv *priv = handler_context;
1615 struct pci_dev *pdev = priv->pci_dev;
1616 acpi_status status;
1617
1618 /*
1619 * Once BIOS AML code touches the OpRegion we warn and inhibit any
1620 * further access from the driver itself. This device is now owned
1621 * by the system firmware.
1622 */
1623 mutex_lock(&priv->acpi_lock);
1624
1625 if (!priv->acpi_reserved && i801_acpi_is_smbus_ioport(priv, address)) {
1626 priv->acpi_reserved = true;
1627
1628 dev_warn(&pdev->dev, "BIOS is accessing SMBus registers\n");
1629 dev_warn(&pdev->dev, "Driver SMBus register access inhibited\n");
1630
1631 /*
1632 * BIOS is accessing the host controller so prevent it from
1633 * suspending automatically from now on.
1634 */
1635 pm_runtime_get_sync(&pdev->dev);
1636 }
1637
1638 if ((function & ACPI_IO_MASK) == ACPI_READ)
1639 status = acpi_os_read_port(address, (u32 *)value, bits);
1640 else
1641 status = acpi_os_write_port(address, (u32)*value, bits);
1642
1643 mutex_unlock(&priv->acpi_lock);
1644
1645 return status;
1646 }
1647
i801_acpi_probe(struct i801_priv * priv)1648 static int i801_acpi_probe(struct i801_priv *priv)
1649 {
1650 acpi_handle ah = ACPI_HANDLE(&priv->pci_dev->dev);
1651 acpi_status status;
1652
1653 status = acpi_install_address_space_handler(ah, ACPI_ADR_SPACE_SYSTEM_IO,
1654 i801_acpi_io_handler, NULL, priv);
1655 if (ACPI_SUCCESS(status))
1656 return 0;
1657
1658 return acpi_check_resource_conflict(&priv->pci_dev->resource[SMBBAR]);
1659 }
1660
i801_acpi_remove(struct i801_priv * priv)1661 static void i801_acpi_remove(struct i801_priv *priv)
1662 {
1663 acpi_handle ah = ACPI_HANDLE(&priv->pci_dev->dev);
1664
1665 acpi_remove_address_space_handler(ah, ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler);
1666 }
1667 #else
i801_acpi_probe(struct i801_priv * priv)1668 static inline int i801_acpi_probe(struct i801_priv *priv) { return 0; }
i801_acpi_remove(struct i801_priv * priv)1669 static inline void i801_acpi_remove(struct i801_priv *priv) { }
1670 #endif
1671
i801_setup_hstcfg(struct i801_priv * priv)1672 static void i801_setup_hstcfg(struct i801_priv *priv)
1673 {
1674 unsigned char hstcfg = priv->original_hstcfg;
1675
1676 hstcfg &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */
1677 hstcfg |= SMBHSTCFG_HST_EN;
1678 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hstcfg);
1679 }
1680
i801_probe(struct pci_dev * dev,const struct pci_device_id * id)1681 static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
1682 {
1683 int err, i;
1684 struct i801_priv *priv;
1685
1686 priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
1687 if (!priv)
1688 return -ENOMEM;
1689
1690 i2c_set_adapdata(&priv->adapter, priv);
1691 priv->adapter.owner = THIS_MODULE;
1692 priv->adapter.class = i801_get_adapter_class(priv);
1693 priv->adapter.algo = &smbus_algorithm;
1694 priv->adapter.dev.parent = &dev->dev;
1695 ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&dev->dev));
1696 priv->adapter.retries = 3;
1697 mutex_init(&priv->acpi_lock);
1698
1699 priv->pci_dev = dev;
1700 switch (dev->device) {
1701 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS:
1702 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS:
1703 case PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS:
1704 case PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS:
1705 case PCI_DEVICE_ID_INTEL_DNV_SMBUS:
1706 case PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS:
1707 case PCI_DEVICE_ID_INTEL_COMETLAKE_V_SMBUS:
1708 priv->features |= FEATURE_BLOCK_PROC;
1709 priv->features |= FEATURE_I2C_BLOCK_READ;
1710 priv->features |= FEATURE_IRQ;
1711 priv->features |= FEATURE_SMBUS_PEC;
1712 priv->features |= FEATURE_BLOCK_BUFFER;
1713 priv->features |= FEATURE_TCO_SPT;
1714 priv->features |= FEATURE_HOST_NOTIFY;
1715 break;
1716
1717 case PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS:
1718 case PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS:
1719 case PCI_DEVICE_ID_INTEL_CDF_SMBUS:
1720 case PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS:
1721 case PCI_DEVICE_ID_INTEL_ICELAKE_N_SMBUS:
1722 case PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS:
1723 case PCI_DEVICE_ID_INTEL_COMETLAKE_H_SMBUS:
1724 case PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS:
1725 case PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS:
1726 case PCI_DEVICE_ID_INTEL_TIGERLAKE_H_SMBUS:
1727 case PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS:
1728 case PCI_DEVICE_ID_INTEL_EBG_SMBUS:
1729 case PCI_DEVICE_ID_INTEL_ALDER_LAKE_S_SMBUS:
1730 case PCI_DEVICE_ID_INTEL_ALDER_LAKE_P_SMBUS:
1731 case PCI_DEVICE_ID_INTEL_ALDER_LAKE_M_SMBUS:
1732 priv->features |= FEATURE_BLOCK_PROC;
1733 priv->features |= FEATURE_I2C_BLOCK_READ;
1734 priv->features |= FEATURE_IRQ;
1735 priv->features |= FEATURE_SMBUS_PEC;
1736 priv->features |= FEATURE_BLOCK_BUFFER;
1737 priv->features |= FEATURE_TCO_CNL;
1738 priv->features |= FEATURE_HOST_NOTIFY;
1739 break;
1740
1741 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0:
1742 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1:
1743 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2:
1744 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0:
1745 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1:
1746 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2:
1747 priv->features |= FEATURE_IDF;
1748 fallthrough;
1749 default:
1750 priv->features |= FEATURE_BLOCK_PROC;
1751 priv->features |= FEATURE_I2C_BLOCK_READ;
1752 priv->features |= FEATURE_IRQ;
1753 fallthrough;
1754 case PCI_DEVICE_ID_INTEL_82801DB_3:
1755 priv->features |= FEATURE_SMBUS_PEC;
1756 priv->features |= FEATURE_BLOCK_BUFFER;
1757 fallthrough;
1758 case PCI_DEVICE_ID_INTEL_82801CA_3:
1759 priv->features |= FEATURE_HOST_NOTIFY;
1760 fallthrough;
1761 case PCI_DEVICE_ID_INTEL_82801BA_2:
1762 case PCI_DEVICE_ID_INTEL_82801AB_3:
1763 case PCI_DEVICE_ID_INTEL_82801AA_3:
1764 break;
1765 }
1766
1767 /* Disable features on user request */
1768 for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
1769 if (priv->features & disable_features & (1 << i))
1770 dev_notice(&dev->dev, "%s disabled by user\n",
1771 i801_feature_names[i]);
1772 }
1773 priv->features &= ~disable_features;
1774
1775 err = pcim_enable_device(dev);
1776 if (err) {
1777 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
1778 err);
1779 return err;
1780 }
1781 pcim_pin_device(dev);
1782
1783 /* Determine the address of the SMBus area */
1784 priv->smba = pci_resource_start(dev, SMBBAR);
1785 if (!priv->smba) {
1786 dev_err(&dev->dev,
1787 "SMBus base address uninitialized, upgrade BIOS\n");
1788 return -ENODEV;
1789 }
1790
1791 if (i801_acpi_probe(priv))
1792 return -ENODEV;
1793
1794 err = pcim_iomap_regions(dev, 1 << SMBBAR, DRV_NAME);
1795 if (err) {
1796 dev_err(&dev->dev,
1797 "Failed to request SMBus region 0x%lx-0x%Lx\n",
1798 priv->smba,
1799 (unsigned long long)pci_resource_end(dev, SMBBAR));
1800 i801_acpi_remove(priv);
1801 return err;
1802 }
1803
1804 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &priv->original_hstcfg);
1805 i801_setup_hstcfg(priv);
1806 if (!(priv->original_hstcfg & SMBHSTCFG_HST_EN))
1807 dev_info(&dev->dev, "Enabling SMBus device\n");
1808
1809 if (priv->original_hstcfg & SMBHSTCFG_SMB_SMI_EN) {
1810 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
1811 /* Disable SMBus interrupt feature if SMBus using SMI# */
1812 priv->features &= ~FEATURE_IRQ;
1813 }
1814 if (priv->original_hstcfg & SMBHSTCFG_SPD_WD)
1815 dev_info(&dev->dev, "SPD Write Disable is set\n");
1816
1817 /* Clear special mode bits */
1818 if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
1819 outb_p(inb_p(SMBAUXCTL(priv)) &
1820 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
1821
1822 /* Remember original Interrupt and Host Notify settings */
1823 priv->original_hstcnt = inb_p(SMBHSTCNT(priv)) & ~SMBHSTCNT_KILL;
1824 if (priv->features & FEATURE_HOST_NOTIFY)
1825 priv->original_slvcmd = inb_p(SMBSLVCMD(priv));
1826
1827 /* Default timeout in interrupt mode: 200 ms */
1828 priv->adapter.timeout = HZ / 5;
1829
1830 if (dev->irq == IRQ_NOTCONNECTED)
1831 priv->features &= ~FEATURE_IRQ;
1832
1833 if (priv->features & FEATURE_IRQ) {
1834 u16 pcists;
1835
1836 /* Complain if an interrupt is already pending */
1837 pci_read_config_word(priv->pci_dev, PCI_STATUS, &pcists);
1838 if (pcists & PCI_STATUS_INTERRUPT)
1839 dev_warn(&dev->dev, "An interrupt is pending!\n");
1840 }
1841
1842 if (priv->features & FEATURE_IRQ) {
1843 init_completion(&priv->done);
1844
1845 err = devm_request_irq(&dev->dev, dev->irq, i801_isr,
1846 IRQF_SHARED, DRV_NAME, priv);
1847 if (err) {
1848 dev_err(&dev->dev, "Failed to allocate irq %d: %d\n",
1849 dev->irq, err);
1850 priv->features &= ~FEATURE_IRQ;
1851 }
1852 }
1853 dev_info(&dev->dev, "SMBus using %s\n",
1854 priv->features & FEATURE_IRQ ? "PCI interrupt" : "polling");
1855
1856 i801_add_tco(priv);
1857
1858 snprintf(priv->adapter.name, sizeof(priv->adapter.name),
1859 "SMBus I801 adapter at %04lx", priv->smba);
1860 err = i2c_add_adapter(&priv->adapter);
1861 if (err) {
1862 i801_acpi_remove(priv);
1863 return err;
1864 }
1865
1866 i801_enable_host_notify(&priv->adapter);
1867
1868 i801_probe_optional_slaves(priv);
1869 /* We ignore errors - multiplexing is optional */
1870 i801_add_mux(priv);
1871
1872 pci_set_drvdata(dev, priv);
1873
1874 dev_pm_set_driver_flags(&dev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
1875 pm_runtime_set_autosuspend_delay(&dev->dev, 1000);
1876 pm_runtime_use_autosuspend(&dev->dev);
1877 pm_runtime_put_autosuspend(&dev->dev);
1878 pm_runtime_allow(&dev->dev);
1879
1880 return 0;
1881 }
1882
i801_remove(struct pci_dev * dev)1883 static void i801_remove(struct pci_dev *dev)
1884 {
1885 struct i801_priv *priv = pci_get_drvdata(dev);
1886
1887 outb_p(priv->original_hstcnt, SMBHSTCNT(priv));
1888 i801_disable_host_notify(priv);
1889 i801_del_mux(priv);
1890 i2c_del_adapter(&priv->adapter);
1891 i801_acpi_remove(priv);
1892 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1893
1894 platform_device_unregister(priv->tco_pdev);
1895
1896 /* if acpi_reserved is set then usage_count is incremented already */
1897 if (!priv->acpi_reserved)
1898 pm_runtime_get_noresume(&dev->dev);
1899
1900 /*
1901 * do not call pci_disable_device(dev) since it can cause hard hangs on
1902 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
1903 */
1904 }
1905
i801_shutdown(struct pci_dev * dev)1906 static void i801_shutdown(struct pci_dev *dev)
1907 {
1908 struct i801_priv *priv = pci_get_drvdata(dev);
1909
1910 /* Restore config registers to avoid hard hang on some systems */
1911 outb_p(priv->original_hstcnt, SMBHSTCNT(priv));
1912 i801_disable_host_notify(priv);
1913 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1914 }
1915
1916 #ifdef CONFIG_PM_SLEEP
i801_suspend(struct device * dev)1917 static int i801_suspend(struct device *dev)
1918 {
1919 struct i801_priv *priv = dev_get_drvdata(dev);
1920
1921 outb_p(priv->original_hstcnt, SMBHSTCNT(priv));
1922 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, priv->original_hstcfg);
1923 return 0;
1924 }
1925
i801_resume(struct device * dev)1926 static int i801_resume(struct device *dev)
1927 {
1928 struct i801_priv *priv = dev_get_drvdata(dev);
1929
1930 i801_setup_hstcfg(priv);
1931 i801_enable_host_notify(&priv->adapter);
1932
1933 return 0;
1934 }
1935 #endif
1936
1937 static SIMPLE_DEV_PM_OPS(i801_pm_ops, i801_suspend, i801_resume);
1938
1939 static struct pci_driver i801_driver = {
1940 .name = DRV_NAME,
1941 .id_table = i801_ids,
1942 .probe = i801_probe,
1943 .remove = i801_remove,
1944 .shutdown = i801_shutdown,
1945 .driver = {
1946 .pm = &i801_pm_ops,
1947 },
1948 };
1949
i2c_i801_init(void)1950 static int __init i2c_i801_init(void)
1951 {
1952 if (dmi_name_in_vendors("FUJITSU"))
1953 input_apanel_init();
1954 return pci_register_driver(&i801_driver);
1955 }
1956
i2c_i801_exit(void)1957 static void __exit i2c_i801_exit(void)
1958 {
1959 pci_unregister_driver(&i801_driver);
1960 }
1961
1962 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>");
1963 MODULE_AUTHOR("Jean Delvare <jdelvare@suse.de>");
1964 MODULE_DESCRIPTION("I801 SMBus driver");
1965 MODULE_LICENSE("GPL");
1966
1967 module_init(i2c_i801_init);
1968 module_exit(i2c_i801_exit);
1969