1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * MPU3050 gyroscope driver
4 *
5 * Copyright (C) 2016 Linaro Ltd.
6 * Author: Linus Walleij <linus.walleij@linaro.org>
7 *
8 * Based on the input subsystem driver, Copyright (C) 2011 Wistron Co.Ltd
9 * Joseph Lai <joseph_lai@wistron.com> and trimmed down by
10 * Alan Cox <alan@linux.intel.com> in turn based on bma023.c.
11 * Device behaviour based on a misc driver posted by Nathan Royer in 2011.
12 *
13 * TODO: add support for setting up the low pass 3dB frequency.
14 */
15
16 #include <linux/bitfield.h>
17 #include <linux/bitops.h>
18 #include <linux/delay.h>
19 #include <linux/err.h>
20 #include <linux/iio/buffer.h>
21 #include <linux/iio/iio.h>
22 #include <linux/iio/sysfs.h>
23 #include <linux/iio/trigger.h>
24 #include <linux/iio/trigger_consumer.h>
25 #include <linux/iio/triggered_buffer.h>
26 #include <linux/interrupt.h>
27 #include <linux/module.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/random.h>
30 #include <linux/slab.h>
31
32 #include "mpu3050.h"
33
34 #define MPU3050_CHIP_ID 0x68
35 #define MPU3050_CHIP_ID_MASK 0x7E
36
37 /*
38 * Register map: anything suffixed *_H is a big-endian high byte and always
39 * followed by the corresponding low byte (*_L) even though these are not
40 * explicitly included in the register definitions.
41 */
42 #define MPU3050_CHIP_ID_REG 0x00
43 #define MPU3050_PRODUCT_ID_REG 0x01
44 #define MPU3050_XG_OFFS_TC 0x05
45 #define MPU3050_YG_OFFS_TC 0x08
46 #define MPU3050_ZG_OFFS_TC 0x0B
47 #define MPU3050_X_OFFS_USR_H 0x0C
48 #define MPU3050_Y_OFFS_USR_H 0x0E
49 #define MPU3050_Z_OFFS_USR_H 0x10
50 #define MPU3050_FIFO_EN 0x12
51 #define MPU3050_AUX_VDDIO 0x13
52 #define MPU3050_SLV_ADDR 0x14
53 #define MPU3050_SMPLRT_DIV 0x15
54 #define MPU3050_DLPF_FS_SYNC 0x16
55 #define MPU3050_INT_CFG 0x17
56 #define MPU3050_AUX_ADDR 0x18
57 #define MPU3050_INT_STATUS 0x1A
58 #define MPU3050_TEMP_H 0x1B
59 #define MPU3050_XOUT_H 0x1D
60 #define MPU3050_YOUT_H 0x1F
61 #define MPU3050_ZOUT_H 0x21
62 #define MPU3050_DMP_CFG1 0x35
63 #define MPU3050_DMP_CFG2 0x36
64 #define MPU3050_BANK_SEL 0x37
65 #define MPU3050_MEM_START_ADDR 0x38
66 #define MPU3050_MEM_R_W 0x39
67 #define MPU3050_FIFO_COUNT_H 0x3A
68 #define MPU3050_FIFO_R 0x3C
69 #define MPU3050_USR_CTRL 0x3D
70 #define MPU3050_PWR_MGM 0x3E
71
72 /* MPU memory bank read options */
73 #define MPU3050_MEM_PRFTCH BIT(5)
74 #define MPU3050_MEM_USER_BANK BIT(4)
75 /* Bits 8-11 select memory bank */
76 #define MPU3050_MEM_RAM_BANK_0 0
77 #define MPU3050_MEM_RAM_BANK_1 1
78 #define MPU3050_MEM_RAM_BANK_2 2
79 #define MPU3050_MEM_RAM_BANK_3 3
80 #define MPU3050_MEM_OTP_BANK_0 4
81
82 #define MPU3050_AXIS_REGS(axis) (MPU3050_XOUT_H + (axis * 2))
83
84 /* Register bits */
85
86 /* FIFO Enable */
87 #define MPU3050_FIFO_EN_FOOTER BIT(0)
88 #define MPU3050_FIFO_EN_AUX_ZOUT BIT(1)
89 #define MPU3050_FIFO_EN_AUX_YOUT BIT(2)
90 #define MPU3050_FIFO_EN_AUX_XOUT BIT(3)
91 #define MPU3050_FIFO_EN_GYRO_ZOUT BIT(4)
92 #define MPU3050_FIFO_EN_GYRO_YOUT BIT(5)
93 #define MPU3050_FIFO_EN_GYRO_XOUT BIT(6)
94 #define MPU3050_FIFO_EN_TEMP_OUT BIT(7)
95
96 /*
97 * Digital Low Pass filter (DLPF)
98 * Full Scale (FS)
99 * and Synchronization
100 */
101 #define MPU3050_EXT_SYNC_NONE 0x00
102 #define MPU3050_EXT_SYNC_TEMP 0x20
103 #define MPU3050_EXT_SYNC_GYROX 0x40
104 #define MPU3050_EXT_SYNC_GYROY 0x60
105 #define MPU3050_EXT_SYNC_GYROZ 0x80
106 #define MPU3050_EXT_SYNC_ACCELX 0xA0
107 #define MPU3050_EXT_SYNC_ACCELY 0xC0
108 #define MPU3050_EXT_SYNC_ACCELZ 0xE0
109 #define MPU3050_EXT_SYNC_MASK 0xE0
110 #define MPU3050_EXT_SYNC_SHIFT 5
111
112 #define MPU3050_FS_250DPS 0x00
113 #define MPU3050_FS_500DPS 0x08
114 #define MPU3050_FS_1000DPS 0x10
115 #define MPU3050_FS_2000DPS 0x18
116 #define MPU3050_FS_MASK 0x18
117 #define MPU3050_FS_SHIFT 3
118
119 #define MPU3050_DLPF_CFG_256HZ_NOLPF2 0x00
120 #define MPU3050_DLPF_CFG_188HZ 0x01
121 #define MPU3050_DLPF_CFG_98HZ 0x02
122 #define MPU3050_DLPF_CFG_42HZ 0x03
123 #define MPU3050_DLPF_CFG_20HZ 0x04
124 #define MPU3050_DLPF_CFG_10HZ 0x05
125 #define MPU3050_DLPF_CFG_5HZ 0x06
126 #define MPU3050_DLPF_CFG_2100HZ_NOLPF 0x07
127 #define MPU3050_DLPF_CFG_MASK 0x07
128 #define MPU3050_DLPF_CFG_SHIFT 0
129
130 /* Interrupt config */
131 #define MPU3050_INT_RAW_RDY_EN BIT(0)
132 #define MPU3050_INT_DMP_DONE_EN BIT(1)
133 #define MPU3050_INT_MPU_RDY_EN BIT(2)
134 #define MPU3050_INT_ANYRD_2CLEAR BIT(4)
135 #define MPU3050_INT_LATCH_EN BIT(5)
136 #define MPU3050_INT_OPEN BIT(6)
137 #define MPU3050_INT_ACTL BIT(7)
138 /* Interrupt status */
139 #define MPU3050_INT_STATUS_RAW_RDY BIT(0)
140 #define MPU3050_INT_STATUS_DMP_DONE BIT(1)
141 #define MPU3050_INT_STATUS_MPU_RDY BIT(2)
142 #define MPU3050_INT_STATUS_FIFO_OVFLW BIT(7)
143 /* USR_CTRL */
144 #define MPU3050_USR_CTRL_FIFO_EN BIT(6)
145 #define MPU3050_USR_CTRL_AUX_IF_EN BIT(5)
146 #define MPU3050_USR_CTRL_AUX_IF_RST BIT(3)
147 #define MPU3050_USR_CTRL_FIFO_RST BIT(1)
148 #define MPU3050_USR_CTRL_GYRO_RST BIT(0)
149 /* PWR_MGM */
150 #define MPU3050_PWR_MGM_PLL_X 0x01
151 #define MPU3050_PWR_MGM_PLL_Y 0x02
152 #define MPU3050_PWR_MGM_PLL_Z 0x03
153 #define MPU3050_PWR_MGM_CLKSEL_MASK 0x07
154 #define MPU3050_PWR_MGM_STBY_ZG BIT(3)
155 #define MPU3050_PWR_MGM_STBY_YG BIT(4)
156 #define MPU3050_PWR_MGM_STBY_XG BIT(5)
157 #define MPU3050_PWR_MGM_SLEEP BIT(6)
158 #define MPU3050_PWR_MGM_RESET BIT(7)
159 #define MPU3050_PWR_MGM_MASK 0xff
160
161 /*
162 * Fullscale precision is (for finest precision) +/- 250 deg/s, so the full
163 * scale is actually 500 deg/s. All 16 bits are then used to cover this scale,
164 * in two's complement.
165 */
166 static unsigned int mpu3050_fs_precision[] = {
167 IIO_DEGREE_TO_RAD(250),
168 IIO_DEGREE_TO_RAD(500),
169 IIO_DEGREE_TO_RAD(1000),
170 IIO_DEGREE_TO_RAD(2000)
171 };
172
173 /*
174 * Regulator names
175 */
176 static const char mpu3050_reg_vdd[] = "vdd";
177 static const char mpu3050_reg_vlogic[] = "vlogic";
178
mpu3050_get_freq(struct mpu3050 * mpu3050)179 static unsigned int mpu3050_get_freq(struct mpu3050 *mpu3050)
180 {
181 unsigned int freq;
182
183 if (mpu3050->lpf == MPU3050_DLPF_CFG_256HZ_NOLPF2)
184 freq = 8000;
185 else
186 freq = 1000;
187 freq /= (mpu3050->divisor + 1);
188
189 return freq;
190 }
191
mpu3050_start_sampling(struct mpu3050 * mpu3050)192 static int mpu3050_start_sampling(struct mpu3050 *mpu3050)
193 {
194 __be16 raw_val[3];
195 int ret;
196 int i;
197
198 /* Reset */
199 ret = regmap_update_bits(mpu3050->map, MPU3050_PWR_MGM,
200 MPU3050_PWR_MGM_RESET, MPU3050_PWR_MGM_RESET);
201 if (ret)
202 return ret;
203
204 /* Turn on the Z-axis PLL */
205 ret = regmap_update_bits(mpu3050->map, MPU3050_PWR_MGM,
206 MPU3050_PWR_MGM_CLKSEL_MASK,
207 MPU3050_PWR_MGM_PLL_Z);
208 if (ret)
209 return ret;
210
211 /* Write calibration offset registers */
212 for (i = 0; i < 3; i++)
213 raw_val[i] = cpu_to_be16(mpu3050->calibration[i]);
214
215 ret = regmap_bulk_write(mpu3050->map, MPU3050_X_OFFS_USR_H, raw_val,
216 sizeof(raw_val));
217 if (ret)
218 return ret;
219
220 /* Set low pass filter (sample rate), sync and full scale */
221 ret = regmap_write(mpu3050->map, MPU3050_DLPF_FS_SYNC,
222 MPU3050_EXT_SYNC_NONE << MPU3050_EXT_SYNC_SHIFT |
223 mpu3050->fullscale << MPU3050_FS_SHIFT |
224 mpu3050->lpf << MPU3050_DLPF_CFG_SHIFT);
225 if (ret)
226 return ret;
227
228 /* Set up sampling frequency */
229 ret = regmap_write(mpu3050->map, MPU3050_SMPLRT_DIV, mpu3050->divisor);
230 if (ret)
231 return ret;
232
233 /*
234 * Max 50 ms start-up time after setting DLPF_FS_SYNC
235 * according to the data sheet, then wait for the next sample
236 * at this frequency T = 1000/f ms.
237 */
238 msleep(50 + 1000 / mpu3050_get_freq(mpu3050));
239
240 return 0;
241 }
242
mpu3050_set_8khz_samplerate(struct mpu3050 * mpu3050)243 static int mpu3050_set_8khz_samplerate(struct mpu3050 *mpu3050)
244 {
245 int ret;
246 u8 divisor;
247 enum mpu3050_lpf lpf;
248
249 lpf = mpu3050->lpf;
250 divisor = mpu3050->divisor;
251
252 mpu3050->lpf = LPF_256_HZ_NOLPF; /* 8 kHz base frequency */
253 mpu3050->divisor = 0; /* Divide by 1 */
254 ret = mpu3050_start_sampling(mpu3050);
255
256 mpu3050->lpf = lpf;
257 mpu3050->divisor = divisor;
258
259 return ret;
260 }
261
mpu3050_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)262 static int mpu3050_read_raw(struct iio_dev *indio_dev,
263 struct iio_chan_spec const *chan,
264 int *val, int *val2,
265 long mask)
266 {
267 struct mpu3050 *mpu3050 = iio_priv(indio_dev);
268 int ret;
269 __be16 raw_val;
270
271 switch (mask) {
272 case IIO_CHAN_INFO_OFFSET:
273 switch (chan->type) {
274 case IIO_TEMP:
275 /*
276 * The temperature scaling is (x+23000)/280 Celsius
277 * for the "best fit straight line" temperature range
278 * of -30C..85C. The 23000 includes room temperature
279 * offset of +35C, 280 is the precision scale and x is
280 * the 16-bit signed integer reported by hardware.
281 *
282 * Temperature value itself represents temperature of
283 * the sensor die.
284 */
285 *val = 23000;
286 return IIO_VAL_INT;
287 default:
288 return -EINVAL;
289 }
290 case IIO_CHAN_INFO_CALIBBIAS:
291 switch (chan->type) {
292 case IIO_ANGL_VEL:
293 *val = mpu3050->calibration[chan->scan_index-1];
294 return IIO_VAL_INT;
295 default:
296 return -EINVAL;
297 }
298 case IIO_CHAN_INFO_SAMP_FREQ:
299 *val = mpu3050_get_freq(mpu3050);
300 return IIO_VAL_INT;
301 case IIO_CHAN_INFO_SCALE:
302 switch (chan->type) {
303 case IIO_TEMP:
304 /* Millidegrees, see about temperature scaling above */
305 *val = 1000;
306 *val2 = 280;
307 return IIO_VAL_FRACTIONAL;
308 case IIO_ANGL_VEL:
309 /*
310 * Convert to the corresponding full scale in
311 * radians. All 16 bits are used with sign to
312 * span the available scale: to account for the one
313 * missing value if we multiply by 1/S16_MAX, instead
314 * multiply with 2/U16_MAX.
315 */
316 *val = mpu3050_fs_precision[mpu3050->fullscale] * 2;
317 *val2 = U16_MAX;
318 return IIO_VAL_FRACTIONAL;
319 default:
320 return -EINVAL;
321 }
322 case IIO_CHAN_INFO_RAW:
323 /* Resume device */
324 pm_runtime_get_sync(mpu3050->dev);
325 mutex_lock(&mpu3050->lock);
326
327 ret = mpu3050_set_8khz_samplerate(mpu3050);
328 if (ret)
329 goto out_read_raw_unlock;
330
331 switch (chan->type) {
332 case IIO_TEMP:
333 ret = regmap_bulk_read(mpu3050->map, MPU3050_TEMP_H,
334 &raw_val, sizeof(raw_val));
335 if (ret) {
336 dev_err(mpu3050->dev,
337 "error reading temperature\n");
338 goto out_read_raw_unlock;
339 }
340
341 *val = (s16)be16_to_cpu(raw_val);
342 ret = IIO_VAL_INT;
343
344 goto out_read_raw_unlock;
345 case IIO_ANGL_VEL:
346 ret = regmap_bulk_read(mpu3050->map,
347 MPU3050_AXIS_REGS(chan->scan_index-1),
348 &raw_val,
349 sizeof(raw_val));
350 if (ret) {
351 dev_err(mpu3050->dev,
352 "error reading axis data\n");
353 goto out_read_raw_unlock;
354 }
355
356 *val = be16_to_cpu(raw_val);
357 ret = IIO_VAL_INT;
358
359 goto out_read_raw_unlock;
360 default:
361 ret = -EINVAL;
362 goto out_read_raw_unlock;
363 }
364 default:
365 break;
366 }
367
368 return -EINVAL;
369
370 out_read_raw_unlock:
371 mutex_unlock(&mpu3050->lock);
372 pm_runtime_mark_last_busy(mpu3050->dev);
373 pm_runtime_put_autosuspend(mpu3050->dev);
374
375 return ret;
376 }
377
mpu3050_write_raw(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,int val,int val2,long mask)378 static int mpu3050_write_raw(struct iio_dev *indio_dev,
379 const struct iio_chan_spec *chan,
380 int val, int val2, long mask)
381 {
382 struct mpu3050 *mpu3050 = iio_priv(indio_dev);
383 /*
384 * Couldn't figure out a way to precalculate these at compile time.
385 */
386 unsigned int fs250 =
387 DIV_ROUND_CLOSEST(mpu3050_fs_precision[0] * 1000000 * 2,
388 U16_MAX);
389 unsigned int fs500 =
390 DIV_ROUND_CLOSEST(mpu3050_fs_precision[1] * 1000000 * 2,
391 U16_MAX);
392 unsigned int fs1000 =
393 DIV_ROUND_CLOSEST(mpu3050_fs_precision[2] * 1000000 * 2,
394 U16_MAX);
395 unsigned int fs2000 =
396 DIV_ROUND_CLOSEST(mpu3050_fs_precision[3] * 1000000 * 2,
397 U16_MAX);
398
399 switch (mask) {
400 case IIO_CHAN_INFO_CALIBBIAS:
401 if (chan->type != IIO_ANGL_VEL)
402 return -EINVAL;
403 mpu3050->calibration[chan->scan_index-1] = val;
404 return 0;
405 case IIO_CHAN_INFO_SAMP_FREQ:
406 /*
407 * The max samplerate is 8000 Hz, the minimum
408 * 1000 / 256 ~= 4 Hz
409 */
410 if (val < 4 || val > 8000)
411 return -EINVAL;
412
413 /*
414 * Above 1000 Hz we must turn off the digital low pass filter
415 * so we get a base frequency of 8kHz to the divider
416 */
417 if (val > 1000) {
418 mpu3050->lpf = LPF_256_HZ_NOLPF;
419 mpu3050->divisor = DIV_ROUND_CLOSEST(8000, val) - 1;
420 return 0;
421 }
422
423 mpu3050->lpf = LPF_188_HZ;
424 mpu3050->divisor = DIV_ROUND_CLOSEST(1000, val) - 1;
425 return 0;
426 case IIO_CHAN_INFO_SCALE:
427 if (chan->type != IIO_ANGL_VEL)
428 return -EINVAL;
429 /*
430 * We support +/-250, +/-500, +/-1000 and +/2000 deg/s
431 * which means we need to round to the closest radians
432 * which will be roughly +/-4.3, +/-8.7, +/-17.5, +/-35
433 * rad/s. The scale is then for the 16 bits used to cover
434 * it 2/(2^16) of that.
435 */
436
437 /* Just too large, set the max range */
438 if (val != 0) {
439 mpu3050->fullscale = FS_2000_DPS;
440 return 0;
441 }
442
443 /*
444 * Now we're dealing with fractions below zero in millirad/s
445 * do some integer interpolation and match with the closest
446 * fullscale in the table.
447 */
448 if (val2 <= fs250 ||
449 val2 < ((fs500 + fs250) / 2))
450 mpu3050->fullscale = FS_250_DPS;
451 else if (val2 <= fs500 ||
452 val2 < ((fs1000 + fs500) / 2))
453 mpu3050->fullscale = FS_500_DPS;
454 else if (val2 <= fs1000 ||
455 val2 < ((fs2000 + fs1000) / 2))
456 mpu3050->fullscale = FS_1000_DPS;
457 else
458 /* Catch-all */
459 mpu3050->fullscale = FS_2000_DPS;
460 return 0;
461 default:
462 break;
463 }
464
465 return -EINVAL;
466 }
467
mpu3050_trigger_handler(int irq,void * p)468 static irqreturn_t mpu3050_trigger_handler(int irq, void *p)
469 {
470 const struct iio_poll_func *pf = p;
471 struct iio_dev *indio_dev = pf->indio_dev;
472 struct mpu3050 *mpu3050 = iio_priv(indio_dev);
473 int ret;
474 struct {
475 __be16 chans[4];
476 s64 timestamp __aligned(8);
477 } scan;
478 s64 timestamp;
479 unsigned int datums_from_fifo = 0;
480
481 /*
482 * If we're using the hardware trigger, get the precise timestamp from
483 * the top half of the threaded IRQ handler. Otherwise get the
484 * timestamp here so it will be close in time to the actual values
485 * read from the registers.
486 */
487 if (iio_trigger_using_own(indio_dev))
488 timestamp = mpu3050->hw_timestamp;
489 else
490 timestamp = iio_get_time_ns(indio_dev);
491
492 mutex_lock(&mpu3050->lock);
493
494 /* Using the hardware IRQ trigger? Check the buffer then. */
495 if (mpu3050->hw_irq_trigger) {
496 __be16 raw_fifocnt;
497 u16 fifocnt;
498 /* X, Y, Z + temperature */
499 unsigned int bytes_per_datum = 8;
500 bool fifo_overflow = false;
501
502 ret = regmap_bulk_read(mpu3050->map,
503 MPU3050_FIFO_COUNT_H,
504 &raw_fifocnt,
505 sizeof(raw_fifocnt));
506 if (ret)
507 goto out_trigger_unlock;
508 fifocnt = be16_to_cpu(raw_fifocnt);
509
510 if (fifocnt == 512) {
511 dev_info(mpu3050->dev,
512 "FIFO overflow! Emptying and resetting FIFO\n");
513 fifo_overflow = true;
514 /* Reset and enable the FIFO */
515 ret = regmap_update_bits(mpu3050->map,
516 MPU3050_USR_CTRL,
517 MPU3050_USR_CTRL_FIFO_EN |
518 MPU3050_USR_CTRL_FIFO_RST,
519 MPU3050_USR_CTRL_FIFO_EN |
520 MPU3050_USR_CTRL_FIFO_RST);
521 if (ret) {
522 dev_info(mpu3050->dev, "error resetting FIFO\n");
523 goto out_trigger_unlock;
524 }
525 mpu3050->pending_fifo_footer = false;
526 }
527
528 if (fifocnt)
529 dev_dbg(mpu3050->dev,
530 "%d bytes in the FIFO\n",
531 fifocnt);
532
533 while (!fifo_overflow && fifocnt > bytes_per_datum) {
534 unsigned int toread;
535 unsigned int offset;
536 __be16 fifo_values[5];
537
538 /*
539 * If there is a FIFO footer in the pipe, first clear
540 * that out. This follows the complex algorithm in the
541 * datasheet that states that you may never leave the
542 * FIFO empty after the first reading: you have to
543 * always leave two footer bytes in it. The footer is
544 * in practice just two zero bytes.
545 */
546 if (mpu3050->pending_fifo_footer) {
547 toread = bytes_per_datum + 2;
548 offset = 0;
549 } else {
550 toread = bytes_per_datum;
551 offset = 1;
552 /* Put in some dummy value */
553 fifo_values[0] = cpu_to_be16(0xAAAA);
554 }
555
556 ret = regmap_bulk_read(mpu3050->map,
557 MPU3050_FIFO_R,
558 &fifo_values[offset],
559 toread);
560 if (ret)
561 goto out_trigger_unlock;
562
563 dev_dbg(mpu3050->dev,
564 "%04x %04x %04x %04x %04x\n",
565 fifo_values[0],
566 fifo_values[1],
567 fifo_values[2],
568 fifo_values[3],
569 fifo_values[4]);
570
571 /* Index past the footer (fifo_values[0]) and push */
572 iio_push_to_buffers_with_ts_unaligned(indio_dev,
573 &fifo_values[1],
574 sizeof(__be16) * 4,
575 timestamp);
576
577 fifocnt -= toread;
578 datums_from_fifo++;
579 mpu3050->pending_fifo_footer = true;
580
581 /*
582 * If we're emptying the FIFO, just make sure to
583 * check if something new appeared.
584 */
585 if (fifocnt < bytes_per_datum) {
586 ret = regmap_bulk_read(mpu3050->map,
587 MPU3050_FIFO_COUNT_H,
588 &raw_fifocnt,
589 sizeof(raw_fifocnt));
590 if (ret)
591 goto out_trigger_unlock;
592 fifocnt = be16_to_cpu(raw_fifocnt);
593 }
594
595 if (fifocnt < bytes_per_datum)
596 dev_dbg(mpu3050->dev,
597 "%d bytes left in the FIFO\n",
598 fifocnt);
599
600 /*
601 * At this point, the timestamp that triggered the
602 * hardware interrupt is no longer valid for what
603 * we are reading (the interrupt likely fired for
604 * the value on the top of the FIFO), so set the
605 * timestamp to zero and let userspace deal with it.
606 */
607 timestamp = 0;
608 }
609 }
610
611 /*
612 * If we picked some datums from the FIFO that's enough, else
613 * fall through and just read from the current value registers.
614 * This happens in two cases:
615 *
616 * - We are using some other trigger (external, like an HRTimer)
617 * than the sensor's own sample generator. In this case the
618 * sensor is just set to the max sampling frequency and we give
619 * the trigger a copy of the latest value every time we get here.
620 *
621 * - The hardware trigger is active but unused and we actually use
622 * another trigger which calls here with a frequency higher
623 * than what the device provides data. We will then just read
624 * duplicate values directly from the hardware registers.
625 */
626 if (datums_from_fifo) {
627 dev_dbg(mpu3050->dev,
628 "read %d datums from the FIFO\n",
629 datums_from_fifo);
630 goto out_trigger_unlock;
631 }
632
633 ret = regmap_bulk_read(mpu3050->map, MPU3050_TEMP_H, scan.chans,
634 sizeof(scan.chans));
635 if (ret) {
636 dev_err(mpu3050->dev,
637 "error reading axis data\n");
638 goto out_trigger_unlock;
639 }
640
641 iio_push_to_buffers_with_timestamp(indio_dev, &scan, timestamp);
642
643 out_trigger_unlock:
644 mutex_unlock(&mpu3050->lock);
645 iio_trigger_notify_done(indio_dev->trig);
646
647 return IRQ_HANDLED;
648 }
649
mpu3050_buffer_preenable(struct iio_dev * indio_dev)650 static int mpu3050_buffer_preenable(struct iio_dev *indio_dev)
651 {
652 struct mpu3050 *mpu3050 = iio_priv(indio_dev);
653
654 pm_runtime_get_sync(mpu3050->dev);
655
656 /* Unless we have OUR trigger active, run at full speed */
657 if (!mpu3050->hw_irq_trigger)
658 return mpu3050_set_8khz_samplerate(mpu3050);
659
660 return 0;
661 }
662
mpu3050_buffer_postdisable(struct iio_dev * indio_dev)663 static int mpu3050_buffer_postdisable(struct iio_dev *indio_dev)
664 {
665 struct mpu3050 *mpu3050 = iio_priv(indio_dev);
666
667 pm_runtime_mark_last_busy(mpu3050->dev);
668 pm_runtime_put_autosuspend(mpu3050->dev);
669
670 return 0;
671 }
672
673 static const struct iio_buffer_setup_ops mpu3050_buffer_setup_ops = {
674 .preenable = mpu3050_buffer_preenable,
675 .postdisable = mpu3050_buffer_postdisable,
676 };
677
678 static const struct iio_mount_matrix *
mpu3050_get_mount_matrix(const struct iio_dev * indio_dev,const struct iio_chan_spec * chan)679 mpu3050_get_mount_matrix(const struct iio_dev *indio_dev,
680 const struct iio_chan_spec *chan)
681 {
682 struct mpu3050 *mpu3050 = iio_priv(indio_dev);
683
684 return &mpu3050->orientation;
685 }
686
687 static const struct iio_chan_spec_ext_info mpu3050_ext_info[] = {
688 IIO_MOUNT_MATRIX(IIO_SHARED_BY_TYPE, mpu3050_get_mount_matrix),
689 { },
690 };
691
692 #define MPU3050_AXIS_CHANNEL(axis, index) \
693 { \
694 .type = IIO_ANGL_VEL, \
695 .modified = 1, \
696 .channel2 = IIO_MOD_##axis, \
697 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
698 BIT(IIO_CHAN_INFO_CALIBBIAS), \
699 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
700 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),\
701 .ext_info = mpu3050_ext_info, \
702 .scan_index = index, \
703 .scan_type = { \
704 .sign = 's', \
705 .realbits = 16, \
706 .storagebits = 16, \
707 .endianness = IIO_BE, \
708 }, \
709 }
710
711 static const struct iio_chan_spec mpu3050_channels[] = {
712 {
713 .type = IIO_TEMP,
714 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
715 BIT(IIO_CHAN_INFO_SCALE) |
716 BIT(IIO_CHAN_INFO_OFFSET),
717 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),
718 .scan_index = 0,
719 .scan_type = {
720 .sign = 's',
721 .realbits = 16,
722 .storagebits = 16,
723 .endianness = IIO_BE,
724 },
725 },
726 MPU3050_AXIS_CHANNEL(X, 1),
727 MPU3050_AXIS_CHANNEL(Y, 2),
728 MPU3050_AXIS_CHANNEL(Z, 3),
729 IIO_CHAN_SOFT_TIMESTAMP(4),
730 };
731
732 /* Four channels apart from timestamp, scan mask = 0x0f */
733 static const unsigned long mpu3050_scan_masks[] = { 0xf, 0 };
734
735 /*
736 * These are just the hardcoded factors resulting from the more elaborate
737 * calculations done with fractions in the scale raw get/set functions.
738 */
739 static IIO_CONST_ATTR(anglevel_scale_available,
740 "0.000122070 "
741 "0.000274658 "
742 "0.000518798 "
743 "0.001068115");
744
745 static struct attribute *mpu3050_attributes[] = {
746 &iio_const_attr_anglevel_scale_available.dev_attr.attr,
747 NULL,
748 };
749
750 static const struct attribute_group mpu3050_attribute_group = {
751 .attrs = mpu3050_attributes,
752 };
753
754 static const struct iio_info mpu3050_info = {
755 .read_raw = mpu3050_read_raw,
756 .write_raw = mpu3050_write_raw,
757 .attrs = &mpu3050_attribute_group,
758 };
759
760 /**
761 * mpu3050_read_mem() - read MPU-3050 internal memory
762 * @mpu3050: device to read from
763 * @bank: target bank
764 * @addr: target address
765 * @len: number of bytes
766 * @buf: the buffer to store the read bytes in
767 */
mpu3050_read_mem(struct mpu3050 * mpu3050,u8 bank,u8 addr,u8 len,u8 * buf)768 static int mpu3050_read_mem(struct mpu3050 *mpu3050,
769 u8 bank,
770 u8 addr,
771 u8 len,
772 u8 *buf)
773 {
774 int ret;
775
776 ret = regmap_write(mpu3050->map,
777 MPU3050_BANK_SEL,
778 bank);
779 if (ret)
780 return ret;
781
782 ret = regmap_write(mpu3050->map,
783 MPU3050_MEM_START_ADDR,
784 addr);
785 if (ret)
786 return ret;
787
788 return regmap_bulk_read(mpu3050->map,
789 MPU3050_MEM_R_W,
790 buf,
791 len);
792 }
793
mpu3050_hw_init(struct mpu3050 * mpu3050)794 static int mpu3050_hw_init(struct mpu3050 *mpu3050)
795 {
796 int ret;
797 __le64 otp_le;
798 u64 otp;
799
800 /* Reset */
801 ret = regmap_update_bits(mpu3050->map,
802 MPU3050_PWR_MGM,
803 MPU3050_PWR_MGM_RESET,
804 MPU3050_PWR_MGM_RESET);
805 if (ret)
806 return ret;
807
808 /* Turn on the PLL */
809 ret = regmap_update_bits(mpu3050->map,
810 MPU3050_PWR_MGM,
811 MPU3050_PWR_MGM_CLKSEL_MASK,
812 MPU3050_PWR_MGM_PLL_Z);
813 if (ret)
814 return ret;
815
816 /* Disable IRQs */
817 ret = regmap_write(mpu3050->map,
818 MPU3050_INT_CFG,
819 0);
820 if (ret)
821 return ret;
822
823 /* Read out the 8 bytes of OTP (one-time-programmable) memory */
824 ret = mpu3050_read_mem(mpu3050,
825 (MPU3050_MEM_PRFTCH |
826 MPU3050_MEM_USER_BANK |
827 MPU3050_MEM_OTP_BANK_0),
828 0,
829 sizeof(otp_le),
830 (u8 *)&otp_le);
831 if (ret)
832 return ret;
833
834 /* This is device-unique data so it goes into the entropy pool */
835 add_device_randomness(&otp_le, sizeof(otp_le));
836
837 otp = le64_to_cpu(otp_le);
838
839 dev_info(mpu3050->dev,
840 "die ID: %04llX, wafer ID: %02llX, A lot ID: %04llX, "
841 "W lot ID: %03llX, WP ID: %01llX, rev ID: %02llX\n",
842 /* Die ID, bits 0-12 */
843 FIELD_GET(GENMASK_ULL(12, 0), otp),
844 /* Wafer ID, bits 13-17 */
845 FIELD_GET(GENMASK_ULL(17, 13), otp),
846 /* A lot ID, bits 18-33 */
847 FIELD_GET(GENMASK_ULL(33, 18), otp),
848 /* W lot ID, bits 34-45 */
849 FIELD_GET(GENMASK_ULL(45, 34), otp),
850 /* WP ID, bits 47-49 */
851 FIELD_GET(GENMASK_ULL(49, 47), otp),
852 /* rev ID, bits 50-55 */
853 FIELD_GET(GENMASK_ULL(55, 50), otp));
854
855 return 0;
856 }
857
mpu3050_power_up(struct mpu3050 * mpu3050)858 static int mpu3050_power_up(struct mpu3050 *mpu3050)
859 {
860 int ret;
861
862 ret = regulator_bulk_enable(ARRAY_SIZE(mpu3050->regs), mpu3050->regs);
863 if (ret) {
864 dev_err(mpu3050->dev, "cannot enable regulators\n");
865 return ret;
866 }
867 /*
868 * 20-100 ms start-up time for register read/write according to
869 * the datasheet, be on the safe side and wait 200 ms.
870 */
871 msleep(200);
872
873 /* Take device out of sleep mode */
874 ret = regmap_update_bits(mpu3050->map, MPU3050_PWR_MGM,
875 MPU3050_PWR_MGM_SLEEP, 0);
876 if (ret) {
877 dev_err(mpu3050->dev, "error setting power mode\n");
878 return ret;
879 }
880 usleep_range(10000, 20000);
881
882 return 0;
883 }
884
mpu3050_power_down(struct mpu3050 * mpu3050)885 static int mpu3050_power_down(struct mpu3050 *mpu3050)
886 {
887 int ret;
888
889 /*
890 * Put MPU-3050 into sleep mode before cutting regulators.
891 * This is important, because we may not be the sole user
892 * of the regulator so the power may stay on after this, and
893 * then we would be wasting power unless we go to sleep mode
894 * first.
895 */
896 ret = regmap_update_bits(mpu3050->map, MPU3050_PWR_MGM,
897 MPU3050_PWR_MGM_SLEEP, MPU3050_PWR_MGM_SLEEP);
898 if (ret)
899 dev_err(mpu3050->dev, "error putting to sleep\n");
900
901 ret = regulator_bulk_disable(ARRAY_SIZE(mpu3050->regs), mpu3050->regs);
902 if (ret)
903 dev_err(mpu3050->dev, "error disabling regulators\n");
904
905 return 0;
906 }
907
mpu3050_irq_handler(int irq,void * p)908 static irqreturn_t mpu3050_irq_handler(int irq, void *p)
909 {
910 struct iio_trigger *trig = p;
911 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
912 struct mpu3050 *mpu3050 = iio_priv(indio_dev);
913
914 if (!mpu3050->hw_irq_trigger)
915 return IRQ_NONE;
916
917 /* Get the time stamp as close in time as possible */
918 mpu3050->hw_timestamp = iio_get_time_ns(indio_dev);
919
920 return IRQ_WAKE_THREAD;
921 }
922
mpu3050_irq_thread(int irq,void * p)923 static irqreturn_t mpu3050_irq_thread(int irq, void *p)
924 {
925 struct iio_trigger *trig = p;
926 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
927 struct mpu3050 *mpu3050 = iio_priv(indio_dev);
928 unsigned int val;
929 int ret;
930
931 /* ACK IRQ and check if it was from us */
932 ret = regmap_read(mpu3050->map, MPU3050_INT_STATUS, &val);
933 if (ret) {
934 dev_err(mpu3050->dev, "error reading IRQ status\n");
935 return IRQ_HANDLED;
936 }
937 if (!(val & MPU3050_INT_STATUS_RAW_RDY))
938 return IRQ_NONE;
939
940 iio_trigger_poll_chained(p);
941
942 return IRQ_HANDLED;
943 }
944
945 /**
946 * mpu3050_drdy_trigger_set_state() - set data ready interrupt state
947 * @trig: trigger instance
948 * @enable: true if trigger should be enabled, false to disable
949 */
mpu3050_drdy_trigger_set_state(struct iio_trigger * trig,bool enable)950 static int mpu3050_drdy_trigger_set_state(struct iio_trigger *trig,
951 bool enable)
952 {
953 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
954 struct mpu3050 *mpu3050 = iio_priv(indio_dev);
955 unsigned int val;
956 int ret;
957
958 /* Disabling trigger: disable interrupt and return */
959 if (!enable) {
960 /* Disable all interrupts */
961 ret = regmap_write(mpu3050->map,
962 MPU3050_INT_CFG,
963 0);
964 if (ret)
965 dev_err(mpu3050->dev, "error disabling IRQ\n");
966
967 /* Clear IRQ flag */
968 ret = regmap_read(mpu3050->map, MPU3050_INT_STATUS, &val);
969 if (ret)
970 dev_err(mpu3050->dev, "error clearing IRQ status\n");
971
972 /* Disable all things in the FIFO and reset it */
973 ret = regmap_write(mpu3050->map, MPU3050_FIFO_EN, 0);
974 if (ret)
975 dev_err(mpu3050->dev, "error disabling FIFO\n");
976
977 ret = regmap_write(mpu3050->map, MPU3050_USR_CTRL,
978 MPU3050_USR_CTRL_FIFO_RST);
979 if (ret)
980 dev_err(mpu3050->dev, "error resetting FIFO\n");
981
982 pm_runtime_mark_last_busy(mpu3050->dev);
983 pm_runtime_put_autosuspend(mpu3050->dev);
984 mpu3050->hw_irq_trigger = false;
985
986 return 0;
987 } else {
988 /* Else we're enabling the trigger from this point */
989 pm_runtime_get_sync(mpu3050->dev);
990 mpu3050->hw_irq_trigger = true;
991
992 /* Disable all things in the FIFO */
993 ret = regmap_write(mpu3050->map, MPU3050_FIFO_EN, 0);
994 if (ret)
995 return ret;
996
997 /* Reset and enable the FIFO */
998 ret = regmap_update_bits(mpu3050->map, MPU3050_USR_CTRL,
999 MPU3050_USR_CTRL_FIFO_EN |
1000 MPU3050_USR_CTRL_FIFO_RST,
1001 MPU3050_USR_CTRL_FIFO_EN |
1002 MPU3050_USR_CTRL_FIFO_RST);
1003 if (ret)
1004 return ret;
1005
1006 mpu3050->pending_fifo_footer = false;
1007
1008 /* Turn on the FIFO for temp+X+Y+Z */
1009 ret = regmap_write(mpu3050->map, MPU3050_FIFO_EN,
1010 MPU3050_FIFO_EN_TEMP_OUT |
1011 MPU3050_FIFO_EN_GYRO_XOUT |
1012 MPU3050_FIFO_EN_GYRO_YOUT |
1013 MPU3050_FIFO_EN_GYRO_ZOUT |
1014 MPU3050_FIFO_EN_FOOTER);
1015 if (ret)
1016 return ret;
1017
1018 /* Configure the sample engine */
1019 ret = mpu3050_start_sampling(mpu3050);
1020 if (ret)
1021 return ret;
1022
1023 /* Clear IRQ flag */
1024 ret = regmap_read(mpu3050->map, MPU3050_INT_STATUS, &val);
1025 if (ret)
1026 dev_err(mpu3050->dev, "error clearing IRQ status\n");
1027
1028 /* Give us interrupts whenever there is new data ready */
1029 val = MPU3050_INT_RAW_RDY_EN;
1030
1031 if (mpu3050->irq_actl)
1032 val |= MPU3050_INT_ACTL;
1033 if (mpu3050->irq_latch)
1034 val |= MPU3050_INT_LATCH_EN;
1035 if (mpu3050->irq_opendrain)
1036 val |= MPU3050_INT_OPEN;
1037
1038 ret = regmap_write(mpu3050->map, MPU3050_INT_CFG, val);
1039 if (ret)
1040 return ret;
1041 }
1042
1043 return 0;
1044 }
1045
1046 static const struct iio_trigger_ops mpu3050_trigger_ops = {
1047 .set_trigger_state = mpu3050_drdy_trigger_set_state,
1048 };
1049
mpu3050_trigger_probe(struct iio_dev * indio_dev,int irq)1050 static int mpu3050_trigger_probe(struct iio_dev *indio_dev, int irq)
1051 {
1052 struct mpu3050 *mpu3050 = iio_priv(indio_dev);
1053 unsigned long irq_trig;
1054 int ret;
1055
1056 mpu3050->trig = devm_iio_trigger_alloc(&indio_dev->dev,
1057 "%s-dev%d",
1058 indio_dev->name,
1059 iio_device_id(indio_dev));
1060 if (!mpu3050->trig)
1061 return -ENOMEM;
1062
1063 /* Check if IRQ is open drain */
1064 if (of_property_read_bool(mpu3050->dev->of_node, "drive-open-drain"))
1065 mpu3050->irq_opendrain = true;
1066
1067 irq_trig = irqd_get_trigger_type(irq_get_irq_data(irq));
1068 /*
1069 * Configure the interrupt generator hardware to supply whatever
1070 * the interrupt is configured for, edges low/high level low/high,
1071 * we can provide it all.
1072 */
1073 switch (irq_trig) {
1074 case IRQF_TRIGGER_RISING:
1075 dev_info(&indio_dev->dev,
1076 "pulse interrupts on the rising edge\n");
1077 break;
1078 case IRQF_TRIGGER_FALLING:
1079 mpu3050->irq_actl = true;
1080 dev_info(&indio_dev->dev,
1081 "pulse interrupts on the falling edge\n");
1082 break;
1083 case IRQF_TRIGGER_HIGH:
1084 mpu3050->irq_latch = true;
1085 dev_info(&indio_dev->dev,
1086 "interrupts active high level\n");
1087 /*
1088 * With level IRQs, we mask the IRQ until it is processed,
1089 * but with edge IRQs (pulses) we can queue several interrupts
1090 * in the top half.
1091 */
1092 irq_trig |= IRQF_ONESHOT;
1093 break;
1094 case IRQF_TRIGGER_LOW:
1095 mpu3050->irq_latch = true;
1096 mpu3050->irq_actl = true;
1097 irq_trig |= IRQF_ONESHOT;
1098 dev_info(&indio_dev->dev,
1099 "interrupts active low level\n");
1100 break;
1101 default:
1102 /* This is the most preferred mode, if possible */
1103 dev_err(&indio_dev->dev,
1104 "unsupported IRQ trigger specified (%lx), enforce "
1105 "rising edge\n", irq_trig);
1106 irq_trig = IRQF_TRIGGER_RISING;
1107 break;
1108 }
1109
1110 /* An open drain line can be shared with several devices */
1111 if (mpu3050->irq_opendrain)
1112 irq_trig |= IRQF_SHARED;
1113
1114 ret = request_threaded_irq(irq,
1115 mpu3050_irq_handler,
1116 mpu3050_irq_thread,
1117 irq_trig,
1118 mpu3050->trig->name,
1119 mpu3050->trig);
1120 if (ret) {
1121 dev_err(mpu3050->dev,
1122 "can't get IRQ %d, error %d\n", irq, ret);
1123 return ret;
1124 }
1125
1126 mpu3050->irq = irq;
1127 mpu3050->trig->dev.parent = mpu3050->dev;
1128 mpu3050->trig->ops = &mpu3050_trigger_ops;
1129 iio_trigger_set_drvdata(mpu3050->trig, indio_dev);
1130
1131 ret = iio_trigger_register(mpu3050->trig);
1132 if (ret)
1133 return ret;
1134
1135 indio_dev->trig = iio_trigger_get(mpu3050->trig);
1136
1137 return 0;
1138 }
1139
mpu3050_common_probe(struct device * dev,struct regmap * map,int irq,const char * name)1140 int mpu3050_common_probe(struct device *dev,
1141 struct regmap *map,
1142 int irq,
1143 const char *name)
1144 {
1145 struct iio_dev *indio_dev;
1146 struct mpu3050 *mpu3050;
1147 unsigned int val;
1148 int ret;
1149
1150 indio_dev = devm_iio_device_alloc(dev, sizeof(*mpu3050));
1151 if (!indio_dev)
1152 return -ENOMEM;
1153 mpu3050 = iio_priv(indio_dev);
1154
1155 mpu3050->dev = dev;
1156 mpu3050->map = map;
1157 mutex_init(&mpu3050->lock);
1158 /* Default fullscale: 2000 degrees per second */
1159 mpu3050->fullscale = FS_2000_DPS;
1160 /* 1 kHz, divide by 100, default frequency = 10 Hz */
1161 mpu3050->lpf = MPU3050_DLPF_CFG_188HZ;
1162 mpu3050->divisor = 99;
1163
1164 /* Read the mounting matrix, if present */
1165 ret = iio_read_mount_matrix(dev, &mpu3050->orientation);
1166 if (ret)
1167 return ret;
1168
1169 /* Fetch and turn on regulators */
1170 mpu3050->regs[0].supply = mpu3050_reg_vdd;
1171 mpu3050->regs[1].supply = mpu3050_reg_vlogic;
1172 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(mpu3050->regs),
1173 mpu3050->regs);
1174 if (ret) {
1175 dev_err(dev, "Cannot get regulators\n");
1176 return ret;
1177 }
1178
1179 ret = mpu3050_power_up(mpu3050);
1180 if (ret)
1181 return ret;
1182
1183 ret = regmap_read(map, MPU3050_CHIP_ID_REG, &val);
1184 if (ret) {
1185 dev_err(dev, "could not read device ID\n");
1186 ret = -ENODEV;
1187
1188 goto err_power_down;
1189 }
1190
1191 if ((val & MPU3050_CHIP_ID_MASK) != MPU3050_CHIP_ID) {
1192 dev_err(dev, "unsupported chip id %02x\n",
1193 (u8)(val & MPU3050_CHIP_ID_MASK));
1194 ret = -ENODEV;
1195 goto err_power_down;
1196 }
1197
1198 ret = regmap_read(map, MPU3050_PRODUCT_ID_REG, &val);
1199 if (ret) {
1200 dev_err(dev, "could not read device ID\n");
1201 ret = -ENODEV;
1202
1203 goto err_power_down;
1204 }
1205 dev_info(dev, "found MPU-3050 part no: %d, version: %d\n",
1206 ((val >> 4) & 0xf), (val & 0xf));
1207
1208 ret = mpu3050_hw_init(mpu3050);
1209 if (ret)
1210 goto err_power_down;
1211
1212 indio_dev->channels = mpu3050_channels;
1213 indio_dev->num_channels = ARRAY_SIZE(mpu3050_channels);
1214 indio_dev->info = &mpu3050_info;
1215 indio_dev->available_scan_masks = mpu3050_scan_masks;
1216 indio_dev->modes = INDIO_DIRECT_MODE;
1217 indio_dev->name = name;
1218
1219 ret = iio_triggered_buffer_setup(indio_dev, iio_pollfunc_store_time,
1220 mpu3050_trigger_handler,
1221 &mpu3050_buffer_setup_ops);
1222 if (ret) {
1223 dev_err(dev, "triggered buffer setup failed\n");
1224 goto err_power_down;
1225 }
1226
1227 ret = iio_device_register(indio_dev);
1228 if (ret) {
1229 dev_err(dev, "device register failed\n");
1230 goto err_cleanup_buffer;
1231 }
1232
1233 dev_set_drvdata(dev, indio_dev);
1234
1235 /* Check if we have an assigned IRQ to use as trigger */
1236 if (irq) {
1237 ret = mpu3050_trigger_probe(indio_dev, irq);
1238 if (ret)
1239 dev_err(dev, "failed to register trigger\n");
1240 }
1241
1242 /* Enable runtime PM */
1243 pm_runtime_get_noresume(dev);
1244 pm_runtime_set_active(dev);
1245 pm_runtime_enable(dev);
1246 /*
1247 * Set autosuspend to two orders of magnitude larger than the
1248 * start-up time. 100ms start-up time means 10000ms autosuspend,
1249 * i.e. 10 seconds.
1250 */
1251 pm_runtime_set_autosuspend_delay(dev, 10000);
1252 pm_runtime_use_autosuspend(dev);
1253 pm_runtime_put(dev);
1254
1255 return 0;
1256
1257 err_cleanup_buffer:
1258 iio_triggered_buffer_cleanup(indio_dev);
1259 err_power_down:
1260 mpu3050_power_down(mpu3050);
1261
1262 return ret;
1263 }
1264 EXPORT_SYMBOL(mpu3050_common_probe);
1265
mpu3050_common_remove(struct device * dev)1266 int mpu3050_common_remove(struct device *dev)
1267 {
1268 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1269 struct mpu3050 *mpu3050 = iio_priv(indio_dev);
1270
1271 pm_runtime_get_sync(dev);
1272 pm_runtime_put_noidle(dev);
1273 pm_runtime_disable(dev);
1274 iio_triggered_buffer_cleanup(indio_dev);
1275 if (mpu3050->irq)
1276 free_irq(mpu3050->irq, mpu3050);
1277 iio_device_unregister(indio_dev);
1278 mpu3050_power_down(mpu3050);
1279
1280 return 0;
1281 }
1282 EXPORT_SYMBOL(mpu3050_common_remove);
1283
1284 #ifdef CONFIG_PM
mpu3050_runtime_suspend(struct device * dev)1285 static int mpu3050_runtime_suspend(struct device *dev)
1286 {
1287 return mpu3050_power_down(iio_priv(dev_get_drvdata(dev)));
1288 }
1289
mpu3050_runtime_resume(struct device * dev)1290 static int mpu3050_runtime_resume(struct device *dev)
1291 {
1292 return mpu3050_power_up(iio_priv(dev_get_drvdata(dev)));
1293 }
1294 #endif /* CONFIG_PM */
1295
1296 const struct dev_pm_ops mpu3050_dev_pm_ops = {
1297 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1298 pm_runtime_force_resume)
1299 SET_RUNTIME_PM_OPS(mpu3050_runtime_suspend,
1300 mpu3050_runtime_resume, NULL)
1301 };
1302 EXPORT_SYMBOL(mpu3050_dev_pm_ops);
1303
1304 MODULE_AUTHOR("Linus Walleij");
1305 MODULE_DESCRIPTION("MPU3050 gyroscope driver");
1306 MODULE_LICENSE("GPL");
1307