1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Driver for Renesas R-Car MIPI CSI-2 Receiver
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 */
7
8 #include <linux/delay.h>
9 #include <linux/interrupt.h>
10 #include <linux/io.h>
11 #include <linux/module.h>
12 #include <linux/of.h>
13 #include <linux/of_device.h>
14 #include <linux/of_graph.h>
15 #include <linux/platform_device.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/reset.h>
18 #include <linux/sys_soc.h>
19
20 #include <media/v4l2-ctrls.h>
21 #include <media/v4l2-device.h>
22 #include <media/v4l2-fwnode.h>
23 #include <media/v4l2-mc.h>
24 #include <media/v4l2-subdev.h>
25
26 struct rcar_csi2;
27
28 /* Register offsets and bits */
29
30 /* Control Timing Select */
31 #define TREF_REG 0x00
32 #define TREF_TREF BIT(0)
33
34 /* Software Reset */
35 #define SRST_REG 0x04
36 #define SRST_SRST BIT(0)
37
38 /* PHY Operation Control */
39 #define PHYCNT_REG 0x08
40 #define PHYCNT_SHUTDOWNZ BIT(17)
41 #define PHYCNT_RSTZ BIT(16)
42 #define PHYCNT_ENABLECLK BIT(4)
43 #define PHYCNT_ENABLE_3 BIT(3)
44 #define PHYCNT_ENABLE_2 BIT(2)
45 #define PHYCNT_ENABLE_1 BIT(1)
46 #define PHYCNT_ENABLE_0 BIT(0)
47
48 /* Checksum Control */
49 #define CHKSUM_REG 0x0c
50 #define CHKSUM_ECC_EN BIT(1)
51 #define CHKSUM_CRC_EN BIT(0)
52
53 /*
54 * Channel Data Type Select
55 * VCDT[0-15]: Channel 0 VCDT[16-31]: Channel 1
56 * VCDT2[0-15]: Channel 2 VCDT2[16-31]: Channel 3
57 */
58 #define VCDT_REG 0x10
59 #define VCDT2_REG 0x14
60 #define VCDT_VCDTN_EN BIT(15)
61 #define VCDT_SEL_VC(n) (((n) & 0x3) << 8)
62 #define VCDT_SEL_DTN_ON BIT(6)
63 #define VCDT_SEL_DT(n) (((n) & 0x3f) << 0)
64
65 /* Frame Data Type Select */
66 #define FRDT_REG 0x18
67
68 /* Field Detection Control */
69 #define FLD_REG 0x1c
70 #define FLD_FLD_NUM(n) (((n) & 0xff) << 16)
71 #define FLD_DET_SEL(n) (((n) & 0x3) << 4)
72 #define FLD_FLD_EN4 BIT(3)
73 #define FLD_FLD_EN3 BIT(2)
74 #define FLD_FLD_EN2 BIT(1)
75 #define FLD_FLD_EN BIT(0)
76
77 /* Automatic Standby Control */
78 #define ASTBY_REG 0x20
79
80 /* Long Data Type Setting 0 */
81 #define LNGDT0_REG 0x28
82
83 /* Long Data Type Setting 1 */
84 #define LNGDT1_REG 0x2c
85
86 /* Interrupt Enable */
87 #define INTEN_REG 0x30
88 #define INTEN_INT_AFIFO_OF BIT(27)
89 #define INTEN_INT_ERRSOTHS BIT(4)
90 #define INTEN_INT_ERRSOTSYNCHS BIT(3)
91
92 /* Interrupt Source Mask */
93 #define INTCLOSE_REG 0x34
94
95 /* Interrupt Status Monitor */
96 #define INTSTATE_REG 0x38
97 #define INTSTATE_INT_ULPS_START BIT(7)
98 #define INTSTATE_INT_ULPS_END BIT(6)
99
100 /* Interrupt Error Status Monitor */
101 #define INTERRSTATE_REG 0x3c
102
103 /* Short Packet Data */
104 #define SHPDAT_REG 0x40
105
106 /* Short Packet Count */
107 #define SHPCNT_REG 0x44
108
109 /* LINK Operation Control */
110 #define LINKCNT_REG 0x48
111 #define LINKCNT_MONITOR_EN BIT(31)
112 #define LINKCNT_REG_MONI_PACT_EN BIT(25)
113 #define LINKCNT_ICLK_NONSTOP BIT(24)
114
115 /* Lane Swap */
116 #define LSWAP_REG 0x4c
117 #define LSWAP_L3SEL(n) (((n) & 0x3) << 6)
118 #define LSWAP_L2SEL(n) (((n) & 0x3) << 4)
119 #define LSWAP_L1SEL(n) (((n) & 0x3) << 2)
120 #define LSWAP_L0SEL(n) (((n) & 0x3) << 0)
121
122 /* PHY Test Interface Write Register */
123 #define PHTW_REG 0x50
124 #define PHTW_DWEN BIT(24)
125 #define PHTW_TESTDIN_DATA(n) (((n & 0xff)) << 16)
126 #define PHTW_CWEN BIT(8)
127 #define PHTW_TESTDIN_CODE(n) ((n & 0xff))
128
129 #define PHYFRX_REG 0x64
130 #define PHYFRX_FORCERX_MODE_3 BIT(3)
131 #define PHYFRX_FORCERX_MODE_2 BIT(2)
132 #define PHYFRX_FORCERX_MODE_1 BIT(1)
133 #define PHYFRX_FORCERX_MODE_0 BIT(0)
134
135 struct phtw_value {
136 u16 data;
137 u16 code;
138 };
139
140 struct rcsi2_mbps_reg {
141 u16 mbps;
142 u16 reg;
143 };
144
145 static const struct rcsi2_mbps_reg phtw_mbps_v3u[] = {
146 { .mbps = 1500, .reg = 0xcc },
147 { .mbps = 1550, .reg = 0x1d },
148 { .mbps = 1600, .reg = 0x27 },
149 { .mbps = 1650, .reg = 0x30 },
150 { .mbps = 1700, .reg = 0x39 },
151 { .mbps = 1750, .reg = 0x42 },
152 { .mbps = 1800, .reg = 0x4b },
153 { .mbps = 1850, .reg = 0x55 },
154 { .mbps = 1900, .reg = 0x5e },
155 { .mbps = 1950, .reg = 0x67 },
156 { .mbps = 2000, .reg = 0x71 },
157 { .mbps = 2050, .reg = 0x79 },
158 { .mbps = 2100, .reg = 0x83 },
159 { .mbps = 2150, .reg = 0x8c },
160 { .mbps = 2200, .reg = 0x95 },
161 { .mbps = 2250, .reg = 0x9e },
162 { .mbps = 2300, .reg = 0xa7 },
163 { .mbps = 2350, .reg = 0xb0 },
164 { .mbps = 2400, .reg = 0xba },
165 { .mbps = 2450, .reg = 0xc3 },
166 { .mbps = 2500, .reg = 0xcc },
167 { /* sentinel */ },
168 };
169
170 static const struct rcsi2_mbps_reg phtw_mbps_h3_v3h_m3n[] = {
171 { .mbps = 80, .reg = 0x86 },
172 { .mbps = 90, .reg = 0x86 },
173 { .mbps = 100, .reg = 0x87 },
174 { .mbps = 110, .reg = 0x87 },
175 { .mbps = 120, .reg = 0x88 },
176 { .mbps = 130, .reg = 0x88 },
177 { .mbps = 140, .reg = 0x89 },
178 { .mbps = 150, .reg = 0x89 },
179 { .mbps = 160, .reg = 0x8a },
180 { .mbps = 170, .reg = 0x8a },
181 { .mbps = 180, .reg = 0x8b },
182 { .mbps = 190, .reg = 0x8b },
183 { .mbps = 205, .reg = 0x8c },
184 { .mbps = 220, .reg = 0x8d },
185 { .mbps = 235, .reg = 0x8e },
186 { .mbps = 250, .reg = 0x8e },
187 { /* sentinel */ },
188 };
189
190 static const struct rcsi2_mbps_reg phtw_mbps_v3m_e3[] = {
191 { .mbps = 80, .reg = 0x00 },
192 { .mbps = 90, .reg = 0x20 },
193 { .mbps = 100, .reg = 0x40 },
194 { .mbps = 110, .reg = 0x02 },
195 { .mbps = 130, .reg = 0x22 },
196 { .mbps = 140, .reg = 0x42 },
197 { .mbps = 150, .reg = 0x04 },
198 { .mbps = 170, .reg = 0x24 },
199 { .mbps = 180, .reg = 0x44 },
200 { .mbps = 200, .reg = 0x06 },
201 { .mbps = 220, .reg = 0x26 },
202 { .mbps = 240, .reg = 0x46 },
203 { .mbps = 250, .reg = 0x08 },
204 { .mbps = 270, .reg = 0x28 },
205 { .mbps = 300, .reg = 0x0a },
206 { .mbps = 330, .reg = 0x2a },
207 { .mbps = 360, .reg = 0x4a },
208 { .mbps = 400, .reg = 0x0c },
209 { .mbps = 450, .reg = 0x2c },
210 { .mbps = 500, .reg = 0x0e },
211 { .mbps = 550, .reg = 0x2e },
212 { .mbps = 600, .reg = 0x10 },
213 { .mbps = 650, .reg = 0x30 },
214 { .mbps = 700, .reg = 0x12 },
215 { .mbps = 750, .reg = 0x32 },
216 { .mbps = 800, .reg = 0x52 },
217 { .mbps = 850, .reg = 0x72 },
218 { .mbps = 900, .reg = 0x14 },
219 { .mbps = 950, .reg = 0x34 },
220 { .mbps = 1000, .reg = 0x54 },
221 { .mbps = 1050, .reg = 0x74 },
222 { .mbps = 1125, .reg = 0x16 },
223 { /* sentinel */ },
224 };
225
226 /* PHY Test Interface Clear */
227 #define PHTC_REG 0x58
228 #define PHTC_TESTCLR BIT(0)
229
230 /* PHY Frequency Control */
231 #define PHYPLL_REG 0x68
232 #define PHYPLL_HSFREQRANGE(n) ((n) << 16)
233
234 static const struct rcsi2_mbps_reg hsfreqrange_v3u[] = {
235 { .mbps = 80, .reg = 0x00 },
236 { .mbps = 90, .reg = 0x10 },
237 { .mbps = 100, .reg = 0x20 },
238 { .mbps = 110, .reg = 0x30 },
239 { .mbps = 120, .reg = 0x01 },
240 { .mbps = 130, .reg = 0x11 },
241 { .mbps = 140, .reg = 0x21 },
242 { .mbps = 150, .reg = 0x31 },
243 { .mbps = 160, .reg = 0x02 },
244 { .mbps = 170, .reg = 0x12 },
245 { .mbps = 180, .reg = 0x22 },
246 { .mbps = 190, .reg = 0x32 },
247 { .mbps = 205, .reg = 0x03 },
248 { .mbps = 220, .reg = 0x13 },
249 { .mbps = 235, .reg = 0x23 },
250 { .mbps = 250, .reg = 0x33 },
251 { .mbps = 275, .reg = 0x04 },
252 { .mbps = 300, .reg = 0x14 },
253 { .mbps = 325, .reg = 0x25 },
254 { .mbps = 350, .reg = 0x35 },
255 { .mbps = 400, .reg = 0x05 },
256 { .mbps = 450, .reg = 0x16 },
257 { .mbps = 500, .reg = 0x26 },
258 { .mbps = 550, .reg = 0x37 },
259 { .mbps = 600, .reg = 0x07 },
260 { .mbps = 650, .reg = 0x18 },
261 { .mbps = 700, .reg = 0x28 },
262 { .mbps = 750, .reg = 0x39 },
263 { .mbps = 800, .reg = 0x09 },
264 { .mbps = 850, .reg = 0x19 },
265 { .mbps = 900, .reg = 0x29 },
266 { .mbps = 950, .reg = 0x3a },
267 { .mbps = 1000, .reg = 0x0a },
268 { .mbps = 1050, .reg = 0x1a },
269 { .mbps = 1100, .reg = 0x2a },
270 { .mbps = 1150, .reg = 0x3b },
271 { .mbps = 1200, .reg = 0x0b },
272 { .mbps = 1250, .reg = 0x1b },
273 { .mbps = 1300, .reg = 0x2b },
274 { .mbps = 1350, .reg = 0x3c },
275 { .mbps = 1400, .reg = 0x0c },
276 { .mbps = 1450, .reg = 0x1c },
277 { .mbps = 1500, .reg = 0x2c },
278 { .mbps = 1550, .reg = 0x3d },
279 { .mbps = 1600, .reg = 0x0d },
280 { .mbps = 1650, .reg = 0x1d },
281 { .mbps = 1700, .reg = 0x2e },
282 { .mbps = 1750, .reg = 0x3e },
283 { .mbps = 1800, .reg = 0x0e },
284 { .mbps = 1850, .reg = 0x1e },
285 { .mbps = 1900, .reg = 0x2f },
286 { .mbps = 1950, .reg = 0x3f },
287 { .mbps = 2000, .reg = 0x0f },
288 { .mbps = 2050, .reg = 0x40 },
289 { .mbps = 2100, .reg = 0x41 },
290 { .mbps = 2150, .reg = 0x42 },
291 { .mbps = 2200, .reg = 0x43 },
292 { .mbps = 2300, .reg = 0x45 },
293 { .mbps = 2350, .reg = 0x46 },
294 { .mbps = 2400, .reg = 0x47 },
295 { .mbps = 2450, .reg = 0x48 },
296 { .mbps = 2500, .reg = 0x49 },
297 { /* sentinel */ },
298 };
299
300 static const struct rcsi2_mbps_reg hsfreqrange_h3_v3h_m3n[] = {
301 { .mbps = 80, .reg = 0x00 },
302 { .mbps = 90, .reg = 0x10 },
303 { .mbps = 100, .reg = 0x20 },
304 { .mbps = 110, .reg = 0x30 },
305 { .mbps = 120, .reg = 0x01 },
306 { .mbps = 130, .reg = 0x11 },
307 { .mbps = 140, .reg = 0x21 },
308 { .mbps = 150, .reg = 0x31 },
309 { .mbps = 160, .reg = 0x02 },
310 { .mbps = 170, .reg = 0x12 },
311 { .mbps = 180, .reg = 0x22 },
312 { .mbps = 190, .reg = 0x32 },
313 { .mbps = 205, .reg = 0x03 },
314 { .mbps = 220, .reg = 0x13 },
315 { .mbps = 235, .reg = 0x23 },
316 { .mbps = 250, .reg = 0x33 },
317 { .mbps = 275, .reg = 0x04 },
318 { .mbps = 300, .reg = 0x14 },
319 { .mbps = 325, .reg = 0x25 },
320 { .mbps = 350, .reg = 0x35 },
321 { .mbps = 400, .reg = 0x05 },
322 { .mbps = 450, .reg = 0x16 },
323 { .mbps = 500, .reg = 0x26 },
324 { .mbps = 550, .reg = 0x37 },
325 { .mbps = 600, .reg = 0x07 },
326 { .mbps = 650, .reg = 0x18 },
327 { .mbps = 700, .reg = 0x28 },
328 { .mbps = 750, .reg = 0x39 },
329 { .mbps = 800, .reg = 0x09 },
330 { .mbps = 850, .reg = 0x19 },
331 { .mbps = 900, .reg = 0x29 },
332 { .mbps = 950, .reg = 0x3a },
333 { .mbps = 1000, .reg = 0x0a },
334 { .mbps = 1050, .reg = 0x1a },
335 { .mbps = 1100, .reg = 0x2a },
336 { .mbps = 1150, .reg = 0x3b },
337 { .mbps = 1200, .reg = 0x0b },
338 { .mbps = 1250, .reg = 0x1b },
339 { .mbps = 1300, .reg = 0x2b },
340 { .mbps = 1350, .reg = 0x3c },
341 { .mbps = 1400, .reg = 0x0c },
342 { .mbps = 1450, .reg = 0x1c },
343 { .mbps = 1500, .reg = 0x2c },
344 { /* sentinel */ },
345 };
346
347 static const struct rcsi2_mbps_reg hsfreqrange_m3w_h3es1[] = {
348 { .mbps = 80, .reg = 0x00 },
349 { .mbps = 90, .reg = 0x10 },
350 { .mbps = 100, .reg = 0x20 },
351 { .mbps = 110, .reg = 0x30 },
352 { .mbps = 120, .reg = 0x01 },
353 { .mbps = 130, .reg = 0x11 },
354 { .mbps = 140, .reg = 0x21 },
355 { .mbps = 150, .reg = 0x31 },
356 { .mbps = 160, .reg = 0x02 },
357 { .mbps = 170, .reg = 0x12 },
358 { .mbps = 180, .reg = 0x22 },
359 { .mbps = 190, .reg = 0x32 },
360 { .mbps = 205, .reg = 0x03 },
361 { .mbps = 220, .reg = 0x13 },
362 { .mbps = 235, .reg = 0x23 },
363 { .mbps = 250, .reg = 0x33 },
364 { .mbps = 275, .reg = 0x04 },
365 { .mbps = 300, .reg = 0x14 },
366 { .mbps = 325, .reg = 0x05 },
367 { .mbps = 350, .reg = 0x15 },
368 { .mbps = 400, .reg = 0x25 },
369 { .mbps = 450, .reg = 0x06 },
370 { .mbps = 500, .reg = 0x16 },
371 { .mbps = 550, .reg = 0x07 },
372 { .mbps = 600, .reg = 0x17 },
373 { .mbps = 650, .reg = 0x08 },
374 { .mbps = 700, .reg = 0x18 },
375 { .mbps = 750, .reg = 0x09 },
376 { .mbps = 800, .reg = 0x19 },
377 { .mbps = 850, .reg = 0x29 },
378 { .mbps = 900, .reg = 0x39 },
379 { .mbps = 950, .reg = 0x0a },
380 { .mbps = 1000, .reg = 0x1a },
381 { .mbps = 1050, .reg = 0x2a },
382 { .mbps = 1100, .reg = 0x3a },
383 { .mbps = 1150, .reg = 0x0b },
384 { .mbps = 1200, .reg = 0x1b },
385 { .mbps = 1250, .reg = 0x2b },
386 { .mbps = 1300, .reg = 0x3b },
387 { .mbps = 1350, .reg = 0x0c },
388 { .mbps = 1400, .reg = 0x1c },
389 { .mbps = 1450, .reg = 0x2c },
390 { .mbps = 1500, .reg = 0x3c },
391 { /* sentinel */ },
392 };
393
394 /* PHY ESC Error Monitor */
395 #define PHEERM_REG 0x74
396
397 /* PHY Clock Lane Monitor */
398 #define PHCLM_REG 0x78
399 #define PHCLM_STOPSTATECKL BIT(0)
400
401 /* PHY Data Lane Monitor */
402 #define PHDLM_REG 0x7c
403
404 /* CSI0CLK Frequency Configuration Preset Register */
405 #define CSI0CLKFCPR_REG 0x260
406 #define CSI0CLKFREQRANGE(n) ((n & 0x3f) << 16)
407
408 struct rcar_csi2_format {
409 u32 code;
410 unsigned int datatype;
411 unsigned int bpp;
412 };
413
414 static const struct rcar_csi2_format rcar_csi2_formats[] = {
415 { .code = MEDIA_BUS_FMT_RGB888_1X24, .datatype = 0x24, .bpp = 24 },
416 { .code = MEDIA_BUS_FMT_UYVY8_1X16, .datatype = 0x1e, .bpp = 16 },
417 { .code = MEDIA_BUS_FMT_YUYV8_1X16, .datatype = 0x1e, .bpp = 16 },
418 { .code = MEDIA_BUS_FMT_UYVY8_2X8, .datatype = 0x1e, .bpp = 16 },
419 { .code = MEDIA_BUS_FMT_YUYV10_2X10, .datatype = 0x1e, .bpp = 20 },
420 { .code = MEDIA_BUS_FMT_Y10_1X10, .datatype = 0x2b, .bpp = 10 },
421 { .code = MEDIA_BUS_FMT_SBGGR8_1X8, .datatype = 0x2a, .bpp = 8 },
422 { .code = MEDIA_BUS_FMT_SGBRG8_1X8, .datatype = 0x2a, .bpp = 8 },
423 { .code = MEDIA_BUS_FMT_SGRBG8_1X8, .datatype = 0x2a, .bpp = 8 },
424 { .code = MEDIA_BUS_FMT_SRGGB8_1X8, .datatype = 0x2a, .bpp = 8 },
425 { .code = MEDIA_BUS_FMT_Y8_1X8, .datatype = 0x2a, .bpp = 8 },
426 };
427
rcsi2_code_to_fmt(unsigned int code)428 static const struct rcar_csi2_format *rcsi2_code_to_fmt(unsigned int code)
429 {
430 unsigned int i;
431
432 for (i = 0; i < ARRAY_SIZE(rcar_csi2_formats); i++)
433 if (rcar_csi2_formats[i].code == code)
434 return &rcar_csi2_formats[i];
435
436 return NULL;
437 }
438
439 enum rcar_csi2_pads {
440 RCAR_CSI2_SINK,
441 RCAR_CSI2_SOURCE_VC0,
442 RCAR_CSI2_SOURCE_VC1,
443 RCAR_CSI2_SOURCE_VC2,
444 RCAR_CSI2_SOURCE_VC3,
445 NR_OF_RCAR_CSI2_PAD,
446 };
447
448 struct rcar_csi2_info {
449 int (*init_phtw)(struct rcar_csi2 *priv, unsigned int mbps);
450 int (*phy_post_init)(struct rcar_csi2 *priv);
451 const struct rcsi2_mbps_reg *hsfreqrange;
452 unsigned int csi0clkfreqrange;
453 unsigned int num_channels;
454 bool clear_ulps;
455 bool use_isp;
456 };
457
458 struct rcar_csi2 {
459 struct device *dev;
460 void __iomem *base;
461 const struct rcar_csi2_info *info;
462 struct reset_control *rstc;
463
464 struct v4l2_subdev subdev;
465 struct media_pad pads[NR_OF_RCAR_CSI2_PAD];
466
467 struct v4l2_async_notifier notifier;
468 struct v4l2_subdev *remote;
469 unsigned int remote_pad;
470
471 struct mutex lock; /* Protects mf and stream_count. */
472 struct v4l2_mbus_framefmt mf;
473 int stream_count;
474
475 unsigned short lanes;
476 unsigned char lane_swap[4];
477 };
478
sd_to_csi2(struct v4l2_subdev * sd)479 static inline struct rcar_csi2 *sd_to_csi2(struct v4l2_subdev *sd)
480 {
481 return container_of(sd, struct rcar_csi2, subdev);
482 }
483
notifier_to_csi2(struct v4l2_async_notifier * n)484 static inline struct rcar_csi2 *notifier_to_csi2(struct v4l2_async_notifier *n)
485 {
486 return container_of(n, struct rcar_csi2, notifier);
487 }
488
rcsi2_read(struct rcar_csi2 * priv,unsigned int reg)489 static u32 rcsi2_read(struct rcar_csi2 *priv, unsigned int reg)
490 {
491 return ioread32(priv->base + reg);
492 }
493
rcsi2_write(struct rcar_csi2 * priv,unsigned int reg,u32 data)494 static void rcsi2_write(struct rcar_csi2 *priv, unsigned int reg, u32 data)
495 {
496 iowrite32(data, priv->base + reg);
497 }
498
rcsi2_enter_standby(struct rcar_csi2 * priv)499 static void rcsi2_enter_standby(struct rcar_csi2 *priv)
500 {
501 rcsi2_write(priv, PHYCNT_REG, 0);
502 rcsi2_write(priv, PHTC_REG, PHTC_TESTCLR);
503 reset_control_assert(priv->rstc);
504 usleep_range(100, 150);
505 pm_runtime_put(priv->dev);
506 }
507
rcsi2_exit_standby(struct rcar_csi2 * priv)508 static int rcsi2_exit_standby(struct rcar_csi2 *priv)
509 {
510 int ret;
511
512 ret = pm_runtime_resume_and_get(priv->dev);
513 if (ret < 0)
514 return ret;
515
516 reset_control_deassert(priv->rstc);
517
518 return 0;
519 }
520
rcsi2_wait_phy_start(struct rcar_csi2 * priv,unsigned int lanes)521 static int rcsi2_wait_phy_start(struct rcar_csi2 *priv,
522 unsigned int lanes)
523 {
524 unsigned int timeout;
525
526 /* Wait for the clock and data lanes to enter LP-11 state. */
527 for (timeout = 0; timeout <= 20; timeout++) {
528 const u32 lane_mask = (1 << lanes) - 1;
529
530 if ((rcsi2_read(priv, PHCLM_REG) & PHCLM_STOPSTATECKL) &&
531 (rcsi2_read(priv, PHDLM_REG) & lane_mask) == lane_mask)
532 return 0;
533
534 usleep_range(1000, 2000);
535 }
536
537 dev_err(priv->dev, "Timeout waiting for LP-11 state\n");
538
539 return -ETIMEDOUT;
540 }
541
rcsi2_set_phypll(struct rcar_csi2 * priv,unsigned int mbps)542 static int rcsi2_set_phypll(struct rcar_csi2 *priv, unsigned int mbps)
543 {
544 const struct rcsi2_mbps_reg *hsfreq;
545
546 for (hsfreq = priv->info->hsfreqrange; hsfreq->mbps != 0; hsfreq++)
547 if (hsfreq->mbps >= mbps)
548 break;
549
550 if (!hsfreq->mbps) {
551 dev_err(priv->dev, "Unsupported PHY speed (%u Mbps)", mbps);
552 return -ERANGE;
553 }
554
555 rcsi2_write(priv, PHYPLL_REG, PHYPLL_HSFREQRANGE(hsfreq->reg));
556
557 return 0;
558 }
559
rcsi2_calc_mbps(struct rcar_csi2 * priv,unsigned int bpp,unsigned int lanes)560 static int rcsi2_calc_mbps(struct rcar_csi2 *priv, unsigned int bpp,
561 unsigned int lanes)
562 {
563 struct v4l2_subdev *source;
564 struct v4l2_ctrl *ctrl;
565 u64 mbps;
566
567 if (!priv->remote)
568 return -ENODEV;
569
570 source = priv->remote;
571
572 /* Read the pixel rate control from remote. */
573 ctrl = v4l2_ctrl_find(source->ctrl_handler, V4L2_CID_PIXEL_RATE);
574 if (!ctrl) {
575 dev_err(priv->dev, "no pixel rate control in subdev %s\n",
576 source->name);
577 return -EINVAL;
578 }
579
580 /*
581 * Calculate the phypll in mbps.
582 * link_freq = (pixel_rate * bits_per_sample) / (2 * nr_of_lanes)
583 * bps = link_freq * 2
584 */
585 mbps = v4l2_ctrl_g_ctrl_int64(ctrl) * bpp;
586 do_div(mbps, lanes * 1000000);
587
588 return mbps;
589 }
590
rcsi2_get_active_lanes(struct rcar_csi2 * priv,unsigned int * lanes)591 static int rcsi2_get_active_lanes(struct rcar_csi2 *priv,
592 unsigned int *lanes)
593 {
594 struct v4l2_mbus_config mbus_config = { 0 };
595 unsigned int num_lanes = UINT_MAX;
596 int ret;
597
598 *lanes = priv->lanes;
599
600 ret = v4l2_subdev_call(priv->remote, pad, get_mbus_config,
601 priv->remote_pad, &mbus_config);
602 if (ret == -ENOIOCTLCMD) {
603 dev_dbg(priv->dev, "No remote mbus configuration available\n");
604 return 0;
605 }
606
607 if (ret) {
608 dev_err(priv->dev, "Failed to get remote mbus configuration\n");
609 return ret;
610 }
611
612 if (mbus_config.type != V4L2_MBUS_CSI2_DPHY) {
613 dev_err(priv->dev, "Unsupported media bus type %u\n",
614 mbus_config.type);
615 return -EINVAL;
616 }
617
618 if (mbus_config.flags & V4L2_MBUS_CSI2_1_LANE)
619 num_lanes = 1;
620 else if (mbus_config.flags & V4L2_MBUS_CSI2_2_LANE)
621 num_lanes = 2;
622 else if (mbus_config.flags & V4L2_MBUS_CSI2_3_LANE)
623 num_lanes = 3;
624 else if (mbus_config.flags & V4L2_MBUS_CSI2_4_LANE)
625 num_lanes = 4;
626
627 if (num_lanes > priv->lanes) {
628 dev_err(priv->dev,
629 "Unsupported mbus config: too many data lanes %u\n",
630 num_lanes);
631 return -EINVAL;
632 }
633
634 *lanes = num_lanes;
635
636 return 0;
637 }
638
rcsi2_start_receiver(struct rcar_csi2 * priv)639 static int rcsi2_start_receiver(struct rcar_csi2 *priv)
640 {
641 const struct rcar_csi2_format *format;
642 u32 phycnt, vcdt = 0, vcdt2 = 0, fld = 0;
643 unsigned int lanes;
644 unsigned int i;
645 int mbps, ret;
646
647 dev_dbg(priv->dev, "Input size (%ux%u%c)\n",
648 priv->mf.width, priv->mf.height,
649 priv->mf.field == V4L2_FIELD_NONE ? 'p' : 'i');
650
651 /* Code is validated in set_fmt. */
652 format = rcsi2_code_to_fmt(priv->mf.code);
653 if (!format)
654 return -EINVAL;
655
656 /*
657 * Enable all supported CSI-2 channels with virtual channel and
658 * data type matching.
659 *
660 * NOTE: It's not possible to get individual datatype for each
661 * source virtual channel. Once this is possible in V4L2
662 * it should be used here.
663 */
664 for (i = 0; i < priv->info->num_channels; i++) {
665 u32 vcdt_part;
666
667 vcdt_part = VCDT_SEL_VC(i) | VCDT_VCDTN_EN | VCDT_SEL_DTN_ON |
668 VCDT_SEL_DT(format->datatype);
669
670 /* Store in correct reg and offset. */
671 if (i < 2)
672 vcdt |= vcdt_part << ((i % 2) * 16);
673 else
674 vcdt2 |= vcdt_part << ((i % 2) * 16);
675 }
676
677 if (priv->mf.field == V4L2_FIELD_ALTERNATE) {
678 fld = FLD_DET_SEL(1) | FLD_FLD_EN4 | FLD_FLD_EN3 | FLD_FLD_EN2
679 | FLD_FLD_EN;
680
681 if (priv->mf.height == 240)
682 fld |= FLD_FLD_NUM(0);
683 else
684 fld |= FLD_FLD_NUM(1);
685 }
686
687 /*
688 * Get the number of active data lanes inspecting the remote mbus
689 * configuration.
690 */
691 ret = rcsi2_get_active_lanes(priv, &lanes);
692 if (ret)
693 return ret;
694
695 phycnt = PHYCNT_ENABLECLK;
696 phycnt |= (1 << lanes) - 1;
697
698 mbps = rcsi2_calc_mbps(priv, format->bpp, lanes);
699 if (mbps < 0)
700 return mbps;
701
702 /* Enable interrupts. */
703 rcsi2_write(priv, INTEN_REG, INTEN_INT_AFIFO_OF | INTEN_INT_ERRSOTHS
704 | INTEN_INT_ERRSOTSYNCHS);
705
706 /* Init */
707 rcsi2_write(priv, TREF_REG, TREF_TREF);
708 rcsi2_write(priv, PHTC_REG, 0);
709
710 /* Configure */
711 if (!priv->info->use_isp) {
712 rcsi2_write(priv, VCDT_REG, vcdt);
713 if (vcdt2)
714 rcsi2_write(priv, VCDT2_REG, vcdt2);
715 }
716
717 /* Lanes are zero indexed. */
718 rcsi2_write(priv, LSWAP_REG,
719 LSWAP_L0SEL(priv->lane_swap[0] - 1) |
720 LSWAP_L1SEL(priv->lane_swap[1] - 1) |
721 LSWAP_L2SEL(priv->lane_swap[2] - 1) |
722 LSWAP_L3SEL(priv->lane_swap[3] - 1));
723
724 /* Start */
725 if (priv->info->init_phtw) {
726 ret = priv->info->init_phtw(priv, mbps);
727 if (ret)
728 return ret;
729 }
730
731 if (priv->info->hsfreqrange) {
732 ret = rcsi2_set_phypll(priv, mbps);
733 if (ret)
734 return ret;
735 }
736
737 if (priv->info->csi0clkfreqrange)
738 rcsi2_write(priv, CSI0CLKFCPR_REG,
739 CSI0CLKFREQRANGE(priv->info->csi0clkfreqrange));
740
741 if (priv->info->use_isp)
742 rcsi2_write(priv, PHYFRX_REG,
743 PHYFRX_FORCERX_MODE_3 | PHYFRX_FORCERX_MODE_2 |
744 PHYFRX_FORCERX_MODE_1 | PHYFRX_FORCERX_MODE_0);
745
746 rcsi2_write(priv, PHYCNT_REG, phycnt);
747 rcsi2_write(priv, LINKCNT_REG, LINKCNT_MONITOR_EN |
748 LINKCNT_REG_MONI_PACT_EN | LINKCNT_ICLK_NONSTOP);
749 rcsi2_write(priv, FLD_REG, fld);
750 rcsi2_write(priv, PHYCNT_REG, phycnt | PHYCNT_SHUTDOWNZ);
751 rcsi2_write(priv, PHYCNT_REG, phycnt | PHYCNT_SHUTDOWNZ | PHYCNT_RSTZ);
752
753 ret = rcsi2_wait_phy_start(priv, lanes);
754 if (ret)
755 return ret;
756
757 if (priv->info->use_isp)
758 rcsi2_write(priv, PHYFRX_REG, 0);
759
760 /* Run post PHY start initialization, if needed. */
761 if (priv->info->phy_post_init) {
762 ret = priv->info->phy_post_init(priv);
763 if (ret)
764 return ret;
765 }
766
767 /* Clear Ultra Low Power interrupt. */
768 if (priv->info->clear_ulps)
769 rcsi2_write(priv, INTSTATE_REG,
770 INTSTATE_INT_ULPS_START |
771 INTSTATE_INT_ULPS_END);
772 return 0;
773 }
774
rcsi2_start(struct rcar_csi2 * priv)775 static int rcsi2_start(struct rcar_csi2 *priv)
776 {
777 int ret;
778
779 ret = rcsi2_exit_standby(priv);
780 if (ret < 0)
781 return ret;
782
783 ret = rcsi2_start_receiver(priv);
784 if (ret) {
785 rcsi2_enter_standby(priv);
786 return ret;
787 }
788
789 ret = v4l2_subdev_call(priv->remote, video, s_stream, 1);
790 if (ret) {
791 rcsi2_enter_standby(priv);
792 return ret;
793 }
794
795 return 0;
796 }
797
rcsi2_stop(struct rcar_csi2 * priv)798 static void rcsi2_stop(struct rcar_csi2 *priv)
799 {
800 rcsi2_enter_standby(priv);
801 v4l2_subdev_call(priv->remote, video, s_stream, 0);
802 }
803
rcsi2_s_stream(struct v4l2_subdev * sd,int enable)804 static int rcsi2_s_stream(struct v4l2_subdev *sd, int enable)
805 {
806 struct rcar_csi2 *priv = sd_to_csi2(sd);
807 int ret = 0;
808
809 mutex_lock(&priv->lock);
810
811 if (!priv->remote) {
812 ret = -ENODEV;
813 goto out;
814 }
815
816 if (enable && priv->stream_count == 0) {
817 ret = rcsi2_start(priv);
818 if (ret)
819 goto out;
820 } else if (!enable && priv->stream_count == 1) {
821 rcsi2_stop(priv);
822 }
823
824 priv->stream_count += enable ? 1 : -1;
825 out:
826 mutex_unlock(&priv->lock);
827
828 return ret;
829 }
830
rcsi2_set_pad_format(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * format)831 static int rcsi2_set_pad_format(struct v4l2_subdev *sd,
832 struct v4l2_subdev_state *sd_state,
833 struct v4l2_subdev_format *format)
834 {
835 struct rcar_csi2 *priv = sd_to_csi2(sd);
836 struct v4l2_mbus_framefmt *framefmt;
837
838 mutex_lock(&priv->lock);
839
840 if (!rcsi2_code_to_fmt(format->format.code))
841 format->format.code = rcar_csi2_formats[0].code;
842
843 if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
844 priv->mf = format->format;
845 } else {
846 framefmt = v4l2_subdev_get_try_format(sd, sd_state, 0);
847 *framefmt = format->format;
848 }
849
850 mutex_unlock(&priv->lock);
851
852 return 0;
853 }
854
rcsi2_get_pad_format(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * format)855 static int rcsi2_get_pad_format(struct v4l2_subdev *sd,
856 struct v4l2_subdev_state *sd_state,
857 struct v4l2_subdev_format *format)
858 {
859 struct rcar_csi2 *priv = sd_to_csi2(sd);
860
861 mutex_lock(&priv->lock);
862
863 if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE)
864 format->format = priv->mf;
865 else
866 format->format = *v4l2_subdev_get_try_format(sd, sd_state, 0);
867
868 mutex_unlock(&priv->lock);
869
870 return 0;
871 }
872
873 static const struct v4l2_subdev_video_ops rcar_csi2_video_ops = {
874 .s_stream = rcsi2_s_stream,
875 };
876
877 static const struct v4l2_subdev_pad_ops rcar_csi2_pad_ops = {
878 .set_fmt = rcsi2_set_pad_format,
879 .get_fmt = rcsi2_get_pad_format,
880 };
881
882 static const struct v4l2_subdev_ops rcar_csi2_subdev_ops = {
883 .video = &rcar_csi2_video_ops,
884 .pad = &rcar_csi2_pad_ops,
885 };
886
rcsi2_irq(int irq,void * data)887 static irqreturn_t rcsi2_irq(int irq, void *data)
888 {
889 struct rcar_csi2 *priv = data;
890 u32 status, err_status;
891
892 status = rcsi2_read(priv, INTSTATE_REG);
893 err_status = rcsi2_read(priv, INTERRSTATE_REG);
894
895 if (!status)
896 return IRQ_HANDLED;
897
898 rcsi2_write(priv, INTSTATE_REG, status);
899
900 if (!err_status)
901 return IRQ_HANDLED;
902
903 rcsi2_write(priv, INTERRSTATE_REG, err_status);
904
905 dev_info(priv->dev, "Transfer error, restarting CSI-2 receiver\n");
906
907 return IRQ_WAKE_THREAD;
908 }
909
rcsi2_irq_thread(int irq,void * data)910 static irqreturn_t rcsi2_irq_thread(int irq, void *data)
911 {
912 struct rcar_csi2 *priv = data;
913
914 mutex_lock(&priv->lock);
915 rcsi2_stop(priv);
916 usleep_range(1000, 2000);
917 if (rcsi2_start(priv))
918 dev_warn(priv->dev, "Failed to restart CSI-2 receiver\n");
919 mutex_unlock(&priv->lock);
920
921 return IRQ_HANDLED;
922 }
923
924 /* -----------------------------------------------------------------------------
925 * Async handling and registration of subdevices and links.
926 */
927
rcsi2_notify_bound(struct v4l2_async_notifier * notifier,struct v4l2_subdev * subdev,struct v4l2_async_subdev * asd)928 static int rcsi2_notify_bound(struct v4l2_async_notifier *notifier,
929 struct v4l2_subdev *subdev,
930 struct v4l2_async_subdev *asd)
931 {
932 struct rcar_csi2 *priv = notifier_to_csi2(notifier);
933 int pad;
934
935 pad = media_entity_get_fwnode_pad(&subdev->entity, asd->match.fwnode,
936 MEDIA_PAD_FL_SOURCE);
937 if (pad < 0) {
938 dev_err(priv->dev, "Failed to find pad for %s\n", subdev->name);
939 return pad;
940 }
941
942 priv->remote = subdev;
943 priv->remote_pad = pad;
944
945 dev_dbg(priv->dev, "Bound %s pad: %d\n", subdev->name, pad);
946
947 return media_create_pad_link(&subdev->entity, pad,
948 &priv->subdev.entity, 0,
949 MEDIA_LNK_FL_ENABLED |
950 MEDIA_LNK_FL_IMMUTABLE);
951 }
952
rcsi2_notify_unbind(struct v4l2_async_notifier * notifier,struct v4l2_subdev * subdev,struct v4l2_async_subdev * asd)953 static void rcsi2_notify_unbind(struct v4l2_async_notifier *notifier,
954 struct v4l2_subdev *subdev,
955 struct v4l2_async_subdev *asd)
956 {
957 struct rcar_csi2 *priv = notifier_to_csi2(notifier);
958
959 priv->remote = NULL;
960
961 dev_dbg(priv->dev, "Unbind %s\n", subdev->name);
962 }
963
964 static const struct v4l2_async_notifier_operations rcar_csi2_notify_ops = {
965 .bound = rcsi2_notify_bound,
966 .unbind = rcsi2_notify_unbind,
967 };
968
rcsi2_parse_v4l2(struct rcar_csi2 * priv,struct v4l2_fwnode_endpoint * vep)969 static int rcsi2_parse_v4l2(struct rcar_csi2 *priv,
970 struct v4l2_fwnode_endpoint *vep)
971 {
972 unsigned int i;
973
974 /* Only port 0 endpoint 0 is valid. */
975 if (vep->base.port || vep->base.id)
976 return -ENOTCONN;
977
978 if (vep->bus_type != V4L2_MBUS_CSI2_DPHY) {
979 dev_err(priv->dev, "Unsupported bus: %u\n", vep->bus_type);
980 return -EINVAL;
981 }
982
983 priv->lanes = vep->bus.mipi_csi2.num_data_lanes;
984 if (priv->lanes != 1 && priv->lanes != 2 && priv->lanes != 4) {
985 dev_err(priv->dev, "Unsupported number of data-lanes: %u\n",
986 priv->lanes);
987 return -EINVAL;
988 }
989
990 for (i = 0; i < ARRAY_SIZE(priv->lane_swap); i++) {
991 priv->lane_swap[i] = i < priv->lanes ?
992 vep->bus.mipi_csi2.data_lanes[i] : i;
993
994 /* Check for valid lane number. */
995 if (priv->lane_swap[i] < 1 || priv->lane_swap[i] > 4) {
996 dev_err(priv->dev, "data-lanes must be in 1-4 range\n");
997 return -EINVAL;
998 }
999 }
1000
1001 return 0;
1002 }
1003
rcsi2_parse_dt(struct rcar_csi2 * priv)1004 static int rcsi2_parse_dt(struct rcar_csi2 *priv)
1005 {
1006 struct v4l2_async_subdev *asd;
1007 struct fwnode_handle *fwnode;
1008 struct fwnode_handle *ep;
1009 struct v4l2_fwnode_endpoint v4l2_ep = {
1010 .bus_type = V4L2_MBUS_CSI2_DPHY
1011 };
1012 int ret;
1013
1014 ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(priv->dev), 0, 0, 0);
1015 if (!ep) {
1016 dev_err(priv->dev, "Not connected to subdevice\n");
1017 return -EINVAL;
1018 }
1019
1020 ret = v4l2_fwnode_endpoint_parse(ep, &v4l2_ep);
1021 if (ret) {
1022 dev_err(priv->dev, "Could not parse v4l2 endpoint\n");
1023 fwnode_handle_put(ep);
1024 return -EINVAL;
1025 }
1026
1027 ret = rcsi2_parse_v4l2(priv, &v4l2_ep);
1028 if (ret) {
1029 fwnode_handle_put(ep);
1030 return ret;
1031 }
1032
1033 fwnode = fwnode_graph_get_remote_endpoint(ep);
1034 fwnode_handle_put(ep);
1035
1036 dev_dbg(priv->dev, "Found '%pOF'\n", to_of_node(fwnode));
1037
1038 v4l2_async_nf_init(&priv->notifier);
1039 priv->notifier.ops = &rcar_csi2_notify_ops;
1040
1041 asd = v4l2_async_nf_add_fwnode(&priv->notifier, fwnode,
1042 struct v4l2_async_subdev);
1043 fwnode_handle_put(fwnode);
1044 if (IS_ERR(asd))
1045 return PTR_ERR(asd);
1046
1047 ret = v4l2_async_subdev_nf_register(&priv->subdev, &priv->notifier);
1048 if (ret)
1049 v4l2_async_nf_cleanup(&priv->notifier);
1050
1051 return ret;
1052 }
1053
1054 /* -----------------------------------------------------------------------------
1055 * PHTW initialization sequences.
1056 *
1057 * NOTE: Magic values are from the datasheet and lack documentation.
1058 */
1059
rcsi2_phtw_write(struct rcar_csi2 * priv,u16 data,u16 code)1060 static int rcsi2_phtw_write(struct rcar_csi2 *priv, u16 data, u16 code)
1061 {
1062 unsigned int timeout;
1063
1064 rcsi2_write(priv, PHTW_REG,
1065 PHTW_DWEN | PHTW_TESTDIN_DATA(data) |
1066 PHTW_CWEN | PHTW_TESTDIN_CODE(code));
1067
1068 /* Wait for DWEN and CWEN to be cleared by hardware. */
1069 for (timeout = 0; timeout <= 20; timeout++) {
1070 if (!(rcsi2_read(priv, PHTW_REG) & (PHTW_DWEN | PHTW_CWEN)))
1071 return 0;
1072
1073 usleep_range(1000, 2000);
1074 }
1075
1076 dev_err(priv->dev, "Timeout waiting for PHTW_DWEN and/or PHTW_CWEN\n");
1077
1078 return -ETIMEDOUT;
1079 }
1080
rcsi2_phtw_write_array(struct rcar_csi2 * priv,const struct phtw_value * values)1081 static int rcsi2_phtw_write_array(struct rcar_csi2 *priv,
1082 const struct phtw_value *values)
1083 {
1084 const struct phtw_value *value;
1085 int ret;
1086
1087 for (value = values; value->data || value->code; value++) {
1088 ret = rcsi2_phtw_write(priv, value->data, value->code);
1089 if (ret)
1090 return ret;
1091 }
1092
1093 return 0;
1094 }
1095
rcsi2_phtw_write_mbps(struct rcar_csi2 * priv,unsigned int mbps,const struct rcsi2_mbps_reg * values,u16 code)1096 static int rcsi2_phtw_write_mbps(struct rcar_csi2 *priv, unsigned int mbps,
1097 const struct rcsi2_mbps_reg *values, u16 code)
1098 {
1099 const struct rcsi2_mbps_reg *value;
1100
1101 for (value = values; value->mbps; value++)
1102 if (value->mbps >= mbps)
1103 break;
1104
1105 if (!value->mbps) {
1106 dev_err(priv->dev, "Unsupported PHY speed (%u Mbps)", mbps);
1107 return -ERANGE;
1108 }
1109
1110 return rcsi2_phtw_write(priv, value->reg, code);
1111 }
1112
__rcsi2_init_phtw_h3_v3h_m3n(struct rcar_csi2 * priv,unsigned int mbps)1113 static int __rcsi2_init_phtw_h3_v3h_m3n(struct rcar_csi2 *priv,
1114 unsigned int mbps)
1115 {
1116 static const struct phtw_value step1[] = {
1117 { .data = 0xcc, .code = 0xe2 },
1118 { .data = 0x01, .code = 0xe3 },
1119 { .data = 0x11, .code = 0xe4 },
1120 { .data = 0x01, .code = 0xe5 },
1121 { .data = 0x10, .code = 0x04 },
1122 { /* sentinel */ },
1123 };
1124
1125 static const struct phtw_value step2[] = {
1126 { .data = 0x38, .code = 0x08 },
1127 { .data = 0x01, .code = 0x00 },
1128 { .data = 0x4b, .code = 0xac },
1129 { .data = 0x03, .code = 0x00 },
1130 { .data = 0x80, .code = 0x07 },
1131 { /* sentinel */ },
1132 };
1133
1134 int ret;
1135
1136 ret = rcsi2_phtw_write_array(priv, step1);
1137 if (ret)
1138 return ret;
1139
1140 if (mbps != 0 && mbps <= 250) {
1141 ret = rcsi2_phtw_write(priv, 0x39, 0x05);
1142 if (ret)
1143 return ret;
1144
1145 ret = rcsi2_phtw_write_mbps(priv, mbps, phtw_mbps_h3_v3h_m3n,
1146 0xf1);
1147 if (ret)
1148 return ret;
1149 }
1150
1151 return rcsi2_phtw_write_array(priv, step2);
1152 }
1153
rcsi2_init_phtw_h3_v3h_m3n(struct rcar_csi2 * priv,unsigned int mbps)1154 static int rcsi2_init_phtw_h3_v3h_m3n(struct rcar_csi2 *priv, unsigned int mbps)
1155 {
1156 return __rcsi2_init_phtw_h3_v3h_m3n(priv, mbps);
1157 }
1158
rcsi2_init_phtw_h3es2(struct rcar_csi2 * priv,unsigned int mbps)1159 static int rcsi2_init_phtw_h3es2(struct rcar_csi2 *priv, unsigned int mbps)
1160 {
1161 return __rcsi2_init_phtw_h3_v3h_m3n(priv, 0);
1162 }
1163
rcsi2_init_phtw_v3m_e3(struct rcar_csi2 * priv,unsigned int mbps)1164 static int rcsi2_init_phtw_v3m_e3(struct rcar_csi2 *priv, unsigned int mbps)
1165 {
1166 return rcsi2_phtw_write_mbps(priv, mbps, phtw_mbps_v3m_e3, 0x44);
1167 }
1168
rcsi2_phy_post_init_v3m_e3(struct rcar_csi2 * priv)1169 static int rcsi2_phy_post_init_v3m_e3(struct rcar_csi2 *priv)
1170 {
1171 static const struct phtw_value step1[] = {
1172 { .data = 0xee, .code = 0x34 },
1173 { .data = 0xee, .code = 0x44 },
1174 { .data = 0xee, .code = 0x54 },
1175 { .data = 0xee, .code = 0x84 },
1176 { .data = 0xee, .code = 0x94 },
1177 { /* sentinel */ },
1178 };
1179
1180 return rcsi2_phtw_write_array(priv, step1);
1181 }
1182
rcsi2_init_phtw_v3u(struct rcar_csi2 * priv,unsigned int mbps)1183 static int rcsi2_init_phtw_v3u(struct rcar_csi2 *priv,
1184 unsigned int mbps)
1185 {
1186 /* In case of 1500Mbps or less */
1187 static const struct phtw_value step1[] = {
1188 { .data = 0xcc, .code = 0xe2 },
1189 { /* sentinel */ },
1190 };
1191
1192 static const struct phtw_value step2[] = {
1193 { .data = 0x01, .code = 0xe3 },
1194 { .data = 0x11, .code = 0xe4 },
1195 { .data = 0x01, .code = 0xe5 },
1196 { /* sentinel */ },
1197 };
1198
1199 /* In case of 1500Mbps or less */
1200 static const struct phtw_value step3[] = {
1201 { .data = 0x38, .code = 0x08 },
1202 { /* sentinel */ },
1203 };
1204
1205 static const struct phtw_value step4[] = {
1206 { .data = 0x01, .code = 0x00 },
1207 { .data = 0x4b, .code = 0xac },
1208 { .data = 0x03, .code = 0x00 },
1209 { .data = 0x80, .code = 0x07 },
1210 { /* sentinel */ },
1211 };
1212
1213 int ret;
1214
1215 if (mbps != 0 && mbps <= 1500)
1216 ret = rcsi2_phtw_write_array(priv, step1);
1217 else
1218 ret = rcsi2_phtw_write_mbps(priv, mbps, phtw_mbps_v3u, 0xe2);
1219 if (ret)
1220 return ret;
1221
1222 ret = rcsi2_phtw_write_array(priv, step2);
1223 if (ret)
1224 return ret;
1225
1226 if (mbps != 0 && mbps <= 1500) {
1227 ret = rcsi2_phtw_write_array(priv, step3);
1228 if (ret)
1229 return ret;
1230 }
1231
1232 ret = rcsi2_phtw_write_array(priv, step4);
1233 if (ret)
1234 return ret;
1235
1236 return ret;
1237 }
1238
1239 /* -----------------------------------------------------------------------------
1240 * Platform Device Driver.
1241 */
1242
1243 static const struct media_entity_operations rcar_csi2_entity_ops = {
1244 .link_validate = v4l2_subdev_link_validate,
1245 };
1246
rcsi2_probe_resources(struct rcar_csi2 * priv,struct platform_device * pdev)1247 static int rcsi2_probe_resources(struct rcar_csi2 *priv,
1248 struct platform_device *pdev)
1249 {
1250 int irq, ret;
1251
1252 priv->base = devm_platform_ioremap_resource(pdev, 0);
1253 if (IS_ERR(priv->base))
1254 return PTR_ERR(priv->base);
1255
1256 irq = platform_get_irq(pdev, 0);
1257 if (irq < 0)
1258 return irq;
1259
1260 ret = devm_request_threaded_irq(&pdev->dev, irq, rcsi2_irq,
1261 rcsi2_irq_thread, IRQF_SHARED,
1262 KBUILD_MODNAME, priv);
1263 if (ret)
1264 return ret;
1265
1266 priv->rstc = devm_reset_control_get(&pdev->dev, NULL);
1267
1268 return PTR_ERR_OR_ZERO(priv->rstc);
1269 }
1270
1271 static const struct rcar_csi2_info rcar_csi2_info_r8a7795 = {
1272 .init_phtw = rcsi2_init_phtw_h3_v3h_m3n,
1273 .hsfreqrange = hsfreqrange_h3_v3h_m3n,
1274 .csi0clkfreqrange = 0x20,
1275 .num_channels = 4,
1276 .clear_ulps = true,
1277 };
1278
1279 static const struct rcar_csi2_info rcar_csi2_info_r8a7795es1 = {
1280 .hsfreqrange = hsfreqrange_m3w_h3es1,
1281 .num_channels = 4,
1282 };
1283
1284 static const struct rcar_csi2_info rcar_csi2_info_r8a7795es2 = {
1285 .init_phtw = rcsi2_init_phtw_h3es2,
1286 .hsfreqrange = hsfreqrange_h3_v3h_m3n,
1287 .csi0clkfreqrange = 0x20,
1288 .num_channels = 4,
1289 .clear_ulps = true,
1290 };
1291
1292 static const struct rcar_csi2_info rcar_csi2_info_r8a7796 = {
1293 .hsfreqrange = hsfreqrange_m3w_h3es1,
1294 .num_channels = 4,
1295 };
1296
1297 static const struct rcar_csi2_info rcar_csi2_info_r8a77961 = {
1298 .hsfreqrange = hsfreqrange_m3w_h3es1,
1299 .num_channels = 4,
1300 };
1301
1302 static const struct rcar_csi2_info rcar_csi2_info_r8a77965 = {
1303 .init_phtw = rcsi2_init_phtw_h3_v3h_m3n,
1304 .hsfreqrange = hsfreqrange_h3_v3h_m3n,
1305 .csi0clkfreqrange = 0x20,
1306 .num_channels = 4,
1307 .clear_ulps = true,
1308 };
1309
1310 static const struct rcar_csi2_info rcar_csi2_info_r8a77970 = {
1311 .init_phtw = rcsi2_init_phtw_v3m_e3,
1312 .phy_post_init = rcsi2_phy_post_init_v3m_e3,
1313 .num_channels = 4,
1314 };
1315
1316 static const struct rcar_csi2_info rcar_csi2_info_r8a77980 = {
1317 .init_phtw = rcsi2_init_phtw_h3_v3h_m3n,
1318 .hsfreqrange = hsfreqrange_h3_v3h_m3n,
1319 .csi0clkfreqrange = 0x20,
1320 .clear_ulps = true,
1321 };
1322
1323 static const struct rcar_csi2_info rcar_csi2_info_r8a77990 = {
1324 .init_phtw = rcsi2_init_phtw_v3m_e3,
1325 .phy_post_init = rcsi2_phy_post_init_v3m_e3,
1326 .num_channels = 2,
1327 };
1328
1329 static const struct rcar_csi2_info rcar_csi2_info_r8a779a0 = {
1330 .init_phtw = rcsi2_init_phtw_v3u,
1331 .hsfreqrange = hsfreqrange_v3u,
1332 .csi0clkfreqrange = 0x20,
1333 .clear_ulps = true,
1334 .use_isp = true,
1335 };
1336
1337 static const struct of_device_id rcar_csi2_of_table[] = {
1338 {
1339 .compatible = "renesas,r8a774a1-csi2",
1340 .data = &rcar_csi2_info_r8a7796,
1341 },
1342 {
1343 .compatible = "renesas,r8a774b1-csi2",
1344 .data = &rcar_csi2_info_r8a77965,
1345 },
1346 {
1347 .compatible = "renesas,r8a774c0-csi2",
1348 .data = &rcar_csi2_info_r8a77990,
1349 },
1350 {
1351 .compatible = "renesas,r8a774e1-csi2",
1352 .data = &rcar_csi2_info_r8a7795,
1353 },
1354 {
1355 .compatible = "renesas,r8a7795-csi2",
1356 .data = &rcar_csi2_info_r8a7795,
1357 },
1358 {
1359 .compatible = "renesas,r8a7796-csi2",
1360 .data = &rcar_csi2_info_r8a7796,
1361 },
1362 {
1363 .compatible = "renesas,r8a77961-csi2",
1364 .data = &rcar_csi2_info_r8a77961,
1365 },
1366 {
1367 .compatible = "renesas,r8a77965-csi2",
1368 .data = &rcar_csi2_info_r8a77965,
1369 },
1370 {
1371 .compatible = "renesas,r8a77970-csi2",
1372 .data = &rcar_csi2_info_r8a77970,
1373 },
1374 {
1375 .compatible = "renesas,r8a77980-csi2",
1376 .data = &rcar_csi2_info_r8a77980,
1377 },
1378 {
1379 .compatible = "renesas,r8a77990-csi2",
1380 .data = &rcar_csi2_info_r8a77990,
1381 },
1382 {
1383 .compatible = "renesas,r8a779a0-csi2",
1384 .data = &rcar_csi2_info_r8a779a0,
1385 },
1386 { /* sentinel */ },
1387 };
1388 MODULE_DEVICE_TABLE(of, rcar_csi2_of_table);
1389
1390 static const struct soc_device_attribute r8a7795[] = {
1391 {
1392 .soc_id = "r8a7795", .revision = "ES1.*",
1393 .data = &rcar_csi2_info_r8a7795es1,
1394 },
1395 {
1396 .soc_id = "r8a7795", .revision = "ES2.*",
1397 .data = &rcar_csi2_info_r8a7795es2,
1398 },
1399 { /* sentinel */ },
1400 };
1401
rcsi2_probe(struct platform_device * pdev)1402 static int rcsi2_probe(struct platform_device *pdev)
1403 {
1404 const struct soc_device_attribute *attr;
1405 struct rcar_csi2 *priv;
1406 unsigned int i, num_pads;
1407 int ret;
1408
1409 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
1410 if (!priv)
1411 return -ENOMEM;
1412
1413 priv->info = of_device_get_match_data(&pdev->dev);
1414
1415 /*
1416 * The different ES versions of r8a7795 (H3) behave differently but
1417 * share the same compatible string.
1418 */
1419 attr = soc_device_match(r8a7795);
1420 if (attr)
1421 priv->info = attr->data;
1422
1423 priv->dev = &pdev->dev;
1424
1425 mutex_init(&priv->lock);
1426 priv->stream_count = 0;
1427
1428 ret = rcsi2_probe_resources(priv, pdev);
1429 if (ret) {
1430 dev_err(priv->dev, "Failed to get resources\n");
1431 goto error_mutex;
1432 }
1433
1434 platform_set_drvdata(pdev, priv);
1435
1436 ret = rcsi2_parse_dt(priv);
1437 if (ret)
1438 goto error_mutex;
1439
1440 priv->subdev.owner = THIS_MODULE;
1441 priv->subdev.dev = &pdev->dev;
1442 v4l2_subdev_init(&priv->subdev, &rcar_csi2_subdev_ops);
1443 v4l2_set_subdevdata(&priv->subdev, &pdev->dev);
1444 snprintf(priv->subdev.name, V4L2_SUBDEV_NAME_SIZE, "%s %s",
1445 KBUILD_MODNAME, dev_name(&pdev->dev));
1446 priv->subdev.flags = V4L2_SUBDEV_FL_HAS_DEVNODE;
1447
1448 priv->subdev.entity.function = MEDIA_ENT_F_PROC_VIDEO_PIXEL_FORMATTER;
1449 priv->subdev.entity.ops = &rcar_csi2_entity_ops;
1450
1451 num_pads = priv->info->use_isp ? 2 : NR_OF_RCAR_CSI2_PAD;
1452
1453 priv->pads[RCAR_CSI2_SINK].flags = MEDIA_PAD_FL_SINK;
1454 for (i = RCAR_CSI2_SOURCE_VC0; i < num_pads; i++)
1455 priv->pads[i].flags = MEDIA_PAD_FL_SOURCE;
1456
1457 ret = media_entity_pads_init(&priv->subdev.entity, num_pads,
1458 priv->pads);
1459 if (ret)
1460 goto error_async;
1461
1462 pm_runtime_enable(&pdev->dev);
1463
1464 ret = v4l2_async_register_subdev(&priv->subdev);
1465 if (ret < 0)
1466 goto error_async;
1467
1468 dev_info(priv->dev, "%d lanes found\n", priv->lanes);
1469
1470 return 0;
1471
1472 error_async:
1473 v4l2_async_nf_unregister(&priv->notifier);
1474 v4l2_async_nf_cleanup(&priv->notifier);
1475 error_mutex:
1476 mutex_destroy(&priv->lock);
1477
1478 return ret;
1479 }
1480
rcsi2_remove(struct platform_device * pdev)1481 static int rcsi2_remove(struct platform_device *pdev)
1482 {
1483 struct rcar_csi2 *priv = platform_get_drvdata(pdev);
1484
1485 v4l2_async_nf_unregister(&priv->notifier);
1486 v4l2_async_nf_cleanup(&priv->notifier);
1487 v4l2_async_unregister_subdev(&priv->subdev);
1488
1489 pm_runtime_disable(&pdev->dev);
1490
1491 mutex_destroy(&priv->lock);
1492
1493 return 0;
1494 }
1495
1496 static struct platform_driver rcar_csi2_pdrv = {
1497 .remove = rcsi2_remove,
1498 .probe = rcsi2_probe,
1499 .driver = {
1500 .name = "rcar-csi2",
1501 .of_match_table = rcar_csi2_of_table,
1502 },
1503 };
1504
1505 module_platform_driver(rcar_csi2_pdrv);
1506
1507 MODULE_AUTHOR("Niklas Söderlund <niklas.soderlund@ragnatech.se>");
1508 MODULE_DESCRIPTION("Renesas R-Car MIPI CSI-2 receiver driver");
1509 MODULE_LICENSE("GPL");
1510