1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Microchip KSZ9477 switch driver main logic
4 *
5 * Copyright (C) 2017-2019 Microchip Technology Inc.
6 */
7
8 #include <linux/kernel.h>
9 #include <linux/module.h>
10 #include <linux/iopoll.h>
11 #include <linux/platform_data/microchip-ksz.h>
12 #include <linux/phy.h>
13 #include <linux/if_bridge.h>
14 #include <net/dsa.h>
15 #include <net/switchdev.h>
16
17 #include "ksz9477_reg.h"
18 #include "ksz_common.h"
19
20 /* Used with variable features to indicate capabilities. */
21 #define GBIT_SUPPORT BIT(0)
22 #define NEW_XMII BIT(1)
23 #define IS_9893 BIT(2)
24
25 static const struct {
26 int index;
27 char string[ETH_GSTRING_LEN];
28 } ksz9477_mib_names[TOTAL_SWITCH_COUNTER_NUM] = {
29 { 0x00, "rx_hi" },
30 { 0x01, "rx_undersize" },
31 { 0x02, "rx_fragments" },
32 { 0x03, "rx_oversize" },
33 { 0x04, "rx_jabbers" },
34 { 0x05, "rx_symbol_err" },
35 { 0x06, "rx_crc_err" },
36 { 0x07, "rx_align_err" },
37 { 0x08, "rx_mac_ctrl" },
38 { 0x09, "rx_pause" },
39 { 0x0A, "rx_bcast" },
40 { 0x0B, "rx_mcast" },
41 { 0x0C, "rx_ucast" },
42 { 0x0D, "rx_64_or_less" },
43 { 0x0E, "rx_65_127" },
44 { 0x0F, "rx_128_255" },
45 { 0x10, "rx_256_511" },
46 { 0x11, "rx_512_1023" },
47 { 0x12, "rx_1024_1522" },
48 { 0x13, "rx_1523_2000" },
49 { 0x14, "rx_2001" },
50 { 0x15, "tx_hi" },
51 { 0x16, "tx_late_col" },
52 { 0x17, "tx_pause" },
53 { 0x18, "tx_bcast" },
54 { 0x19, "tx_mcast" },
55 { 0x1A, "tx_ucast" },
56 { 0x1B, "tx_deferred" },
57 { 0x1C, "tx_total_col" },
58 { 0x1D, "tx_exc_col" },
59 { 0x1E, "tx_single_col" },
60 { 0x1F, "tx_mult_col" },
61 { 0x80, "rx_total" },
62 { 0x81, "tx_total" },
63 { 0x82, "rx_discards" },
64 { 0x83, "tx_discards" },
65 };
66
ksz_cfg(struct ksz_device * dev,u32 addr,u8 bits,bool set)67 static void ksz_cfg(struct ksz_device *dev, u32 addr, u8 bits, bool set)
68 {
69 regmap_update_bits(dev->regmap[0], addr, bits, set ? bits : 0);
70 }
71
ksz_port_cfg(struct ksz_device * dev,int port,int offset,u8 bits,bool set)72 static void ksz_port_cfg(struct ksz_device *dev, int port, int offset, u8 bits,
73 bool set)
74 {
75 regmap_update_bits(dev->regmap[0], PORT_CTRL_ADDR(port, offset),
76 bits, set ? bits : 0);
77 }
78
ksz9477_cfg32(struct ksz_device * dev,u32 addr,u32 bits,bool set)79 static void ksz9477_cfg32(struct ksz_device *dev, u32 addr, u32 bits, bool set)
80 {
81 regmap_update_bits(dev->regmap[2], addr, bits, set ? bits : 0);
82 }
83
ksz9477_port_cfg32(struct ksz_device * dev,int port,int offset,u32 bits,bool set)84 static void ksz9477_port_cfg32(struct ksz_device *dev, int port, int offset,
85 u32 bits, bool set)
86 {
87 regmap_update_bits(dev->regmap[2], PORT_CTRL_ADDR(port, offset),
88 bits, set ? bits : 0);
89 }
90
ksz9477_wait_vlan_ctrl_ready(struct ksz_device * dev)91 static int ksz9477_wait_vlan_ctrl_ready(struct ksz_device *dev)
92 {
93 unsigned int val;
94
95 return regmap_read_poll_timeout(dev->regmap[0], REG_SW_VLAN_CTRL,
96 val, !(val & VLAN_START), 10, 1000);
97 }
98
ksz9477_get_vlan_table(struct ksz_device * dev,u16 vid,u32 * vlan_table)99 static int ksz9477_get_vlan_table(struct ksz_device *dev, u16 vid,
100 u32 *vlan_table)
101 {
102 int ret;
103
104 mutex_lock(&dev->vlan_mutex);
105
106 ksz_write16(dev, REG_SW_VLAN_ENTRY_INDEX__2, vid & VLAN_INDEX_M);
107 ksz_write8(dev, REG_SW_VLAN_CTRL, VLAN_READ | VLAN_START);
108
109 /* wait to be cleared */
110 ret = ksz9477_wait_vlan_ctrl_ready(dev);
111 if (ret) {
112 dev_dbg(dev->dev, "Failed to read vlan table\n");
113 goto exit;
114 }
115
116 ksz_read32(dev, REG_SW_VLAN_ENTRY__4, &vlan_table[0]);
117 ksz_read32(dev, REG_SW_VLAN_ENTRY_UNTAG__4, &vlan_table[1]);
118 ksz_read32(dev, REG_SW_VLAN_ENTRY_PORTS__4, &vlan_table[2]);
119
120 ksz_write8(dev, REG_SW_VLAN_CTRL, 0);
121
122 exit:
123 mutex_unlock(&dev->vlan_mutex);
124
125 return ret;
126 }
127
ksz9477_set_vlan_table(struct ksz_device * dev,u16 vid,u32 * vlan_table)128 static int ksz9477_set_vlan_table(struct ksz_device *dev, u16 vid,
129 u32 *vlan_table)
130 {
131 int ret;
132
133 mutex_lock(&dev->vlan_mutex);
134
135 ksz_write32(dev, REG_SW_VLAN_ENTRY__4, vlan_table[0]);
136 ksz_write32(dev, REG_SW_VLAN_ENTRY_UNTAG__4, vlan_table[1]);
137 ksz_write32(dev, REG_SW_VLAN_ENTRY_PORTS__4, vlan_table[2]);
138
139 ksz_write16(dev, REG_SW_VLAN_ENTRY_INDEX__2, vid & VLAN_INDEX_M);
140 ksz_write8(dev, REG_SW_VLAN_CTRL, VLAN_START | VLAN_WRITE);
141
142 /* wait to be cleared */
143 ret = ksz9477_wait_vlan_ctrl_ready(dev);
144 if (ret) {
145 dev_dbg(dev->dev, "Failed to write vlan table\n");
146 goto exit;
147 }
148
149 ksz_write8(dev, REG_SW_VLAN_CTRL, 0);
150
151 /* update vlan cache table */
152 dev->vlan_cache[vid].table[0] = vlan_table[0];
153 dev->vlan_cache[vid].table[1] = vlan_table[1];
154 dev->vlan_cache[vid].table[2] = vlan_table[2];
155
156 exit:
157 mutex_unlock(&dev->vlan_mutex);
158
159 return ret;
160 }
161
ksz9477_read_table(struct ksz_device * dev,u32 * table)162 static void ksz9477_read_table(struct ksz_device *dev, u32 *table)
163 {
164 ksz_read32(dev, REG_SW_ALU_VAL_A, &table[0]);
165 ksz_read32(dev, REG_SW_ALU_VAL_B, &table[1]);
166 ksz_read32(dev, REG_SW_ALU_VAL_C, &table[2]);
167 ksz_read32(dev, REG_SW_ALU_VAL_D, &table[3]);
168 }
169
ksz9477_write_table(struct ksz_device * dev,u32 * table)170 static void ksz9477_write_table(struct ksz_device *dev, u32 *table)
171 {
172 ksz_write32(dev, REG_SW_ALU_VAL_A, table[0]);
173 ksz_write32(dev, REG_SW_ALU_VAL_B, table[1]);
174 ksz_write32(dev, REG_SW_ALU_VAL_C, table[2]);
175 ksz_write32(dev, REG_SW_ALU_VAL_D, table[3]);
176 }
177
ksz9477_wait_alu_ready(struct ksz_device * dev)178 static int ksz9477_wait_alu_ready(struct ksz_device *dev)
179 {
180 unsigned int val;
181
182 return regmap_read_poll_timeout(dev->regmap[2], REG_SW_ALU_CTRL__4,
183 val, !(val & ALU_START), 10, 1000);
184 }
185
ksz9477_wait_alu_sta_ready(struct ksz_device * dev)186 static int ksz9477_wait_alu_sta_ready(struct ksz_device *dev)
187 {
188 unsigned int val;
189
190 return regmap_read_poll_timeout(dev->regmap[2],
191 REG_SW_ALU_STAT_CTRL__4,
192 val, !(val & ALU_STAT_START),
193 10, 1000);
194 }
195
ksz9477_reset_switch(struct ksz_device * dev)196 static int ksz9477_reset_switch(struct ksz_device *dev)
197 {
198 u8 data8;
199 u32 data32;
200
201 /* reset switch */
202 ksz_cfg(dev, REG_SW_OPERATION, SW_RESET, true);
203
204 /* turn off SPI DO Edge select */
205 regmap_update_bits(dev->regmap[0], REG_SW_GLOBAL_SERIAL_CTRL_0,
206 SPI_AUTO_EDGE_DETECTION, 0);
207
208 /* default configuration */
209 ksz_read8(dev, REG_SW_LUE_CTRL_1, &data8);
210 data8 = SW_AGING_ENABLE | SW_LINK_AUTO_AGING |
211 SW_SRC_ADDR_FILTER | SW_FLUSH_STP_TABLE | SW_FLUSH_MSTP_TABLE;
212 ksz_write8(dev, REG_SW_LUE_CTRL_1, data8);
213
214 /* disable interrupts */
215 ksz_write32(dev, REG_SW_INT_MASK__4, SWITCH_INT_MASK);
216 ksz_write32(dev, REG_SW_PORT_INT_MASK__4, 0x7F);
217 ksz_read32(dev, REG_SW_PORT_INT_STATUS__4, &data32);
218
219 /* set broadcast storm protection 10% rate */
220 regmap_update_bits(dev->regmap[1], REG_SW_MAC_CTRL_2,
221 BROADCAST_STORM_RATE,
222 (BROADCAST_STORM_VALUE *
223 BROADCAST_STORM_PROT_RATE) / 100);
224
225 if (dev->synclko_125)
226 ksz_write8(dev, REG_SW_GLOBAL_OUTPUT_CTRL__1,
227 SW_ENABLE_REFCLKO | SW_REFCLKO_IS_125MHZ);
228
229 return 0;
230 }
231
ksz9477_r_mib_cnt(struct ksz_device * dev,int port,u16 addr,u64 * cnt)232 static void ksz9477_r_mib_cnt(struct ksz_device *dev, int port, u16 addr,
233 u64 *cnt)
234 {
235 struct ksz_port *p = &dev->ports[port];
236 unsigned int val;
237 u32 data;
238 int ret;
239
240 /* retain the flush/freeze bit */
241 data = p->freeze ? MIB_COUNTER_FLUSH_FREEZE : 0;
242 data |= MIB_COUNTER_READ;
243 data |= (addr << MIB_COUNTER_INDEX_S);
244 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, data);
245
246 ret = regmap_read_poll_timeout(dev->regmap[2],
247 PORT_CTRL_ADDR(port, REG_PORT_MIB_CTRL_STAT__4),
248 val, !(val & MIB_COUNTER_READ), 10, 1000);
249 /* failed to read MIB. get out of loop */
250 if (ret) {
251 dev_dbg(dev->dev, "Failed to get MIB\n");
252 return;
253 }
254
255 /* count resets upon read */
256 ksz_pread32(dev, port, REG_PORT_MIB_DATA, &data);
257 *cnt += data;
258 }
259
ksz9477_r_mib_pkt(struct ksz_device * dev,int port,u16 addr,u64 * dropped,u64 * cnt)260 static void ksz9477_r_mib_pkt(struct ksz_device *dev, int port, u16 addr,
261 u64 *dropped, u64 *cnt)
262 {
263 addr = ksz9477_mib_names[addr].index;
264 ksz9477_r_mib_cnt(dev, port, addr, cnt);
265 }
266
ksz9477_freeze_mib(struct ksz_device * dev,int port,bool freeze)267 static void ksz9477_freeze_mib(struct ksz_device *dev, int port, bool freeze)
268 {
269 u32 val = freeze ? MIB_COUNTER_FLUSH_FREEZE : 0;
270 struct ksz_port *p = &dev->ports[port];
271
272 /* enable/disable the port for flush/freeze function */
273 mutex_lock(&p->mib.cnt_mutex);
274 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, val);
275
276 /* used by MIB counter reading code to know freeze is enabled */
277 p->freeze = freeze;
278 mutex_unlock(&p->mib.cnt_mutex);
279 }
280
ksz9477_port_init_cnt(struct ksz_device * dev,int port)281 static void ksz9477_port_init_cnt(struct ksz_device *dev, int port)
282 {
283 struct ksz_port_mib *mib = &dev->ports[port].mib;
284
285 /* flush all enabled port MIB counters */
286 mutex_lock(&mib->cnt_mutex);
287 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4,
288 MIB_COUNTER_FLUSH_FREEZE);
289 ksz_write8(dev, REG_SW_MAC_CTRL_6, SW_MIB_COUNTER_FLUSH);
290 ksz_pwrite32(dev, port, REG_PORT_MIB_CTRL_STAT__4, 0);
291 mutex_unlock(&mib->cnt_mutex);
292
293 mib->cnt_ptr = 0;
294 memset(mib->counters, 0, dev->mib_cnt * sizeof(u64));
295 }
296
ksz9477_get_tag_protocol(struct dsa_switch * ds,int port,enum dsa_tag_protocol mp)297 static enum dsa_tag_protocol ksz9477_get_tag_protocol(struct dsa_switch *ds,
298 int port,
299 enum dsa_tag_protocol mp)
300 {
301 enum dsa_tag_protocol proto = DSA_TAG_PROTO_KSZ9477;
302 struct ksz_device *dev = ds->priv;
303
304 if (dev->features & IS_9893)
305 proto = DSA_TAG_PROTO_KSZ9893;
306 return proto;
307 }
308
ksz9477_phy_read16(struct dsa_switch * ds,int addr,int reg)309 static int ksz9477_phy_read16(struct dsa_switch *ds, int addr, int reg)
310 {
311 struct ksz_device *dev = ds->priv;
312 u16 val = 0xffff;
313
314 /* No real PHY after this. Simulate the PHY.
315 * A fixed PHY can be setup in the device tree, but this function is
316 * still called for that port during initialization.
317 * For RGMII PHY there is no way to access it so the fixed PHY should
318 * be used. For SGMII PHY the supporting code will be added later.
319 */
320 if (addr >= dev->phy_port_cnt) {
321 struct ksz_port *p = &dev->ports[addr];
322
323 switch (reg) {
324 case MII_BMCR:
325 val = 0x1140;
326 break;
327 case MII_BMSR:
328 val = 0x796d;
329 break;
330 case MII_PHYSID1:
331 val = 0x0022;
332 break;
333 case MII_PHYSID2:
334 val = 0x1631;
335 break;
336 case MII_ADVERTISE:
337 val = 0x05e1;
338 break;
339 case MII_LPA:
340 val = 0xc5e1;
341 break;
342 case MII_CTRL1000:
343 val = 0x0700;
344 break;
345 case MII_STAT1000:
346 if (p->phydev.speed == SPEED_1000)
347 val = 0x3800;
348 else
349 val = 0;
350 break;
351 }
352 } else {
353 ksz_pread16(dev, addr, 0x100 + (reg << 1), &val);
354 }
355
356 return val;
357 }
358
ksz9477_phy_write16(struct dsa_switch * ds,int addr,int reg,u16 val)359 static int ksz9477_phy_write16(struct dsa_switch *ds, int addr, int reg,
360 u16 val)
361 {
362 struct ksz_device *dev = ds->priv;
363
364 /* No real PHY after this. */
365 if (addr >= dev->phy_port_cnt)
366 return 0;
367
368 /* No gigabit support. Do not write to this register. */
369 if (!(dev->features & GBIT_SUPPORT) && reg == MII_CTRL1000)
370 return 0;
371 ksz_pwrite16(dev, addr, 0x100 + (reg << 1), val);
372
373 return 0;
374 }
375
ksz9477_get_strings(struct dsa_switch * ds,int port,u32 stringset,uint8_t * buf)376 static void ksz9477_get_strings(struct dsa_switch *ds, int port,
377 u32 stringset, uint8_t *buf)
378 {
379 int i;
380
381 if (stringset != ETH_SS_STATS)
382 return;
383
384 for (i = 0; i < TOTAL_SWITCH_COUNTER_NUM; i++) {
385 memcpy(buf + i * ETH_GSTRING_LEN, ksz9477_mib_names[i].string,
386 ETH_GSTRING_LEN);
387 }
388 }
389
ksz9477_cfg_port_member(struct ksz_device * dev,int port,u8 member)390 static void ksz9477_cfg_port_member(struct ksz_device *dev, int port,
391 u8 member)
392 {
393 ksz_pwrite32(dev, port, REG_PORT_VLAN_MEMBERSHIP__4, member);
394 }
395
ksz9477_port_stp_state_set(struct dsa_switch * ds,int port,u8 state)396 static void ksz9477_port_stp_state_set(struct dsa_switch *ds, int port,
397 u8 state)
398 {
399 struct ksz_device *dev = ds->priv;
400 struct ksz_port *p = &dev->ports[port];
401 u8 data;
402
403 ksz_pread8(dev, port, P_STP_CTRL, &data);
404 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE);
405
406 switch (state) {
407 case BR_STATE_DISABLED:
408 data |= PORT_LEARN_DISABLE;
409 break;
410 case BR_STATE_LISTENING:
411 data |= (PORT_RX_ENABLE | PORT_LEARN_DISABLE);
412 break;
413 case BR_STATE_LEARNING:
414 data |= PORT_RX_ENABLE;
415 break;
416 case BR_STATE_FORWARDING:
417 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE);
418 break;
419 case BR_STATE_BLOCKING:
420 data |= PORT_LEARN_DISABLE;
421 break;
422 default:
423 dev_err(ds->dev, "invalid STP state: %d\n", state);
424 return;
425 }
426
427 ksz_pwrite8(dev, port, P_STP_CTRL, data);
428 p->stp_state = state;
429
430 ksz_update_port_member(dev, port);
431 }
432
ksz9477_flush_dyn_mac_table(struct ksz_device * dev,int port)433 static void ksz9477_flush_dyn_mac_table(struct ksz_device *dev, int port)
434 {
435 u8 data;
436
437 regmap_update_bits(dev->regmap[0], REG_SW_LUE_CTRL_2,
438 SW_FLUSH_OPTION_M << SW_FLUSH_OPTION_S,
439 SW_FLUSH_OPTION_DYN_MAC << SW_FLUSH_OPTION_S);
440
441 if (port < dev->port_cnt) {
442 /* flush individual port */
443 ksz_pread8(dev, port, P_STP_CTRL, &data);
444 if (!(data & PORT_LEARN_DISABLE))
445 ksz_pwrite8(dev, port, P_STP_CTRL,
446 data | PORT_LEARN_DISABLE);
447 ksz_cfg(dev, S_FLUSH_TABLE_CTRL, SW_FLUSH_DYN_MAC_TABLE, true);
448 ksz_pwrite8(dev, port, P_STP_CTRL, data);
449 } else {
450 /* flush all */
451 ksz_cfg(dev, S_FLUSH_TABLE_CTRL, SW_FLUSH_STP_TABLE, true);
452 }
453 }
454
ksz9477_port_vlan_filtering(struct dsa_switch * ds,int port,bool flag,struct netlink_ext_ack * extack)455 static int ksz9477_port_vlan_filtering(struct dsa_switch *ds, int port,
456 bool flag,
457 struct netlink_ext_ack *extack)
458 {
459 struct ksz_device *dev = ds->priv;
460
461 if (flag) {
462 ksz_port_cfg(dev, port, REG_PORT_LUE_CTRL,
463 PORT_VLAN_LOOKUP_VID_0, true);
464 ksz_cfg(dev, REG_SW_LUE_CTRL_0, SW_VLAN_ENABLE, true);
465 } else {
466 ksz_cfg(dev, REG_SW_LUE_CTRL_0, SW_VLAN_ENABLE, false);
467 ksz_port_cfg(dev, port, REG_PORT_LUE_CTRL,
468 PORT_VLAN_LOOKUP_VID_0, false);
469 }
470
471 return 0;
472 }
473
ksz9477_port_vlan_add(struct dsa_switch * ds,int port,const struct switchdev_obj_port_vlan * vlan,struct netlink_ext_ack * extack)474 static int ksz9477_port_vlan_add(struct dsa_switch *ds, int port,
475 const struct switchdev_obj_port_vlan *vlan,
476 struct netlink_ext_ack *extack)
477 {
478 struct ksz_device *dev = ds->priv;
479 u32 vlan_table[3];
480 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
481 int err;
482
483 err = ksz9477_get_vlan_table(dev, vlan->vid, vlan_table);
484 if (err) {
485 NL_SET_ERR_MSG_MOD(extack, "Failed to get vlan table");
486 return err;
487 }
488
489 vlan_table[0] = VLAN_VALID | (vlan->vid & VLAN_FID_M);
490 if (untagged)
491 vlan_table[1] |= BIT(port);
492 else
493 vlan_table[1] &= ~BIT(port);
494 vlan_table[1] &= ~(BIT(dev->cpu_port));
495
496 vlan_table[2] |= BIT(port) | BIT(dev->cpu_port);
497
498 err = ksz9477_set_vlan_table(dev, vlan->vid, vlan_table);
499 if (err) {
500 NL_SET_ERR_MSG_MOD(extack, "Failed to set vlan table");
501 return err;
502 }
503
504 /* change PVID */
505 if (vlan->flags & BRIDGE_VLAN_INFO_PVID)
506 ksz_pwrite16(dev, port, REG_PORT_DEFAULT_VID, vlan->vid);
507
508 return 0;
509 }
510
ksz9477_port_vlan_del(struct dsa_switch * ds,int port,const struct switchdev_obj_port_vlan * vlan)511 static int ksz9477_port_vlan_del(struct dsa_switch *ds, int port,
512 const struct switchdev_obj_port_vlan *vlan)
513 {
514 struct ksz_device *dev = ds->priv;
515 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
516 u32 vlan_table[3];
517 u16 pvid;
518
519 ksz_pread16(dev, port, REG_PORT_DEFAULT_VID, &pvid);
520 pvid = pvid & 0xFFF;
521
522 if (ksz9477_get_vlan_table(dev, vlan->vid, vlan_table)) {
523 dev_dbg(dev->dev, "Failed to get vlan table\n");
524 return -ETIMEDOUT;
525 }
526
527 vlan_table[2] &= ~BIT(port);
528
529 if (pvid == vlan->vid)
530 pvid = 1;
531
532 if (untagged)
533 vlan_table[1] &= ~BIT(port);
534
535 if (ksz9477_set_vlan_table(dev, vlan->vid, vlan_table)) {
536 dev_dbg(dev->dev, "Failed to set vlan table\n");
537 return -ETIMEDOUT;
538 }
539
540 ksz_pwrite16(dev, port, REG_PORT_DEFAULT_VID, pvid);
541
542 return 0;
543 }
544
ksz9477_port_fdb_add(struct dsa_switch * ds,int port,const unsigned char * addr,u16 vid)545 static int ksz9477_port_fdb_add(struct dsa_switch *ds, int port,
546 const unsigned char *addr, u16 vid)
547 {
548 struct ksz_device *dev = ds->priv;
549 u32 alu_table[4];
550 u32 data;
551 int ret = 0;
552
553 mutex_lock(&dev->alu_mutex);
554
555 /* find any entry with mac & vid */
556 data = vid << ALU_FID_INDEX_S;
557 data |= ((addr[0] << 8) | addr[1]);
558 ksz_write32(dev, REG_SW_ALU_INDEX_0, data);
559
560 data = ((addr[2] << 24) | (addr[3] << 16));
561 data |= ((addr[4] << 8) | addr[5]);
562 ksz_write32(dev, REG_SW_ALU_INDEX_1, data);
563
564 /* start read operation */
565 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_READ | ALU_START);
566
567 /* wait to be finished */
568 ret = ksz9477_wait_alu_ready(dev);
569 if (ret) {
570 dev_dbg(dev->dev, "Failed to read ALU\n");
571 goto exit;
572 }
573
574 /* read ALU entry */
575 ksz9477_read_table(dev, alu_table);
576
577 /* update ALU entry */
578 alu_table[0] = ALU_V_STATIC_VALID;
579 alu_table[1] |= BIT(port);
580 if (vid)
581 alu_table[1] |= ALU_V_USE_FID;
582 alu_table[2] = (vid << ALU_V_FID_S);
583 alu_table[2] |= ((addr[0] << 8) | addr[1]);
584 alu_table[3] = ((addr[2] << 24) | (addr[3] << 16));
585 alu_table[3] |= ((addr[4] << 8) | addr[5]);
586
587 ksz9477_write_table(dev, alu_table);
588
589 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_WRITE | ALU_START);
590
591 /* wait to be finished */
592 ret = ksz9477_wait_alu_ready(dev);
593 if (ret)
594 dev_dbg(dev->dev, "Failed to write ALU\n");
595
596 exit:
597 mutex_unlock(&dev->alu_mutex);
598
599 return ret;
600 }
601
ksz9477_port_fdb_del(struct dsa_switch * ds,int port,const unsigned char * addr,u16 vid)602 static int ksz9477_port_fdb_del(struct dsa_switch *ds, int port,
603 const unsigned char *addr, u16 vid)
604 {
605 struct ksz_device *dev = ds->priv;
606 u32 alu_table[4];
607 u32 data;
608 int ret = 0;
609
610 mutex_lock(&dev->alu_mutex);
611
612 /* read any entry with mac & vid */
613 data = vid << ALU_FID_INDEX_S;
614 data |= ((addr[0] << 8) | addr[1]);
615 ksz_write32(dev, REG_SW_ALU_INDEX_0, data);
616
617 data = ((addr[2] << 24) | (addr[3] << 16));
618 data |= ((addr[4] << 8) | addr[5]);
619 ksz_write32(dev, REG_SW_ALU_INDEX_1, data);
620
621 /* start read operation */
622 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_READ | ALU_START);
623
624 /* wait to be finished */
625 ret = ksz9477_wait_alu_ready(dev);
626 if (ret) {
627 dev_dbg(dev->dev, "Failed to read ALU\n");
628 goto exit;
629 }
630
631 ksz_read32(dev, REG_SW_ALU_VAL_A, &alu_table[0]);
632 if (alu_table[0] & ALU_V_STATIC_VALID) {
633 ksz_read32(dev, REG_SW_ALU_VAL_B, &alu_table[1]);
634 ksz_read32(dev, REG_SW_ALU_VAL_C, &alu_table[2]);
635 ksz_read32(dev, REG_SW_ALU_VAL_D, &alu_table[3]);
636
637 /* clear forwarding port */
638 alu_table[2] &= ~BIT(port);
639
640 /* if there is no port to forward, clear table */
641 if ((alu_table[2] & ALU_V_PORT_MAP) == 0) {
642 alu_table[0] = 0;
643 alu_table[1] = 0;
644 alu_table[2] = 0;
645 alu_table[3] = 0;
646 }
647 } else {
648 alu_table[0] = 0;
649 alu_table[1] = 0;
650 alu_table[2] = 0;
651 alu_table[3] = 0;
652 }
653
654 ksz9477_write_table(dev, alu_table);
655
656 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_WRITE | ALU_START);
657
658 /* wait to be finished */
659 ret = ksz9477_wait_alu_ready(dev);
660 if (ret)
661 dev_dbg(dev->dev, "Failed to write ALU\n");
662
663 exit:
664 mutex_unlock(&dev->alu_mutex);
665
666 return ret;
667 }
668
ksz9477_convert_alu(struct alu_struct * alu,u32 * alu_table)669 static void ksz9477_convert_alu(struct alu_struct *alu, u32 *alu_table)
670 {
671 alu->is_static = !!(alu_table[0] & ALU_V_STATIC_VALID);
672 alu->is_src_filter = !!(alu_table[0] & ALU_V_SRC_FILTER);
673 alu->is_dst_filter = !!(alu_table[0] & ALU_V_DST_FILTER);
674 alu->prio_age = (alu_table[0] >> ALU_V_PRIO_AGE_CNT_S) &
675 ALU_V_PRIO_AGE_CNT_M;
676 alu->mstp = alu_table[0] & ALU_V_MSTP_M;
677
678 alu->is_override = !!(alu_table[1] & ALU_V_OVERRIDE);
679 alu->is_use_fid = !!(alu_table[1] & ALU_V_USE_FID);
680 alu->port_forward = alu_table[1] & ALU_V_PORT_MAP;
681
682 alu->fid = (alu_table[2] >> ALU_V_FID_S) & ALU_V_FID_M;
683
684 alu->mac[0] = (alu_table[2] >> 8) & 0xFF;
685 alu->mac[1] = alu_table[2] & 0xFF;
686 alu->mac[2] = (alu_table[3] >> 24) & 0xFF;
687 alu->mac[3] = (alu_table[3] >> 16) & 0xFF;
688 alu->mac[4] = (alu_table[3] >> 8) & 0xFF;
689 alu->mac[5] = alu_table[3] & 0xFF;
690 }
691
ksz9477_port_fdb_dump(struct dsa_switch * ds,int port,dsa_fdb_dump_cb_t * cb,void * data)692 static int ksz9477_port_fdb_dump(struct dsa_switch *ds, int port,
693 dsa_fdb_dump_cb_t *cb, void *data)
694 {
695 struct ksz_device *dev = ds->priv;
696 int ret = 0;
697 u32 ksz_data;
698 u32 alu_table[4];
699 struct alu_struct alu;
700 int timeout;
701
702 mutex_lock(&dev->alu_mutex);
703
704 /* start ALU search */
705 ksz_write32(dev, REG_SW_ALU_CTRL__4, ALU_START | ALU_SEARCH);
706
707 do {
708 timeout = 1000;
709 do {
710 ksz_read32(dev, REG_SW_ALU_CTRL__4, &ksz_data);
711 if ((ksz_data & ALU_VALID) || !(ksz_data & ALU_START))
712 break;
713 usleep_range(1, 10);
714 } while (timeout-- > 0);
715
716 if (!timeout) {
717 dev_dbg(dev->dev, "Failed to search ALU\n");
718 ret = -ETIMEDOUT;
719 goto exit;
720 }
721
722 /* read ALU table */
723 ksz9477_read_table(dev, alu_table);
724
725 ksz9477_convert_alu(&alu, alu_table);
726
727 if (alu.port_forward & BIT(port)) {
728 ret = cb(alu.mac, alu.fid, alu.is_static, data);
729 if (ret)
730 goto exit;
731 }
732 } while (ksz_data & ALU_START);
733
734 exit:
735
736 /* stop ALU search */
737 ksz_write32(dev, REG_SW_ALU_CTRL__4, 0);
738
739 mutex_unlock(&dev->alu_mutex);
740
741 return ret;
742 }
743
ksz9477_port_mdb_add(struct dsa_switch * ds,int port,const struct switchdev_obj_port_mdb * mdb)744 static int ksz9477_port_mdb_add(struct dsa_switch *ds, int port,
745 const struct switchdev_obj_port_mdb *mdb)
746 {
747 struct ksz_device *dev = ds->priv;
748 u32 static_table[4];
749 u32 data;
750 int index;
751 u32 mac_hi, mac_lo;
752 int err = 0;
753
754 mac_hi = ((mdb->addr[0] << 8) | mdb->addr[1]);
755 mac_lo = ((mdb->addr[2] << 24) | (mdb->addr[3] << 16));
756 mac_lo |= ((mdb->addr[4] << 8) | mdb->addr[5]);
757
758 mutex_lock(&dev->alu_mutex);
759
760 for (index = 0; index < dev->num_statics; index++) {
761 /* find empty slot first */
762 data = (index << ALU_STAT_INDEX_S) |
763 ALU_STAT_READ | ALU_STAT_START;
764 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data);
765
766 /* wait to be finished */
767 err = ksz9477_wait_alu_sta_ready(dev);
768 if (err) {
769 dev_dbg(dev->dev, "Failed to read ALU STATIC\n");
770 goto exit;
771 }
772
773 /* read ALU static table */
774 ksz9477_read_table(dev, static_table);
775
776 if (static_table[0] & ALU_V_STATIC_VALID) {
777 /* check this has same vid & mac address */
778 if (((static_table[2] >> ALU_V_FID_S) == mdb->vid) &&
779 ((static_table[2] & ALU_V_MAC_ADDR_HI) == mac_hi) &&
780 static_table[3] == mac_lo) {
781 /* found matching one */
782 break;
783 }
784 } else {
785 /* found empty one */
786 break;
787 }
788 }
789
790 /* no available entry */
791 if (index == dev->num_statics) {
792 err = -ENOSPC;
793 goto exit;
794 }
795
796 /* add entry */
797 static_table[0] = ALU_V_STATIC_VALID;
798 static_table[1] |= BIT(port);
799 if (mdb->vid)
800 static_table[1] |= ALU_V_USE_FID;
801 static_table[2] = (mdb->vid << ALU_V_FID_S);
802 static_table[2] |= mac_hi;
803 static_table[3] = mac_lo;
804
805 ksz9477_write_table(dev, static_table);
806
807 data = (index << ALU_STAT_INDEX_S) | ALU_STAT_START;
808 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data);
809
810 /* wait to be finished */
811 if (ksz9477_wait_alu_sta_ready(dev))
812 dev_dbg(dev->dev, "Failed to read ALU STATIC\n");
813
814 exit:
815 mutex_unlock(&dev->alu_mutex);
816 return err;
817 }
818
ksz9477_port_mdb_del(struct dsa_switch * ds,int port,const struct switchdev_obj_port_mdb * mdb)819 static int ksz9477_port_mdb_del(struct dsa_switch *ds, int port,
820 const struct switchdev_obj_port_mdb *mdb)
821 {
822 struct ksz_device *dev = ds->priv;
823 u32 static_table[4];
824 u32 data;
825 int index;
826 int ret = 0;
827 u32 mac_hi, mac_lo;
828
829 mac_hi = ((mdb->addr[0] << 8) | mdb->addr[1]);
830 mac_lo = ((mdb->addr[2] << 24) | (mdb->addr[3] << 16));
831 mac_lo |= ((mdb->addr[4] << 8) | mdb->addr[5]);
832
833 mutex_lock(&dev->alu_mutex);
834
835 for (index = 0; index < dev->num_statics; index++) {
836 /* find empty slot first */
837 data = (index << ALU_STAT_INDEX_S) |
838 ALU_STAT_READ | ALU_STAT_START;
839 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data);
840
841 /* wait to be finished */
842 ret = ksz9477_wait_alu_sta_ready(dev);
843 if (ret) {
844 dev_dbg(dev->dev, "Failed to read ALU STATIC\n");
845 goto exit;
846 }
847
848 /* read ALU static table */
849 ksz9477_read_table(dev, static_table);
850
851 if (static_table[0] & ALU_V_STATIC_VALID) {
852 /* check this has same vid & mac address */
853
854 if (((static_table[2] >> ALU_V_FID_S) == mdb->vid) &&
855 ((static_table[2] & ALU_V_MAC_ADDR_HI) == mac_hi) &&
856 static_table[3] == mac_lo) {
857 /* found matching one */
858 break;
859 }
860 }
861 }
862
863 /* no available entry */
864 if (index == dev->num_statics)
865 goto exit;
866
867 /* clear port */
868 static_table[1] &= ~BIT(port);
869
870 if ((static_table[1] & ALU_V_PORT_MAP) == 0) {
871 /* delete entry */
872 static_table[0] = 0;
873 static_table[1] = 0;
874 static_table[2] = 0;
875 static_table[3] = 0;
876 }
877
878 ksz9477_write_table(dev, static_table);
879
880 data = (index << ALU_STAT_INDEX_S) | ALU_STAT_START;
881 ksz_write32(dev, REG_SW_ALU_STAT_CTRL__4, data);
882
883 /* wait to be finished */
884 ret = ksz9477_wait_alu_sta_ready(dev);
885 if (ret)
886 dev_dbg(dev->dev, "Failed to read ALU STATIC\n");
887
888 exit:
889 mutex_unlock(&dev->alu_mutex);
890
891 return ret;
892 }
893
ksz9477_port_mirror_add(struct dsa_switch * ds,int port,struct dsa_mall_mirror_tc_entry * mirror,bool ingress)894 static int ksz9477_port_mirror_add(struct dsa_switch *ds, int port,
895 struct dsa_mall_mirror_tc_entry *mirror,
896 bool ingress)
897 {
898 struct ksz_device *dev = ds->priv;
899
900 if (ingress)
901 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, true);
902 else
903 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, true);
904
905 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_SNIFFER, false);
906
907 /* configure mirror port */
908 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL,
909 PORT_MIRROR_SNIFFER, true);
910
911 ksz_cfg(dev, S_MIRROR_CTRL, SW_MIRROR_RX_TX, false);
912
913 return 0;
914 }
915
ksz9477_port_mirror_del(struct dsa_switch * ds,int port,struct dsa_mall_mirror_tc_entry * mirror)916 static void ksz9477_port_mirror_del(struct dsa_switch *ds, int port,
917 struct dsa_mall_mirror_tc_entry *mirror)
918 {
919 struct ksz_device *dev = ds->priv;
920 u8 data;
921
922 if (mirror->ingress)
923 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, false);
924 else
925 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, false);
926
927 ksz_pread8(dev, port, P_MIRROR_CTRL, &data);
928
929 if (!(data & (PORT_MIRROR_RX | PORT_MIRROR_TX)))
930 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL,
931 PORT_MIRROR_SNIFFER, false);
932 }
933
ksz9477_get_gbit(struct ksz_device * dev,u8 data)934 static bool ksz9477_get_gbit(struct ksz_device *dev, u8 data)
935 {
936 bool gbit;
937
938 if (dev->features & NEW_XMII)
939 gbit = !(data & PORT_MII_NOT_1GBIT);
940 else
941 gbit = !!(data & PORT_MII_1000MBIT_S1);
942 return gbit;
943 }
944
ksz9477_set_gbit(struct ksz_device * dev,bool gbit,u8 * data)945 static void ksz9477_set_gbit(struct ksz_device *dev, bool gbit, u8 *data)
946 {
947 if (dev->features & NEW_XMII) {
948 if (gbit)
949 *data &= ~PORT_MII_NOT_1GBIT;
950 else
951 *data |= PORT_MII_NOT_1GBIT;
952 } else {
953 if (gbit)
954 *data |= PORT_MII_1000MBIT_S1;
955 else
956 *data &= ~PORT_MII_1000MBIT_S1;
957 }
958 }
959
ksz9477_get_xmii(struct ksz_device * dev,u8 data)960 static int ksz9477_get_xmii(struct ksz_device *dev, u8 data)
961 {
962 int mode;
963
964 if (dev->features & NEW_XMII) {
965 switch (data & PORT_MII_SEL_M) {
966 case PORT_MII_SEL:
967 mode = 0;
968 break;
969 case PORT_RMII_SEL:
970 mode = 1;
971 break;
972 case PORT_GMII_SEL:
973 mode = 2;
974 break;
975 default:
976 mode = 3;
977 }
978 } else {
979 switch (data & PORT_MII_SEL_M) {
980 case PORT_MII_SEL_S1:
981 mode = 0;
982 break;
983 case PORT_RMII_SEL_S1:
984 mode = 1;
985 break;
986 case PORT_GMII_SEL_S1:
987 mode = 2;
988 break;
989 default:
990 mode = 3;
991 }
992 }
993 return mode;
994 }
995
ksz9477_set_xmii(struct ksz_device * dev,int mode,u8 * data)996 static void ksz9477_set_xmii(struct ksz_device *dev, int mode, u8 *data)
997 {
998 u8 xmii;
999
1000 if (dev->features & NEW_XMII) {
1001 switch (mode) {
1002 case 0:
1003 xmii = PORT_MII_SEL;
1004 break;
1005 case 1:
1006 xmii = PORT_RMII_SEL;
1007 break;
1008 case 2:
1009 xmii = PORT_GMII_SEL;
1010 break;
1011 default:
1012 xmii = PORT_RGMII_SEL;
1013 break;
1014 }
1015 } else {
1016 switch (mode) {
1017 case 0:
1018 xmii = PORT_MII_SEL_S1;
1019 break;
1020 case 1:
1021 xmii = PORT_RMII_SEL_S1;
1022 break;
1023 case 2:
1024 xmii = PORT_GMII_SEL_S1;
1025 break;
1026 default:
1027 xmii = PORT_RGMII_SEL_S1;
1028 break;
1029 }
1030 }
1031 *data &= ~PORT_MII_SEL_M;
1032 *data |= xmii;
1033 }
1034
ksz9477_get_interface(struct ksz_device * dev,int port)1035 static phy_interface_t ksz9477_get_interface(struct ksz_device *dev, int port)
1036 {
1037 phy_interface_t interface;
1038 bool gbit;
1039 int mode;
1040 u8 data8;
1041
1042 if (port < dev->phy_port_cnt)
1043 return PHY_INTERFACE_MODE_NA;
1044 ksz_pread8(dev, port, REG_PORT_XMII_CTRL_1, &data8);
1045 gbit = ksz9477_get_gbit(dev, data8);
1046 mode = ksz9477_get_xmii(dev, data8);
1047 switch (mode) {
1048 case 2:
1049 interface = PHY_INTERFACE_MODE_GMII;
1050 if (gbit)
1051 break;
1052 fallthrough;
1053 case 0:
1054 interface = PHY_INTERFACE_MODE_MII;
1055 break;
1056 case 1:
1057 interface = PHY_INTERFACE_MODE_RMII;
1058 break;
1059 default:
1060 interface = PHY_INTERFACE_MODE_RGMII;
1061 if (data8 & PORT_RGMII_ID_EG_ENABLE)
1062 interface = PHY_INTERFACE_MODE_RGMII_TXID;
1063 if (data8 & PORT_RGMII_ID_IG_ENABLE) {
1064 interface = PHY_INTERFACE_MODE_RGMII_RXID;
1065 if (data8 & PORT_RGMII_ID_EG_ENABLE)
1066 interface = PHY_INTERFACE_MODE_RGMII_ID;
1067 }
1068 break;
1069 }
1070 return interface;
1071 }
1072
ksz9477_port_mmd_write(struct ksz_device * dev,int port,u8 dev_addr,u16 reg_addr,u16 val)1073 static void ksz9477_port_mmd_write(struct ksz_device *dev, int port,
1074 u8 dev_addr, u16 reg_addr, u16 val)
1075 {
1076 ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_SETUP,
1077 MMD_SETUP(PORT_MMD_OP_INDEX, dev_addr));
1078 ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_INDEX_DATA, reg_addr);
1079 ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_SETUP,
1080 MMD_SETUP(PORT_MMD_OP_DATA_NO_INCR, dev_addr));
1081 ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_INDEX_DATA, val);
1082 }
1083
ksz9477_phy_errata_setup(struct ksz_device * dev,int port)1084 static void ksz9477_phy_errata_setup(struct ksz_device *dev, int port)
1085 {
1086 /* Apply PHY settings to address errata listed in
1087 * KSZ9477, KSZ9897, KSZ9896, KSZ9567, KSZ8565
1088 * Silicon Errata and Data Sheet Clarification documents:
1089 *
1090 * Register settings are needed to improve PHY receive performance
1091 */
1092 ksz9477_port_mmd_write(dev, port, 0x01, 0x6f, 0xdd0b);
1093 ksz9477_port_mmd_write(dev, port, 0x01, 0x8f, 0x6032);
1094 ksz9477_port_mmd_write(dev, port, 0x01, 0x9d, 0x248c);
1095 ksz9477_port_mmd_write(dev, port, 0x01, 0x75, 0x0060);
1096 ksz9477_port_mmd_write(dev, port, 0x01, 0xd3, 0x7777);
1097 ksz9477_port_mmd_write(dev, port, 0x1c, 0x06, 0x3008);
1098 ksz9477_port_mmd_write(dev, port, 0x1c, 0x08, 0x2001);
1099
1100 /* Transmit waveform amplitude can be improved
1101 * (1000BASE-T, 100BASE-TX, 10BASE-Te)
1102 */
1103 ksz9477_port_mmd_write(dev, port, 0x1c, 0x04, 0x00d0);
1104
1105 /* Energy Efficient Ethernet (EEE) feature select must
1106 * be manually disabled (except on KSZ8565 which is 100Mbit)
1107 */
1108 if (dev->features & GBIT_SUPPORT)
1109 ksz9477_port_mmd_write(dev, port, 0x07, 0x3c, 0x0000);
1110
1111 /* Register settings are required to meet data sheet
1112 * supply current specifications
1113 */
1114 ksz9477_port_mmd_write(dev, port, 0x1c, 0x13, 0x6eff);
1115 ksz9477_port_mmd_write(dev, port, 0x1c, 0x14, 0xe6ff);
1116 ksz9477_port_mmd_write(dev, port, 0x1c, 0x15, 0x6eff);
1117 ksz9477_port_mmd_write(dev, port, 0x1c, 0x16, 0xe6ff);
1118 ksz9477_port_mmd_write(dev, port, 0x1c, 0x17, 0x00ff);
1119 ksz9477_port_mmd_write(dev, port, 0x1c, 0x18, 0x43ff);
1120 ksz9477_port_mmd_write(dev, port, 0x1c, 0x19, 0xc3ff);
1121 ksz9477_port_mmd_write(dev, port, 0x1c, 0x1a, 0x6fff);
1122 ksz9477_port_mmd_write(dev, port, 0x1c, 0x1b, 0x07ff);
1123 ksz9477_port_mmd_write(dev, port, 0x1c, 0x1c, 0x0fff);
1124 ksz9477_port_mmd_write(dev, port, 0x1c, 0x1d, 0xe7ff);
1125 ksz9477_port_mmd_write(dev, port, 0x1c, 0x1e, 0xefff);
1126 ksz9477_port_mmd_write(dev, port, 0x1c, 0x20, 0xeeee);
1127 }
1128
ksz9477_port_setup(struct ksz_device * dev,int port,bool cpu_port)1129 static void ksz9477_port_setup(struct ksz_device *dev, int port, bool cpu_port)
1130 {
1131 struct ksz_port *p = &dev->ports[port];
1132 struct dsa_switch *ds = dev->ds;
1133 u8 data8, member;
1134 u16 data16;
1135
1136 /* enable tag tail for host port */
1137 if (cpu_port)
1138 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, PORT_TAIL_TAG_ENABLE,
1139 true);
1140
1141 ksz_port_cfg(dev, port, REG_PORT_CTRL_0, PORT_MAC_LOOPBACK, false);
1142
1143 /* set back pressure */
1144 ksz_port_cfg(dev, port, REG_PORT_MAC_CTRL_1, PORT_BACK_PRESSURE, true);
1145
1146 /* enable broadcast storm limit */
1147 ksz_port_cfg(dev, port, P_BCAST_STORM_CTRL, PORT_BROADCAST_STORM, true);
1148
1149 /* disable DiffServ priority */
1150 ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_DIFFSERV_PRIO_ENABLE, false);
1151
1152 /* replace priority */
1153 ksz_port_cfg(dev, port, REG_PORT_MRI_MAC_CTRL, PORT_USER_PRIO_CEILING,
1154 false);
1155 ksz9477_port_cfg32(dev, port, REG_PORT_MTI_QUEUE_CTRL_0__4,
1156 MTI_PVID_REPLACE, false);
1157
1158 /* enable 802.1p priority */
1159 ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_802_1P_PRIO_ENABLE, true);
1160
1161 if (port < dev->phy_port_cnt) {
1162 /* do not force flow control */
1163 ksz_port_cfg(dev, port, REG_PORT_CTRL_0,
1164 PORT_FORCE_TX_FLOW_CTRL | PORT_FORCE_RX_FLOW_CTRL,
1165 false);
1166
1167 if (dev->phy_errata_9477)
1168 ksz9477_phy_errata_setup(dev, port);
1169 } else {
1170 /* force flow control */
1171 ksz_port_cfg(dev, port, REG_PORT_CTRL_0,
1172 PORT_FORCE_TX_FLOW_CTRL | PORT_FORCE_RX_FLOW_CTRL,
1173 true);
1174
1175 /* configure MAC to 1G & RGMII mode */
1176 ksz_pread8(dev, port, REG_PORT_XMII_CTRL_1, &data8);
1177 switch (p->interface) {
1178 case PHY_INTERFACE_MODE_MII:
1179 ksz9477_set_xmii(dev, 0, &data8);
1180 ksz9477_set_gbit(dev, false, &data8);
1181 p->phydev.speed = SPEED_100;
1182 break;
1183 case PHY_INTERFACE_MODE_RMII:
1184 ksz9477_set_xmii(dev, 1, &data8);
1185 ksz9477_set_gbit(dev, false, &data8);
1186 p->phydev.speed = SPEED_100;
1187 break;
1188 case PHY_INTERFACE_MODE_GMII:
1189 ksz9477_set_xmii(dev, 2, &data8);
1190 ksz9477_set_gbit(dev, true, &data8);
1191 p->phydev.speed = SPEED_1000;
1192 break;
1193 default:
1194 ksz9477_set_xmii(dev, 3, &data8);
1195 ksz9477_set_gbit(dev, true, &data8);
1196 data8 &= ~PORT_RGMII_ID_IG_ENABLE;
1197 data8 &= ~PORT_RGMII_ID_EG_ENABLE;
1198 if (p->interface == PHY_INTERFACE_MODE_RGMII_ID ||
1199 p->interface == PHY_INTERFACE_MODE_RGMII_RXID)
1200 data8 |= PORT_RGMII_ID_IG_ENABLE;
1201 if (p->interface == PHY_INTERFACE_MODE_RGMII_ID ||
1202 p->interface == PHY_INTERFACE_MODE_RGMII_TXID)
1203 data8 |= PORT_RGMII_ID_EG_ENABLE;
1204 /* On KSZ9893, disable RGMII in-band status support */
1205 if (dev->features & IS_9893)
1206 data8 &= ~PORT_MII_MAC_MODE;
1207 p->phydev.speed = SPEED_1000;
1208 break;
1209 }
1210 ksz_pwrite8(dev, port, REG_PORT_XMII_CTRL_1, data8);
1211 p->phydev.duplex = 1;
1212 }
1213
1214 if (cpu_port)
1215 member = dsa_user_ports(ds);
1216 else
1217 member = BIT(dsa_upstream_port(ds, port));
1218
1219 ksz9477_cfg_port_member(dev, port, member);
1220
1221 /* clear pending interrupts */
1222 if (port < dev->phy_port_cnt)
1223 ksz_pread16(dev, port, REG_PORT_PHY_INT_ENABLE, &data16);
1224 }
1225
ksz9477_config_cpu_port(struct dsa_switch * ds)1226 static void ksz9477_config_cpu_port(struct dsa_switch *ds)
1227 {
1228 struct ksz_device *dev = ds->priv;
1229 struct ksz_port *p;
1230 int i;
1231
1232 for (i = 0; i < dev->port_cnt; i++) {
1233 if (dsa_is_cpu_port(ds, i) && (dev->cpu_ports & (1 << i))) {
1234 phy_interface_t interface;
1235 const char *prev_msg;
1236 const char *prev_mode;
1237
1238 dev->cpu_port = i;
1239 p = &dev->ports[i];
1240
1241 /* Read from XMII register to determine host port
1242 * interface. If set specifically in device tree
1243 * note the difference to help debugging.
1244 */
1245 interface = ksz9477_get_interface(dev, i);
1246 if (!p->interface) {
1247 if (dev->compat_interface) {
1248 dev_warn(dev->dev,
1249 "Using legacy switch \"phy-mode\" property, because it is missing on port %d node. "
1250 "Please update your device tree.\n",
1251 i);
1252 p->interface = dev->compat_interface;
1253 } else {
1254 p->interface = interface;
1255 }
1256 }
1257 if (interface && interface != p->interface) {
1258 prev_msg = " instead of ";
1259 prev_mode = phy_modes(interface);
1260 } else {
1261 prev_msg = "";
1262 prev_mode = "";
1263 }
1264 dev_info(dev->dev,
1265 "Port%d: using phy mode %s%s%s\n",
1266 i,
1267 phy_modes(p->interface),
1268 prev_msg,
1269 prev_mode);
1270
1271 /* enable cpu port */
1272 ksz9477_port_setup(dev, i, true);
1273 p->on = 1;
1274 }
1275 }
1276
1277 for (i = 0; i < dev->port_cnt; i++) {
1278 if (i == dev->cpu_port)
1279 continue;
1280 p = &dev->ports[i];
1281
1282 ksz9477_port_stp_state_set(ds, i, BR_STATE_DISABLED);
1283 p->on = 1;
1284 if (i < dev->phy_port_cnt)
1285 p->phy = 1;
1286 if (dev->chip_id == 0x00947700 && i == 6) {
1287 p->sgmii = 1;
1288
1289 /* SGMII PHY detection code is not implemented yet. */
1290 p->phy = 0;
1291 }
1292 }
1293 }
1294
ksz9477_setup(struct dsa_switch * ds)1295 static int ksz9477_setup(struct dsa_switch *ds)
1296 {
1297 struct ksz_device *dev = ds->priv;
1298 int ret = 0;
1299
1300 dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table),
1301 dev->num_vlans, GFP_KERNEL);
1302 if (!dev->vlan_cache)
1303 return -ENOMEM;
1304
1305 ret = ksz9477_reset_switch(dev);
1306 if (ret) {
1307 dev_err(ds->dev, "failed to reset switch\n");
1308 return ret;
1309 }
1310
1311 /* Required for port partitioning. */
1312 ksz9477_cfg32(dev, REG_SW_QM_CTRL__4, UNICAST_VLAN_BOUNDARY,
1313 true);
1314
1315 /* Do not work correctly with tail tagging. */
1316 ksz_cfg(dev, REG_SW_MAC_CTRL_0, SW_CHECK_LENGTH, false);
1317
1318 /* accept packet up to 2000bytes */
1319 ksz_cfg(dev, REG_SW_MAC_CTRL_1, SW_LEGAL_PACKET_DISABLE, true);
1320
1321 ksz9477_config_cpu_port(ds);
1322
1323 ksz_cfg(dev, REG_SW_MAC_CTRL_1, MULTICAST_STORM_DISABLE, true);
1324
1325 /* queue based egress rate limit */
1326 ksz_cfg(dev, REG_SW_MAC_CTRL_5, SW_OUT_RATE_LIMIT_QUEUE_BASED, true);
1327
1328 /* enable global MIB counter freeze function */
1329 ksz_cfg(dev, REG_SW_MAC_CTRL_6, SW_MIB_COUNTER_FREEZE, true);
1330
1331 /* start switch */
1332 ksz_cfg(dev, REG_SW_OPERATION, SW_START, true);
1333
1334 ksz_init_mib_timer(dev);
1335
1336 ds->configure_vlan_while_not_filtering = false;
1337
1338 return 0;
1339 }
1340
1341 static const struct dsa_switch_ops ksz9477_switch_ops = {
1342 .get_tag_protocol = ksz9477_get_tag_protocol,
1343 .setup = ksz9477_setup,
1344 .phy_read = ksz9477_phy_read16,
1345 .phy_write = ksz9477_phy_write16,
1346 .phylink_mac_link_down = ksz_mac_link_down,
1347 .port_enable = ksz_enable_port,
1348 .get_strings = ksz9477_get_strings,
1349 .get_ethtool_stats = ksz_get_ethtool_stats,
1350 .get_sset_count = ksz_sset_count,
1351 .port_bridge_join = ksz_port_bridge_join,
1352 .port_bridge_leave = ksz_port_bridge_leave,
1353 .port_stp_state_set = ksz9477_port_stp_state_set,
1354 .port_fast_age = ksz_port_fast_age,
1355 .port_vlan_filtering = ksz9477_port_vlan_filtering,
1356 .port_vlan_add = ksz9477_port_vlan_add,
1357 .port_vlan_del = ksz9477_port_vlan_del,
1358 .port_fdb_dump = ksz9477_port_fdb_dump,
1359 .port_fdb_add = ksz9477_port_fdb_add,
1360 .port_fdb_del = ksz9477_port_fdb_del,
1361 .port_mdb_add = ksz9477_port_mdb_add,
1362 .port_mdb_del = ksz9477_port_mdb_del,
1363 .port_mirror_add = ksz9477_port_mirror_add,
1364 .port_mirror_del = ksz9477_port_mirror_del,
1365 };
1366
ksz9477_get_port_addr(int port,int offset)1367 static u32 ksz9477_get_port_addr(int port, int offset)
1368 {
1369 return PORT_CTRL_ADDR(port, offset);
1370 }
1371
ksz9477_switch_detect(struct ksz_device * dev)1372 static int ksz9477_switch_detect(struct ksz_device *dev)
1373 {
1374 u8 data8;
1375 u8 id_hi;
1376 u8 id_lo;
1377 u32 id32;
1378 int ret;
1379
1380 /* turn off SPI DO Edge select */
1381 ret = ksz_read8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, &data8);
1382 if (ret)
1383 return ret;
1384
1385 data8 &= ~SPI_AUTO_EDGE_DETECTION;
1386 ret = ksz_write8(dev, REG_SW_GLOBAL_SERIAL_CTRL_0, data8);
1387 if (ret)
1388 return ret;
1389
1390 /* read chip id */
1391 ret = ksz_read32(dev, REG_CHIP_ID0__1, &id32);
1392 if (ret)
1393 return ret;
1394 ret = ksz_read8(dev, REG_GLOBAL_OPTIONS, &data8);
1395 if (ret)
1396 return ret;
1397
1398 /* Number of ports can be reduced depending on chip. */
1399 dev->phy_port_cnt = 5;
1400
1401 /* Default capability is gigabit capable. */
1402 dev->features = GBIT_SUPPORT;
1403
1404 dev_dbg(dev->dev, "Switch detect: ID=%08x%02x\n", id32, data8);
1405 id_hi = (u8)(id32 >> 16);
1406 id_lo = (u8)(id32 >> 8);
1407 if ((id_lo & 0xf) == 3) {
1408 /* Chip is from KSZ9893 design. */
1409 dev_info(dev->dev, "Found KSZ9893\n");
1410 dev->features |= IS_9893;
1411
1412 /* Chip does not support gigabit. */
1413 if (data8 & SW_QW_ABLE)
1414 dev->features &= ~GBIT_SUPPORT;
1415 dev->phy_port_cnt = 2;
1416 } else {
1417 dev_info(dev->dev, "Found KSZ9477 or compatible\n");
1418 /* Chip uses new XMII register definitions. */
1419 dev->features |= NEW_XMII;
1420
1421 /* Chip does not support gigabit. */
1422 if (!(data8 & SW_GIGABIT_ABLE))
1423 dev->features &= ~GBIT_SUPPORT;
1424 }
1425
1426 /* Change chip id to known ones so it can be matched against them. */
1427 id32 = (id_hi << 16) | (id_lo << 8);
1428
1429 dev->chip_id = id32;
1430
1431 return 0;
1432 }
1433
1434 struct ksz_chip_data {
1435 u32 chip_id;
1436 const char *dev_name;
1437 int num_vlans;
1438 int num_alus;
1439 int num_statics;
1440 int cpu_ports;
1441 int port_cnt;
1442 bool phy_errata_9477;
1443 };
1444
1445 static const struct ksz_chip_data ksz9477_switch_chips[] = {
1446 {
1447 .chip_id = 0x00947700,
1448 .dev_name = "KSZ9477",
1449 .num_vlans = 4096,
1450 .num_alus = 4096,
1451 .num_statics = 16,
1452 .cpu_ports = 0x7F, /* can be configured as cpu port */
1453 .port_cnt = 7, /* total physical port count */
1454 .phy_errata_9477 = true,
1455 },
1456 {
1457 .chip_id = 0x00989700,
1458 .dev_name = "KSZ9897",
1459 .num_vlans = 4096,
1460 .num_alus = 4096,
1461 .num_statics = 16,
1462 .cpu_ports = 0x7F, /* can be configured as cpu port */
1463 .port_cnt = 7, /* total physical port count */
1464 .phy_errata_9477 = true,
1465 },
1466 {
1467 .chip_id = 0x00989300,
1468 .dev_name = "KSZ9893",
1469 .num_vlans = 4096,
1470 .num_alus = 4096,
1471 .num_statics = 16,
1472 .cpu_ports = 0x07, /* can be configured as cpu port */
1473 .port_cnt = 3, /* total port count */
1474 },
1475 {
1476 .chip_id = 0x00956700,
1477 .dev_name = "KSZ9567",
1478 .num_vlans = 4096,
1479 .num_alus = 4096,
1480 .num_statics = 16,
1481 .cpu_ports = 0x7F, /* can be configured as cpu port */
1482 .port_cnt = 7, /* total physical port count */
1483 .phy_errata_9477 = true,
1484 },
1485 };
1486
ksz9477_switch_init(struct ksz_device * dev)1487 static int ksz9477_switch_init(struct ksz_device *dev)
1488 {
1489 int i;
1490
1491 dev->ds->ops = &ksz9477_switch_ops;
1492
1493 for (i = 0; i < ARRAY_SIZE(ksz9477_switch_chips); i++) {
1494 const struct ksz_chip_data *chip = &ksz9477_switch_chips[i];
1495
1496 if (dev->chip_id == chip->chip_id) {
1497 dev->name = chip->dev_name;
1498 dev->num_vlans = chip->num_vlans;
1499 dev->num_alus = chip->num_alus;
1500 dev->num_statics = chip->num_statics;
1501 dev->port_cnt = chip->port_cnt;
1502 dev->cpu_ports = chip->cpu_ports;
1503 dev->phy_errata_9477 = chip->phy_errata_9477;
1504
1505 break;
1506 }
1507 }
1508
1509 /* no switch found */
1510 if (!dev->port_cnt)
1511 return -ENODEV;
1512
1513 dev->port_mask = (1 << dev->port_cnt) - 1;
1514
1515 dev->reg_mib_cnt = SWITCH_COUNTER_NUM;
1516 dev->mib_cnt = TOTAL_SWITCH_COUNTER_NUM;
1517
1518 dev->ports = devm_kzalloc(dev->dev,
1519 dev->port_cnt * sizeof(struct ksz_port),
1520 GFP_KERNEL);
1521 if (!dev->ports)
1522 return -ENOMEM;
1523 for (i = 0; i < dev->port_cnt; i++) {
1524 mutex_init(&dev->ports[i].mib.cnt_mutex);
1525 dev->ports[i].mib.counters =
1526 devm_kzalloc(dev->dev,
1527 sizeof(u64) *
1528 (TOTAL_SWITCH_COUNTER_NUM + 1),
1529 GFP_KERNEL);
1530 if (!dev->ports[i].mib.counters)
1531 return -ENOMEM;
1532 }
1533
1534 /* set the real number of ports */
1535 dev->ds->num_ports = dev->port_cnt;
1536
1537 return 0;
1538 }
1539
ksz9477_switch_exit(struct ksz_device * dev)1540 static void ksz9477_switch_exit(struct ksz_device *dev)
1541 {
1542 ksz9477_reset_switch(dev);
1543 }
1544
1545 static const struct ksz_dev_ops ksz9477_dev_ops = {
1546 .get_port_addr = ksz9477_get_port_addr,
1547 .cfg_port_member = ksz9477_cfg_port_member,
1548 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table,
1549 .port_setup = ksz9477_port_setup,
1550 .r_mib_cnt = ksz9477_r_mib_cnt,
1551 .r_mib_pkt = ksz9477_r_mib_pkt,
1552 .freeze_mib = ksz9477_freeze_mib,
1553 .port_init_cnt = ksz9477_port_init_cnt,
1554 .shutdown = ksz9477_reset_switch,
1555 .detect = ksz9477_switch_detect,
1556 .init = ksz9477_switch_init,
1557 .exit = ksz9477_switch_exit,
1558 };
1559
ksz9477_switch_register(struct ksz_device * dev)1560 int ksz9477_switch_register(struct ksz_device *dev)
1561 {
1562 int ret, i;
1563 struct phy_device *phydev;
1564
1565 ret = ksz_switch_register(dev, &ksz9477_dev_ops);
1566 if (ret)
1567 return ret;
1568
1569 for (i = 0; i < dev->phy_port_cnt; ++i) {
1570 if (!dsa_is_user_port(dev->ds, i))
1571 continue;
1572
1573 phydev = dsa_to_port(dev->ds, i)->slave->phydev;
1574
1575 /* The MAC actually cannot run in 1000 half-duplex mode. */
1576 phy_remove_link_mode(phydev,
1577 ETHTOOL_LINK_MODE_1000baseT_Half_BIT);
1578
1579 /* PHY does not support gigabit. */
1580 if (!(dev->features & GBIT_SUPPORT))
1581 phy_remove_link_mode(phydev,
1582 ETHTOOL_LINK_MODE_1000baseT_Full_BIT);
1583 }
1584 return ret;
1585 }
1586 EXPORT_SYMBOL(ksz9477_switch_register);
1587
1588 MODULE_AUTHOR("Woojung Huh <Woojung.Huh@microchip.com>");
1589 MODULE_DESCRIPTION("Microchip KSZ9477 Series Switch DSA Driver");
1590 MODULE_LICENSE("GPL");
1591