1 /*
2 * QorIQ 10G MDIO Controller
3 *
4 * Copyright 2012 Freescale Semiconductor, Inc.
5 * Copyright 2021 NXP
6 *
7 * Authors: Andy Fleming <afleming@freescale.com>
8 * Timur Tabi <timur@freescale.com>
9 *
10 * This file is licensed under the terms of the GNU General Public License
11 * version 2. This program is licensed "as is" without any warranty of any
12 * kind, whether express or implied.
13 */
14
15 #include <linux/acpi.h>
16 #include <linux/acpi_mdio.h>
17 #include <linux/interrupt.h>
18 #include <linux/kernel.h>
19 #include <linux/mdio.h>
20 #include <linux/module.h>
21 #include <linux/of_address.h>
22 #include <linux/of_mdio.h>
23 #include <linux/of_platform.h>
24 #include <linux/phy.h>
25 #include <linux/slab.h>
26
27 /* Number of microseconds to wait for a register to respond */
28 #define TIMEOUT 1000
29
30 struct tgec_mdio_controller {
31 __be32 reserved[12];
32 __be32 mdio_stat; /* MDIO configuration and status */
33 __be32 mdio_ctl; /* MDIO control */
34 __be32 mdio_data; /* MDIO data */
35 __be32 mdio_addr; /* MDIO address */
36 } __packed;
37
38 #define MDIO_STAT_ENC BIT(6)
39 #define MDIO_STAT_CLKDIV(x) (((x>>1) & 0xff) << 8)
40 #define MDIO_STAT_BSY BIT(0)
41 #define MDIO_STAT_RD_ER BIT(1)
42 #define MDIO_CTL_DEV_ADDR(x) (x & 0x1f)
43 #define MDIO_CTL_PORT_ADDR(x) ((x & 0x1f) << 5)
44 #define MDIO_CTL_PRE_DIS BIT(10)
45 #define MDIO_CTL_SCAN_EN BIT(11)
46 #define MDIO_CTL_POST_INC BIT(14)
47 #define MDIO_CTL_READ BIT(15)
48
49 #define MDIO_DATA(x) (x & 0xffff)
50
51 struct mdio_fsl_priv {
52 struct tgec_mdio_controller __iomem *mdio_base;
53 bool is_little_endian;
54 bool has_a011043;
55 };
56
xgmac_read32(void __iomem * regs,bool is_little_endian)57 static u32 xgmac_read32(void __iomem *regs,
58 bool is_little_endian)
59 {
60 if (is_little_endian)
61 return ioread32(regs);
62 else
63 return ioread32be(regs);
64 }
65
xgmac_write32(u32 value,void __iomem * regs,bool is_little_endian)66 static void xgmac_write32(u32 value,
67 void __iomem *regs,
68 bool is_little_endian)
69 {
70 if (is_little_endian)
71 iowrite32(value, regs);
72 else
73 iowrite32be(value, regs);
74 }
75
76 /*
77 * Wait until the MDIO bus is free
78 */
xgmac_wait_until_free(struct device * dev,struct tgec_mdio_controller __iomem * regs,bool is_little_endian)79 static int xgmac_wait_until_free(struct device *dev,
80 struct tgec_mdio_controller __iomem *regs,
81 bool is_little_endian)
82 {
83 unsigned int timeout;
84
85 /* Wait till the bus is free */
86 timeout = TIMEOUT;
87 while ((xgmac_read32(®s->mdio_stat, is_little_endian) &
88 MDIO_STAT_BSY) && timeout) {
89 cpu_relax();
90 timeout--;
91 }
92
93 if (!timeout) {
94 dev_err(dev, "timeout waiting for bus to be free\n");
95 return -ETIMEDOUT;
96 }
97
98 return 0;
99 }
100
101 /*
102 * Wait till the MDIO read or write operation is complete
103 */
xgmac_wait_until_done(struct device * dev,struct tgec_mdio_controller __iomem * regs,bool is_little_endian)104 static int xgmac_wait_until_done(struct device *dev,
105 struct tgec_mdio_controller __iomem *regs,
106 bool is_little_endian)
107 {
108 unsigned int timeout;
109
110 /* Wait till the MDIO write is complete */
111 timeout = TIMEOUT;
112 while ((xgmac_read32(®s->mdio_stat, is_little_endian) &
113 MDIO_STAT_BSY) && timeout) {
114 cpu_relax();
115 timeout--;
116 }
117
118 if (!timeout) {
119 dev_err(dev, "timeout waiting for operation to complete\n");
120 return -ETIMEDOUT;
121 }
122
123 return 0;
124 }
125
126 /*
127 * Write value to the PHY for this device to the register at regnum,waiting
128 * until the write is done before it returns. All PHY configuration has to be
129 * done through the TSEC1 MIIM regs.
130 */
xgmac_mdio_write(struct mii_bus * bus,int phy_id,int regnum,u16 value)131 static int xgmac_mdio_write(struct mii_bus *bus, int phy_id, int regnum, u16 value)
132 {
133 struct mdio_fsl_priv *priv = (struct mdio_fsl_priv *)bus->priv;
134 struct tgec_mdio_controller __iomem *regs = priv->mdio_base;
135 uint16_t dev_addr;
136 u32 mdio_ctl, mdio_stat;
137 int ret;
138 bool endian = priv->is_little_endian;
139
140 mdio_stat = xgmac_read32(®s->mdio_stat, endian);
141 if (regnum & MII_ADDR_C45) {
142 /* Clause 45 (ie 10G) */
143 dev_addr = (regnum >> 16) & 0x1f;
144 mdio_stat |= MDIO_STAT_ENC;
145 } else {
146 /* Clause 22 (ie 1G) */
147 dev_addr = regnum & 0x1f;
148 mdio_stat &= ~MDIO_STAT_ENC;
149 }
150
151 xgmac_write32(mdio_stat, ®s->mdio_stat, endian);
152
153 ret = xgmac_wait_until_free(&bus->dev, regs, endian);
154 if (ret)
155 return ret;
156
157 /* Set the port and dev addr */
158 mdio_ctl = MDIO_CTL_PORT_ADDR(phy_id) | MDIO_CTL_DEV_ADDR(dev_addr);
159 xgmac_write32(mdio_ctl, ®s->mdio_ctl, endian);
160
161 /* Set the register address */
162 if (regnum & MII_ADDR_C45) {
163 xgmac_write32(regnum & 0xffff, ®s->mdio_addr, endian);
164
165 ret = xgmac_wait_until_free(&bus->dev, regs, endian);
166 if (ret)
167 return ret;
168 }
169
170 /* Write the value to the register */
171 xgmac_write32(MDIO_DATA(value), ®s->mdio_data, endian);
172
173 ret = xgmac_wait_until_done(&bus->dev, regs, endian);
174 if (ret)
175 return ret;
176
177 return 0;
178 }
179
180 /*
181 * Reads from register regnum in the PHY for device dev, returning the value.
182 * Clears miimcom first. All PHY configuration has to be done through the
183 * TSEC1 MIIM regs.
184 */
xgmac_mdio_read(struct mii_bus * bus,int phy_id,int regnum)185 static int xgmac_mdio_read(struct mii_bus *bus, int phy_id, int regnum)
186 {
187 struct mdio_fsl_priv *priv = (struct mdio_fsl_priv *)bus->priv;
188 struct tgec_mdio_controller __iomem *regs = priv->mdio_base;
189 uint16_t dev_addr;
190 uint32_t mdio_stat;
191 uint32_t mdio_ctl;
192 uint16_t value;
193 int ret;
194 bool endian = priv->is_little_endian;
195
196 mdio_stat = xgmac_read32(®s->mdio_stat, endian);
197 if (regnum & MII_ADDR_C45) {
198 dev_addr = (regnum >> 16) & 0x1f;
199 mdio_stat |= MDIO_STAT_ENC;
200 } else {
201 dev_addr = regnum & 0x1f;
202 mdio_stat &= ~MDIO_STAT_ENC;
203 }
204
205 xgmac_write32(mdio_stat, ®s->mdio_stat, endian);
206
207 ret = xgmac_wait_until_free(&bus->dev, regs, endian);
208 if (ret)
209 return ret;
210
211 /* Set the Port and Device Addrs */
212 mdio_ctl = MDIO_CTL_PORT_ADDR(phy_id) | MDIO_CTL_DEV_ADDR(dev_addr);
213 xgmac_write32(mdio_ctl, ®s->mdio_ctl, endian);
214
215 /* Set the register address */
216 if (regnum & MII_ADDR_C45) {
217 xgmac_write32(regnum & 0xffff, ®s->mdio_addr, endian);
218
219 ret = xgmac_wait_until_free(&bus->dev, regs, endian);
220 if (ret)
221 return ret;
222 }
223
224 /* Initiate the read */
225 xgmac_write32(mdio_ctl | MDIO_CTL_READ, ®s->mdio_ctl, endian);
226
227 ret = xgmac_wait_until_done(&bus->dev, regs, endian);
228 if (ret)
229 return ret;
230
231 /* Return all Fs if nothing was there */
232 if ((xgmac_read32(®s->mdio_stat, endian) & MDIO_STAT_RD_ER) &&
233 !priv->has_a011043) {
234 dev_dbg(&bus->dev,
235 "Error while reading PHY%d reg at %d.%hhu\n",
236 phy_id, dev_addr, regnum);
237 return 0xffff;
238 }
239
240 value = xgmac_read32(®s->mdio_data, endian) & 0xffff;
241 dev_dbg(&bus->dev, "read %04x\n", value);
242
243 return value;
244 }
245
xgmac_mdio_probe(struct platform_device * pdev)246 static int xgmac_mdio_probe(struct platform_device *pdev)
247 {
248 struct fwnode_handle *fwnode;
249 struct mdio_fsl_priv *priv;
250 struct resource *res;
251 struct mii_bus *bus;
252 int ret;
253
254 /* In DPAA-1, MDIO is one of the many FMan sub-devices. The FMan
255 * defines a register space that spans a large area, covering all the
256 * subdevice areas. Therefore, MDIO cannot claim exclusive access to
257 * this register area.
258 */
259 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
260 if (!res) {
261 dev_err(&pdev->dev, "could not obtain address\n");
262 return -EINVAL;
263 }
264
265 bus = mdiobus_alloc_size(sizeof(struct mdio_fsl_priv));
266 if (!bus)
267 return -ENOMEM;
268
269 bus->name = "Freescale XGMAC MDIO Bus";
270 bus->read = xgmac_mdio_read;
271 bus->write = xgmac_mdio_write;
272 bus->parent = &pdev->dev;
273 bus->probe_capabilities = MDIOBUS_C22_C45;
274 snprintf(bus->id, MII_BUS_ID_SIZE, "%pa", &res->start);
275
276 /* Set the PHY base address */
277 priv = bus->priv;
278 priv->mdio_base = ioremap(res->start, resource_size(res));
279 if (!priv->mdio_base) {
280 ret = -ENOMEM;
281 goto err_ioremap;
282 }
283
284 /* For both ACPI and DT cases, endianness of MDIO controller
285 * needs to be specified using "little-endian" property.
286 */
287 priv->is_little_endian = device_property_read_bool(&pdev->dev,
288 "little-endian");
289
290 priv->has_a011043 = device_property_read_bool(&pdev->dev,
291 "fsl,erratum-a011043");
292
293 fwnode = pdev->dev.fwnode;
294 if (is_of_node(fwnode))
295 ret = of_mdiobus_register(bus, to_of_node(fwnode));
296 else if (is_acpi_node(fwnode))
297 ret = acpi_mdiobus_register(bus, fwnode);
298 else
299 ret = -EINVAL;
300 if (ret) {
301 dev_err(&pdev->dev, "cannot register MDIO bus\n");
302 goto err_registration;
303 }
304
305 platform_set_drvdata(pdev, bus);
306
307 return 0;
308
309 err_registration:
310 iounmap(priv->mdio_base);
311
312 err_ioremap:
313 mdiobus_free(bus);
314
315 return ret;
316 }
317
xgmac_mdio_remove(struct platform_device * pdev)318 static int xgmac_mdio_remove(struct platform_device *pdev)
319 {
320 struct mii_bus *bus = platform_get_drvdata(pdev);
321
322 mdiobus_unregister(bus);
323 iounmap(bus->priv);
324 mdiobus_free(bus);
325
326 return 0;
327 }
328
329 static const struct of_device_id xgmac_mdio_match[] = {
330 {
331 .compatible = "fsl,fman-xmdio",
332 },
333 {
334 .compatible = "fsl,fman-memac-mdio",
335 },
336 {},
337 };
338 MODULE_DEVICE_TABLE(of, xgmac_mdio_match);
339
340 static const struct acpi_device_id xgmac_acpi_match[] = {
341 { "NXP0006" },
342 { }
343 };
344 MODULE_DEVICE_TABLE(acpi, xgmac_acpi_match);
345
346 static struct platform_driver xgmac_mdio_driver = {
347 .driver = {
348 .name = "fsl-fman_xmdio",
349 .of_match_table = xgmac_mdio_match,
350 .acpi_match_table = xgmac_acpi_match,
351 },
352 .probe = xgmac_mdio_probe,
353 .remove = xgmac_mdio_remove,
354 };
355
356 module_platform_driver(xgmac_mdio_driver);
357
358 MODULE_DESCRIPTION("Freescale QorIQ 10G MDIO Controller");
359 MODULE_LICENSE("GPL v2");
360