1 /*
2 * Copyright (c) 2013-2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/highmem.h>
34 #include <linux/module.h>
35 #include <linux/errno.h>
36 #include <linux/pci.h>
37 #include <linux/dma-mapping.h>
38 #include <linux/slab.h>
39 #include <linux/delay.h>
40 #include <linux/random.h>
41 #include <linux/io-mapping.h>
42 #include <linux/mlx5/driver.h>
43 #include <linux/mlx5/eq.h>
44 #include <linux/debugfs.h>
45
46 #include "mlx5_core.h"
47 #include "lib/eq.h"
48 #include "lib/tout.h"
49
50 enum {
51 CMD_IF_REV = 5,
52 };
53
54 enum {
55 CMD_MODE_POLLING,
56 CMD_MODE_EVENTS
57 };
58
59 enum {
60 MLX5_CMD_DELIVERY_STAT_OK = 0x0,
61 MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR = 0x1,
62 MLX5_CMD_DELIVERY_STAT_TOK_ERR = 0x2,
63 MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR = 0x3,
64 MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR = 0x4,
65 MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR = 0x5,
66 MLX5_CMD_DELIVERY_STAT_FW_ERR = 0x6,
67 MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR = 0x7,
68 MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR = 0x8,
69 MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR = 0x9,
70 MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR = 0x10,
71 };
72
73 static struct mlx5_cmd_work_ent *
cmd_alloc_ent(struct mlx5_cmd * cmd,struct mlx5_cmd_msg * in,struct mlx5_cmd_msg * out,void * uout,int uout_size,mlx5_cmd_cbk_t cbk,void * context,int page_queue)74 cmd_alloc_ent(struct mlx5_cmd *cmd, struct mlx5_cmd_msg *in,
75 struct mlx5_cmd_msg *out, void *uout, int uout_size,
76 mlx5_cmd_cbk_t cbk, void *context, int page_queue)
77 {
78 gfp_t alloc_flags = cbk ? GFP_ATOMIC : GFP_KERNEL;
79 struct mlx5_cmd_work_ent *ent;
80
81 ent = kzalloc(sizeof(*ent), alloc_flags);
82 if (!ent)
83 return ERR_PTR(-ENOMEM);
84
85 ent->idx = -EINVAL;
86 ent->in = in;
87 ent->out = out;
88 ent->uout = uout;
89 ent->uout_size = uout_size;
90 ent->callback = cbk;
91 ent->context = context;
92 ent->cmd = cmd;
93 ent->page_queue = page_queue;
94 refcount_set(&ent->refcnt, 1);
95
96 return ent;
97 }
98
cmd_free_ent(struct mlx5_cmd_work_ent * ent)99 static void cmd_free_ent(struct mlx5_cmd_work_ent *ent)
100 {
101 kfree(ent);
102 }
103
alloc_token(struct mlx5_cmd * cmd)104 static u8 alloc_token(struct mlx5_cmd *cmd)
105 {
106 u8 token;
107
108 spin_lock(&cmd->token_lock);
109 cmd->token++;
110 if (cmd->token == 0)
111 cmd->token++;
112 token = cmd->token;
113 spin_unlock(&cmd->token_lock);
114
115 return token;
116 }
117
cmd_alloc_index(struct mlx5_cmd * cmd)118 static int cmd_alloc_index(struct mlx5_cmd *cmd)
119 {
120 unsigned long flags;
121 int ret;
122
123 spin_lock_irqsave(&cmd->alloc_lock, flags);
124 ret = find_first_bit(&cmd->bitmask, cmd->max_reg_cmds);
125 if (ret < cmd->max_reg_cmds)
126 clear_bit(ret, &cmd->bitmask);
127 spin_unlock_irqrestore(&cmd->alloc_lock, flags);
128
129 return ret < cmd->max_reg_cmds ? ret : -ENOMEM;
130 }
131
cmd_free_index(struct mlx5_cmd * cmd,int idx)132 static void cmd_free_index(struct mlx5_cmd *cmd, int idx)
133 {
134 unsigned long flags;
135
136 spin_lock_irqsave(&cmd->alloc_lock, flags);
137 set_bit(idx, &cmd->bitmask);
138 spin_unlock_irqrestore(&cmd->alloc_lock, flags);
139 }
140
cmd_ent_get(struct mlx5_cmd_work_ent * ent)141 static void cmd_ent_get(struct mlx5_cmd_work_ent *ent)
142 {
143 refcount_inc(&ent->refcnt);
144 }
145
cmd_ent_put(struct mlx5_cmd_work_ent * ent)146 static void cmd_ent_put(struct mlx5_cmd_work_ent *ent)
147 {
148 if (!refcount_dec_and_test(&ent->refcnt))
149 return;
150
151 if (ent->idx >= 0)
152 cmd_free_index(ent->cmd, ent->idx);
153
154 cmd_free_ent(ent);
155 }
156
get_inst(struct mlx5_cmd * cmd,int idx)157 static struct mlx5_cmd_layout *get_inst(struct mlx5_cmd *cmd, int idx)
158 {
159 return cmd->cmd_buf + (idx << cmd->log_stride);
160 }
161
mlx5_calc_cmd_blocks(struct mlx5_cmd_msg * msg)162 static int mlx5_calc_cmd_blocks(struct mlx5_cmd_msg *msg)
163 {
164 int size = msg->len;
165 int blen = size - min_t(int, sizeof(msg->first.data), size);
166
167 return DIV_ROUND_UP(blen, MLX5_CMD_DATA_BLOCK_SIZE);
168 }
169
xor8_buf(void * buf,size_t offset,int len)170 static u8 xor8_buf(void *buf, size_t offset, int len)
171 {
172 u8 *ptr = buf;
173 u8 sum = 0;
174 int i;
175 int end = len + offset;
176
177 for (i = offset; i < end; i++)
178 sum ^= ptr[i];
179
180 return sum;
181 }
182
verify_block_sig(struct mlx5_cmd_prot_block * block)183 static int verify_block_sig(struct mlx5_cmd_prot_block *block)
184 {
185 size_t rsvd0_off = offsetof(struct mlx5_cmd_prot_block, rsvd0);
186 int xor_len = sizeof(*block) - sizeof(block->data) - 1;
187
188 if (xor8_buf(block, rsvd0_off, xor_len) != 0xff)
189 return -EINVAL;
190
191 if (xor8_buf(block, 0, sizeof(*block)) != 0xff)
192 return -EINVAL;
193
194 return 0;
195 }
196
calc_block_sig(struct mlx5_cmd_prot_block * block)197 static void calc_block_sig(struct mlx5_cmd_prot_block *block)
198 {
199 int ctrl_xor_len = sizeof(*block) - sizeof(block->data) - 2;
200 size_t rsvd0_off = offsetof(struct mlx5_cmd_prot_block, rsvd0);
201
202 block->ctrl_sig = ~xor8_buf(block, rsvd0_off, ctrl_xor_len);
203 block->sig = ~xor8_buf(block, 0, sizeof(*block) - 1);
204 }
205
calc_chain_sig(struct mlx5_cmd_msg * msg)206 static void calc_chain_sig(struct mlx5_cmd_msg *msg)
207 {
208 struct mlx5_cmd_mailbox *next = msg->next;
209 int n = mlx5_calc_cmd_blocks(msg);
210 int i = 0;
211
212 for (i = 0; i < n && next; i++) {
213 calc_block_sig(next->buf);
214 next = next->next;
215 }
216 }
217
set_signature(struct mlx5_cmd_work_ent * ent,int csum)218 static void set_signature(struct mlx5_cmd_work_ent *ent, int csum)
219 {
220 ent->lay->sig = ~xor8_buf(ent->lay, 0, sizeof(*ent->lay));
221 if (csum) {
222 calc_chain_sig(ent->in);
223 calc_chain_sig(ent->out);
224 }
225 }
226
poll_timeout(struct mlx5_cmd_work_ent * ent)227 static void poll_timeout(struct mlx5_cmd_work_ent *ent)
228 {
229 struct mlx5_core_dev *dev = container_of(ent->cmd, struct mlx5_core_dev, cmd);
230 u64 cmd_to_ms = mlx5_tout_ms(dev, CMD);
231 unsigned long poll_end;
232 u8 own;
233
234 poll_end = jiffies + msecs_to_jiffies(cmd_to_ms + 1000);
235
236 do {
237 own = READ_ONCE(ent->lay->status_own);
238 if (!(own & CMD_OWNER_HW)) {
239 ent->ret = 0;
240 return;
241 }
242 cond_resched();
243 } while (time_before(jiffies, poll_end));
244
245 ent->ret = -ETIMEDOUT;
246 }
247
verify_signature(struct mlx5_cmd_work_ent * ent)248 static int verify_signature(struct mlx5_cmd_work_ent *ent)
249 {
250 struct mlx5_cmd_mailbox *next = ent->out->next;
251 int n = mlx5_calc_cmd_blocks(ent->out);
252 int err;
253 u8 sig;
254 int i = 0;
255
256 sig = xor8_buf(ent->lay, 0, sizeof(*ent->lay));
257 if (sig != 0xff)
258 return -EINVAL;
259
260 for (i = 0; i < n && next; i++) {
261 err = verify_block_sig(next->buf);
262 if (err)
263 return err;
264
265 next = next->next;
266 }
267
268 return 0;
269 }
270
dump_buf(void * buf,int size,int data_only,int offset,int idx)271 static void dump_buf(void *buf, int size, int data_only, int offset, int idx)
272 {
273 __be32 *p = buf;
274 int i;
275
276 for (i = 0; i < size; i += 16) {
277 pr_debug("cmd[%d]: %03x: %08x %08x %08x %08x\n", idx, offset,
278 be32_to_cpu(p[0]), be32_to_cpu(p[1]),
279 be32_to_cpu(p[2]), be32_to_cpu(p[3]));
280 p += 4;
281 offset += 16;
282 }
283 if (!data_only)
284 pr_debug("\n");
285 }
286
mlx5_internal_err_ret_value(struct mlx5_core_dev * dev,u16 op,u32 * synd,u8 * status)287 static int mlx5_internal_err_ret_value(struct mlx5_core_dev *dev, u16 op,
288 u32 *synd, u8 *status)
289 {
290 *synd = 0;
291 *status = 0;
292
293 switch (op) {
294 case MLX5_CMD_OP_TEARDOWN_HCA:
295 case MLX5_CMD_OP_DISABLE_HCA:
296 case MLX5_CMD_OP_MANAGE_PAGES:
297 case MLX5_CMD_OP_DESTROY_MKEY:
298 case MLX5_CMD_OP_DESTROY_EQ:
299 case MLX5_CMD_OP_DESTROY_CQ:
300 case MLX5_CMD_OP_DESTROY_QP:
301 case MLX5_CMD_OP_DESTROY_PSV:
302 case MLX5_CMD_OP_DESTROY_SRQ:
303 case MLX5_CMD_OP_DESTROY_XRC_SRQ:
304 case MLX5_CMD_OP_DESTROY_XRQ:
305 case MLX5_CMD_OP_DESTROY_DCT:
306 case MLX5_CMD_OP_DEALLOC_Q_COUNTER:
307 case MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT:
308 case MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT:
309 case MLX5_CMD_OP_DEALLOC_PD:
310 case MLX5_CMD_OP_DEALLOC_UAR:
311 case MLX5_CMD_OP_DETACH_FROM_MCG:
312 case MLX5_CMD_OP_DEALLOC_XRCD:
313 case MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN:
314 case MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT:
315 case MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY:
316 case MLX5_CMD_OP_DESTROY_LAG:
317 case MLX5_CMD_OP_DESTROY_VPORT_LAG:
318 case MLX5_CMD_OP_DESTROY_TIR:
319 case MLX5_CMD_OP_DESTROY_SQ:
320 case MLX5_CMD_OP_DESTROY_RQ:
321 case MLX5_CMD_OP_DESTROY_RMP:
322 case MLX5_CMD_OP_DESTROY_TIS:
323 case MLX5_CMD_OP_DESTROY_RQT:
324 case MLX5_CMD_OP_DESTROY_FLOW_TABLE:
325 case MLX5_CMD_OP_DESTROY_FLOW_GROUP:
326 case MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY:
327 case MLX5_CMD_OP_DEALLOC_FLOW_COUNTER:
328 case MLX5_CMD_OP_2ERR_QP:
329 case MLX5_CMD_OP_2RST_QP:
330 case MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT:
331 case MLX5_CMD_OP_MODIFY_FLOW_TABLE:
332 case MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY:
333 case MLX5_CMD_OP_SET_FLOW_TABLE_ROOT:
334 case MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT:
335 case MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT:
336 case MLX5_CMD_OP_FPGA_DESTROY_QP:
337 case MLX5_CMD_OP_DESTROY_GENERAL_OBJECT:
338 case MLX5_CMD_OP_DEALLOC_MEMIC:
339 case MLX5_CMD_OP_PAGE_FAULT_RESUME:
340 case MLX5_CMD_OP_QUERY_ESW_FUNCTIONS:
341 case MLX5_CMD_OP_DEALLOC_SF:
342 case MLX5_CMD_OP_DESTROY_UCTX:
343 case MLX5_CMD_OP_DESTROY_UMEM:
344 case MLX5_CMD_OP_MODIFY_RQT:
345 return MLX5_CMD_STAT_OK;
346
347 case MLX5_CMD_OP_QUERY_HCA_CAP:
348 case MLX5_CMD_OP_QUERY_ADAPTER:
349 case MLX5_CMD_OP_INIT_HCA:
350 case MLX5_CMD_OP_ENABLE_HCA:
351 case MLX5_CMD_OP_QUERY_PAGES:
352 case MLX5_CMD_OP_SET_HCA_CAP:
353 case MLX5_CMD_OP_QUERY_ISSI:
354 case MLX5_CMD_OP_SET_ISSI:
355 case MLX5_CMD_OP_CREATE_MKEY:
356 case MLX5_CMD_OP_QUERY_MKEY:
357 case MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS:
358 case MLX5_CMD_OP_CREATE_EQ:
359 case MLX5_CMD_OP_QUERY_EQ:
360 case MLX5_CMD_OP_GEN_EQE:
361 case MLX5_CMD_OP_CREATE_CQ:
362 case MLX5_CMD_OP_QUERY_CQ:
363 case MLX5_CMD_OP_MODIFY_CQ:
364 case MLX5_CMD_OP_CREATE_QP:
365 case MLX5_CMD_OP_RST2INIT_QP:
366 case MLX5_CMD_OP_INIT2RTR_QP:
367 case MLX5_CMD_OP_RTR2RTS_QP:
368 case MLX5_CMD_OP_RTS2RTS_QP:
369 case MLX5_CMD_OP_SQERR2RTS_QP:
370 case MLX5_CMD_OP_QUERY_QP:
371 case MLX5_CMD_OP_SQD_RTS_QP:
372 case MLX5_CMD_OP_INIT2INIT_QP:
373 case MLX5_CMD_OP_CREATE_PSV:
374 case MLX5_CMD_OP_CREATE_SRQ:
375 case MLX5_CMD_OP_QUERY_SRQ:
376 case MLX5_CMD_OP_ARM_RQ:
377 case MLX5_CMD_OP_CREATE_XRC_SRQ:
378 case MLX5_CMD_OP_QUERY_XRC_SRQ:
379 case MLX5_CMD_OP_ARM_XRC_SRQ:
380 case MLX5_CMD_OP_CREATE_XRQ:
381 case MLX5_CMD_OP_QUERY_XRQ:
382 case MLX5_CMD_OP_ARM_XRQ:
383 case MLX5_CMD_OP_CREATE_DCT:
384 case MLX5_CMD_OP_DRAIN_DCT:
385 case MLX5_CMD_OP_QUERY_DCT:
386 case MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION:
387 case MLX5_CMD_OP_QUERY_VPORT_STATE:
388 case MLX5_CMD_OP_MODIFY_VPORT_STATE:
389 case MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT:
390 case MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT:
391 case MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT:
392 case MLX5_CMD_OP_QUERY_ROCE_ADDRESS:
393 case MLX5_CMD_OP_SET_ROCE_ADDRESS:
394 case MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT:
395 case MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT:
396 case MLX5_CMD_OP_QUERY_HCA_VPORT_GID:
397 case MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY:
398 case MLX5_CMD_OP_QUERY_VNIC_ENV:
399 case MLX5_CMD_OP_QUERY_VPORT_COUNTER:
400 case MLX5_CMD_OP_ALLOC_Q_COUNTER:
401 case MLX5_CMD_OP_QUERY_Q_COUNTER:
402 case MLX5_CMD_OP_SET_MONITOR_COUNTER:
403 case MLX5_CMD_OP_ARM_MONITOR_COUNTER:
404 case MLX5_CMD_OP_SET_PP_RATE_LIMIT:
405 case MLX5_CMD_OP_QUERY_RATE_LIMIT:
406 case MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT:
407 case MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT:
408 case MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT:
409 case MLX5_CMD_OP_CREATE_QOS_PARA_VPORT:
410 case MLX5_CMD_OP_ALLOC_PD:
411 case MLX5_CMD_OP_ALLOC_UAR:
412 case MLX5_CMD_OP_CONFIG_INT_MODERATION:
413 case MLX5_CMD_OP_ACCESS_REG:
414 case MLX5_CMD_OP_ATTACH_TO_MCG:
415 case MLX5_CMD_OP_GET_DROPPED_PACKET_LOG:
416 case MLX5_CMD_OP_MAD_IFC:
417 case MLX5_CMD_OP_QUERY_MAD_DEMUX:
418 case MLX5_CMD_OP_SET_MAD_DEMUX:
419 case MLX5_CMD_OP_NOP:
420 case MLX5_CMD_OP_ALLOC_XRCD:
421 case MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN:
422 case MLX5_CMD_OP_QUERY_CONG_STATUS:
423 case MLX5_CMD_OP_MODIFY_CONG_STATUS:
424 case MLX5_CMD_OP_QUERY_CONG_PARAMS:
425 case MLX5_CMD_OP_MODIFY_CONG_PARAMS:
426 case MLX5_CMD_OP_QUERY_CONG_STATISTICS:
427 case MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT:
428 case MLX5_CMD_OP_SET_L2_TABLE_ENTRY:
429 case MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY:
430 case MLX5_CMD_OP_CREATE_LAG:
431 case MLX5_CMD_OP_MODIFY_LAG:
432 case MLX5_CMD_OP_QUERY_LAG:
433 case MLX5_CMD_OP_CREATE_VPORT_LAG:
434 case MLX5_CMD_OP_CREATE_TIR:
435 case MLX5_CMD_OP_MODIFY_TIR:
436 case MLX5_CMD_OP_QUERY_TIR:
437 case MLX5_CMD_OP_CREATE_SQ:
438 case MLX5_CMD_OP_MODIFY_SQ:
439 case MLX5_CMD_OP_QUERY_SQ:
440 case MLX5_CMD_OP_CREATE_RQ:
441 case MLX5_CMD_OP_MODIFY_RQ:
442 case MLX5_CMD_OP_QUERY_RQ:
443 case MLX5_CMD_OP_CREATE_RMP:
444 case MLX5_CMD_OP_MODIFY_RMP:
445 case MLX5_CMD_OP_QUERY_RMP:
446 case MLX5_CMD_OP_CREATE_TIS:
447 case MLX5_CMD_OP_MODIFY_TIS:
448 case MLX5_CMD_OP_QUERY_TIS:
449 case MLX5_CMD_OP_CREATE_RQT:
450 case MLX5_CMD_OP_QUERY_RQT:
451
452 case MLX5_CMD_OP_CREATE_FLOW_TABLE:
453 case MLX5_CMD_OP_QUERY_FLOW_TABLE:
454 case MLX5_CMD_OP_CREATE_FLOW_GROUP:
455 case MLX5_CMD_OP_QUERY_FLOW_GROUP:
456 case MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY:
457 case MLX5_CMD_OP_ALLOC_FLOW_COUNTER:
458 case MLX5_CMD_OP_QUERY_FLOW_COUNTER:
459 case MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT:
460 case MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT:
461 case MLX5_CMD_OP_FPGA_CREATE_QP:
462 case MLX5_CMD_OP_FPGA_MODIFY_QP:
463 case MLX5_CMD_OP_FPGA_QUERY_QP:
464 case MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS:
465 case MLX5_CMD_OP_CREATE_GENERAL_OBJECT:
466 case MLX5_CMD_OP_MODIFY_GENERAL_OBJECT:
467 case MLX5_CMD_OP_QUERY_GENERAL_OBJECT:
468 case MLX5_CMD_OP_CREATE_UCTX:
469 case MLX5_CMD_OP_CREATE_UMEM:
470 case MLX5_CMD_OP_ALLOC_MEMIC:
471 case MLX5_CMD_OP_MODIFY_XRQ:
472 case MLX5_CMD_OP_RELEASE_XRQ_ERROR:
473 case MLX5_CMD_OP_QUERY_VHCA_STATE:
474 case MLX5_CMD_OP_MODIFY_VHCA_STATE:
475 case MLX5_CMD_OP_ALLOC_SF:
476 *status = MLX5_DRIVER_STATUS_ABORTED;
477 *synd = MLX5_DRIVER_SYND;
478 return -EIO;
479 default:
480 mlx5_core_err(dev, "Unknown FW command (%d)\n", op);
481 return -EINVAL;
482 }
483 }
484
mlx5_command_str(int command)485 const char *mlx5_command_str(int command)
486 {
487 #define MLX5_COMMAND_STR_CASE(__cmd) case MLX5_CMD_OP_ ## __cmd: return #__cmd
488
489 switch (command) {
490 MLX5_COMMAND_STR_CASE(QUERY_HCA_CAP);
491 MLX5_COMMAND_STR_CASE(QUERY_ADAPTER);
492 MLX5_COMMAND_STR_CASE(INIT_HCA);
493 MLX5_COMMAND_STR_CASE(TEARDOWN_HCA);
494 MLX5_COMMAND_STR_CASE(ENABLE_HCA);
495 MLX5_COMMAND_STR_CASE(DISABLE_HCA);
496 MLX5_COMMAND_STR_CASE(QUERY_PAGES);
497 MLX5_COMMAND_STR_CASE(MANAGE_PAGES);
498 MLX5_COMMAND_STR_CASE(SET_HCA_CAP);
499 MLX5_COMMAND_STR_CASE(QUERY_ISSI);
500 MLX5_COMMAND_STR_CASE(SET_ISSI);
501 MLX5_COMMAND_STR_CASE(SET_DRIVER_VERSION);
502 MLX5_COMMAND_STR_CASE(CREATE_MKEY);
503 MLX5_COMMAND_STR_CASE(QUERY_MKEY);
504 MLX5_COMMAND_STR_CASE(DESTROY_MKEY);
505 MLX5_COMMAND_STR_CASE(QUERY_SPECIAL_CONTEXTS);
506 MLX5_COMMAND_STR_CASE(PAGE_FAULT_RESUME);
507 MLX5_COMMAND_STR_CASE(CREATE_EQ);
508 MLX5_COMMAND_STR_CASE(DESTROY_EQ);
509 MLX5_COMMAND_STR_CASE(QUERY_EQ);
510 MLX5_COMMAND_STR_CASE(GEN_EQE);
511 MLX5_COMMAND_STR_CASE(CREATE_CQ);
512 MLX5_COMMAND_STR_CASE(DESTROY_CQ);
513 MLX5_COMMAND_STR_CASE(QUERY_CQ);
514 MLX5_COMMAND_STR_CASE(MODIFY_CQ);
515 MLX5_COMMAND_STR_CASE(CREATE_QP);
516 MLX5_COMMAND_STR_CASE(DESTROY_QP);
517 MLX5_COMMAND_STR_CASE(RST2INIT_QP);
518 MLX5_COMMAND_STR_CASE(INIT2RTR_QP);
519 MLX5_COMMAND_STR_CASE(RTR2RTS_QP);
520 MLX5_COMMAND_STR_CASE(RTS2RTS_QP);
521 MLX5_COMMAND_STR_CASE(SQERR2RTS_QP);
522 MLX5_COMMAND_STR_CASE(2ERR_QP);
523 MLX5_COMMAND_STR_CASE(2RST_QP);
524 MLX5_COMMAND_STR_CASE(QUERY_QP);
525 MLX5_COMMAND_STR_CASE(SQD_RTS_QP);
526 MLX5_COMMAND_STR_CASE(INIT2INIT_QP);
527 MLX5_COMMAND_STR_CASE(CREATE_PSV);
528 MLX5_COMMAND_STR_CASE(DESTROY_PSV);
529 MLX5_COMMAND_STR_CASE(CREATE_SRQ);
530 MLX5_COMMAND_STR_CASE(DESTROY_SRQ);
531 MLX5_COMMAND_STR_CASE(QUERY_SRQ);
532 MLX5_COMMAND_STR_CASE(ARM_RQ);
533 MLX5_COMMAND_STR_CASE(CREATE_XRC_SRQ);
534 MLX5_COMMAND_STR_CASE(DESTROY_XRC_SRQ);
535 MLX5_COMMAND_STR_CASE(QUERY_XRC_SRQ);
536 MLX5_COMMAND_STR_CASE(ARM_XRC_SRQ);
537 MLX5_COMMAND_STR_CASE(CREATE_DCT);
538 MLX5_COMMAND_STR_CASE(DESTROY_DCT);
539 MLX5_COMMAND_STR_CASE(DRAIN_DCT);
540 MLX5_COMMAND_STR_CASE(QUERY_DCT);
541 MLX5_COMMAND_STR_CASE(ARM_DCT_FOR_KEY_VIOLATION);
542 MLX5_COMMAND_STR_CASE(QUERY_VPORT_STATE);
543 MLX5_COMMAND_STR_CASE(MODIFY_VPORT_STATE);
544 MLX5_COMMAND_STR_CASE(QUERY_ESW_VPORT_CONTEXT);
545 MLX5_COMMAND_STR_CASE(MODIFY_ESW_VPORT_CONTEXT);
546 MLX5_COMMAND_STR_CASE(QUERY_NIC_VPORT_CONTEXT);
547 MLX5_COMMAND_STR_CASE(MODIFY_NIC_VPORT_CONTEXT);
548 MLX5_COMMAND_STR_CASE(QUERY_ROCE_ADDRESS);
549 MLX5_COMMAND_STR_CASE(SET_ROCE_ADDRESS);
550 MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_CONTEXT);
551 MLX5_COMMAND_STR_CASE(MODIFY_HCA_VPORT_CONTEXT);
552 MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_GID);
553 MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_PKEY);
554 MLX5_COMMAND_STR_CASE(QUERY_VNIC_ENV);
555 MLX5_COMMAND_STR_CASE(QUERY_VPORT_COUNTER);
556 MLX5_COMMAND_STR_CASE(ALLOC_Q_COUNTER);
557 MLX5_COMMAND_STR_CASE(DEALLOC_Q_COUNTER);
558 MLX5_COMMAND_STR_CASE(QUERY_Q_COUNTER);
559 MLX5_COMMAND_STR_CASE(SET_MONITOR_COUNTER);
560 MLX5_COMMAND_STR_CASE(ARM_MONITOR_COUNTER);
561 MLX5_COMMAND_STR_CASE(SET_PP_RATE_LIMIT);
562 MLX5_COMMAND_STR_CASE(QUERY_RATE_LIMIT);
563 MLX5_COMMAND_STR_CASE(CREATE_SCHEDULING_ELEMENT);
564 MLX5_COMMAND_STR_CASE(DESTROY_SCHEDULING_ELEMENT);
565 MLX5_COMMAND_STR_CASE(QUERY_SCHEDULING_ELEMENT);
566 MLX5_COMMAND_STR_CASE(MODIFY_SCHEDULING_ELEMENT);
567 MLX5_COMMAND_STR_CASE(CREATE_QOS_PARA_VPORT);
568 MLX5_COMMAND_STR_CASE(DESTROY_QOS_PARA_VPORT);
569 MLX5_COMMAND_STR_CASE(ALLOC_PD);
570 MLX5_COMMAND_STR_CASE(DEALLOC_PD);
571 MLX5_COMMAND_STR_CASE(ALLOC_UAR);
572 MLX5_COMMAND_STR_CASE(DEALLOC_UAR);
573 MLX5_COMMAND_STR_CASE(CONFIG_INT_MODERATION);
574 MLX5_COMMAND_STR_CASE(ACCESS_REG);
575 MLX5_COMMAND_STR_CASE(ATTACH_TO_MCG);
576 MLX5_COMMAND_STR_CASE(DETACH_FROM_MCG);
577 MLX5_COMMAND_STR_CASE(GET_DROPPED_PACKET_LOG);
578 MLX5_COMMAND_STR_CASE(MAD_IFC);
579 MLX5_COMMAND_STR_CASE(QUERY_MAD_DEMUX);
580 MLX5_COMMAND_STR_CASE(SET_MAD_DEMUX);
581 MLX5_COMMAND_STR_CASE(NOP);
582 MLX5_COMMAND_STR_CASE(ALLOC_XRCD);
583 MLX5_COMMAND_STR_CASE(DEALLOC_XRCD);
584 MLX5_COMMAND_STR_CASE(ALLOC_TRANSPORT_DOMAIN);
585 MLX5_COMMAND_STR_CASE(DEALLOC_TRANSPORT_DOMAIN);
586 MLX5_COMMAND_STR_CASE(QUERY_CONG_STATUS);
587 MLX5_COMMAND_STR_CASE(MODIFY_CONG_STATUS);
588 MLX5_COMMAND_STR_CASE(QUERY_CONG_PARAMS);
589 MLX5_COMMAND_STR_CASE(MODIFY_CONG_PARAMS);
590 MLX5_COMMAND_STR_CASE(QUERY_CONG_STATISTICS);
591 MLX5_COMMAND_STR_CASE(ADD_VXLAN_UDP_DPORT);
592 MLX5_COMMAND_STR_CASE(DELETE_VXLAN_UDP_DPORT);
593 MLX5_COMMAND_STR_CASE(SET_L2_TABLE_ENTRY);
594 MLX5_COMMAND_STR_CASE(QUERY_L2_TABLE_ENTRY);
595 MLX5_COMMAND_STR_CASE(DELETE_L2_TABLE_ENTRY);
596 MLX5_COMMAND_STR_CASE(SET_WOL_ROL);
597 MLX5_COMMAND_STR_CASE(QUERY_WOL_ROL);
598 MLX5_COMMAND_STR_CASE(CREATE_LAG);
599 MLX5_COMMAND_STR_CASE(MODIFY_LAG);
600 MLX5_COMMAND_STR_CASE(QUERY_LAG);
601 MLX5_COMMAND_STR_CASE(DESTROY_LAG);
602 MLX5_COMMAND_STR_CASE(CREATE_VPORT_LAG);
603 MLX5_COMMAND_STR_CASE(DESTROY_VPORT_LAG);
604 MLX5_COMMAND_STR_CASE(CREATE_TIR);
605 MLX5_COMMAND_STR_CASE(MODIFY_TIR);
606 MLX5_COMMAND_STR_CASE(DESTROY_TIR);
607 MLX5_COMMAND_STR_CASE(QUERY_TIR);
608 MLX5_COMMAND_STR_CASE(CREATE_SQ);
609 MLX5_COMMAND_STR_CASE(MODIFY_SQ);
610 MLX5_COMMAND_STR_CASE(DESTROY_SQ);
611 MLX5_COMMAND_STR_CASE(QUERY_SQ);
612 MLX5_COMMAND_STR_CASE(CREATE_RQ);
613 MLX5_COMMAND_STR_CASE(MODIFY_RQ);
614 MLX5_COMMAND_STR_CASE(DESTROY_RQ);
615 MLX5_COMMAND_STR_CASE(QUERY_RQ);
616 MLX5_COMMAND_STR_CASE(CREATE_RMP);
617 MLX5_COMMAND_STR_CASE(MODIFY_RMP);
618 MLX5_COMMAND_STR_CASE(DESTROY_RMP);
619 MLX5_COMMAND_STR_CASE(QUERY_RMP);
620 MLX5_COMMAND_STR_CASE(CREATE_TIS);
621 MLX5_COMMAND_STR_CASE(MODIFY_TIS);
622 MLX5_COMMAND_STR_CASE(DESTROY_TIS);
623 MLX5_COMMAND_STR_CASE(QUERY_TIS);
624 MLX5_COMMAND_STR_CASE(CREATE_RQT);
625 MLX5_COMMAND_STR_CASE(MODIFY_RQT);
626 MLX5_COMMAND_STR_CASE(DESTROY_RQT);
627 MLX5_COMMAND_STR_CASE(QUERY_RQT);
628 MLX5_COMMAND_STR_CASE(SET_FLOW_TABLE_ROOT);
629 MLX5_COMMAND_STR_CASE(CREATE_FLOW_TABLE);
630 MLX5_COMMAND_STR_CASE(DESTROY_FLOW_TABLE);
631 MLX5_COMMAND_STR_CASE(QUERY_FLOW_TABLE);
632 MLX5_COMMAND_STR_CASE(CREATE_FLOW_GROUP);
633 MLX5_COMMAND_STR_CASE(DESTROY_FLOW_GROUP);
634 MLX5_COMMAND_STR_CASE(QUERY_FLOW_GROUP);
635 MLX5_COMMAND_STR_CASE(SET_FLOW_TABLE_ENTRY);
636 MLX5_COMMAND_STR_CASE(QUERY_FLOW_TABLE_ENTRY);
637 MLX5_COMMAND_STR_CASE(DELETE_FLOW_TABLE_ENTRY);
638 MLX5_COMMAND_STR_CASE(ALLOC_FLOW_COUNTER);
639 MLX5_COMMAND_STR_CASE(DEALLOC_FLOW_COUNTER);
640 MLX5_COMMAND_STR_CASE(QUERY_FLOW_COUNTER);
641 MLX5_COMMAND_STR_CASE(MODIFY_FLOW_TABLE);
642 MLX5_COMMAND_STR_CASE(ALLOC_PACKET_REFORMAT_CONTEXT);
643 MLX5_COMMAND_STR_CASE(DEALLOC_PACKET_REFORMAT_CONTEXT);
644 MLX5_COMMAND_STR_CASE(ALLOC_MODIFY_HEADER_CONTEXT);
645 MLX5_COMMAND_STR_CASE(DEALLOC_MODIFY_HEADER_CONTEXT);
646 MLX5_COMMAND_STR_CASE(FPGA_CREATE_QP);
647 MLX5_COMMAND_STR_CASE(FPGA_MODIFY_QP);
648 MLX5_COMMAND_STR_CASE(FPGA_QUERY_QP);
649 MLX5_COMMAND_STR_CASE(FPGA_QUERY_QP_COUNTERS);
650 MLX5_COMMAND_STR_CASE(FPGA_DESTROY_QP);
651 MLX5_COMMAND_STR_CASE(CREATE_XRQ);
652 MLX5_COMMAND_STR_CASE(DESTROY_XRQ);
653 MLX5_COMMAND_STR_CASE(QUERY_XRQ);
654 MLX5_COMMAND_STR_CASE(ARM_XRQ);
655 MLX5_COMMAND_STR_CASE(CREATE_GENERAL_OBJECT);
656 MLX5_COMMAND_STR_CASE(DESTROY_GENERAL_OBJECT);
657 MLX5_COMMAND_STR_CASE(MODIFY_GENERAL_OBJECT);
658 MLX5_COMMAND_STR_CASE(QUERY_GENERAL_OBJECT);
659 MLX5_COMMAND_STR_CASE(QUERY_MODIFY_HEADER_CONTEXT);
660 MLX5_COMMAND_STR_CASE(ALLOC_MEMIC);
661 MLX5_COMMAND_STR_CASE(DEALLOC_MEMIC);
662 MLX5_COMMAND_STR_CASE(QUERY_ESW_FUNCTIONS);
663 MLX5_COMMAND_STR_CASE(CREATE_UCTX);
664 MLX5_COMMAND_STR_CASE(DESTROY_UCTX);
665 MLX5_COMMAND_STR_CASE(CREATE_UMEM);
666 MLX5_COMMAND_STR_CASE(DESTROY_UMEM);
667 MLX5_COMMAND_STR_CASE(RELEASE_XRQ_ERROR);
668 MLX5_COMMAND_STR_CASE(MODIFY_XRQ);
669 MLX5_COMMAND_STR_CASE(QUERY_VHCA_STATE);
670 MLX5_COMMAND_STR_CASE(MODIFY_VHCA_STATE);
671 MLX5_COMMAND_STR_CASE(ALLOC_SF);
672 MLX5_COMMAND_STR_CASE(DEALLOC_SF);
673 default: return "unknown command opcode";
674 }
675 }
676
cmd_status_str(u8 status)677 static const char *cmd_status_str(u8 status)
678 {
679 switch (status) {
680 case MLX5_CMD_STAT_OK:
681 return "OK";
682 case MLX5_CMD_STAT_INT_ERR:
683 return "internal error";
684 case MLX5_CMD_STAT_BAD_OP_ERR:
685 return "bad operation";
686 case MLX5_CMD_STAT_BAD_PARAM_ERR:
687 return "bad parameter";
688 case MLX5_CMD_STAT_BAD_SYS_STATE_ERR:
689 return "bad system state";
690 case MLX5_CMD_STAT_BAD_RES_ERR:
691 return "bad resource";
692 case MLX5_CMD_STAT_RES_BUSY:
693 return "resource busy";
694 case MLX5_CMD_STAT_LIM_ERR:
695 return "limits exceeded";
696 case MLX5_CMD_STAT_BAD_RES_STATE_ERR:
697 return "bad resource state";
698 case MLX5_CMD_STAT_IX_ERR:
699 return "bad index";
700 case MLX5_CMD_STAT_NO_RES_ERR:
701 return "no resources";
702 case MLX5_CMD_STAT_BAD_INP_LEN_ERR:
703 return "bad input length";
704 case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR:
705 return "bad output length";
706 case MLX5_CMD_STAT_BAD_QP_STATE_ERR:
707 return "bad QP state";
708 case MLX5_CMD_STAT_BAD_PKT_ERR:
709 return "bad packet (discarded)";
710 case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR:
711 return "bad size too many outstanding CQEs";
712 default:
713 return "unknown status";
714 }
715 }
716
cmd_status_to_err(u8 status)717 static int cmd_status_to_err(u8 status)
718 {
719 switch (status) {
720 case MLX5_CMD_STAT_OK: return 0;
721 case MLX5_CMD_STAT_INT_ERR: return -EIO;
722 case MLX5_CMD_STAT_BAD_OP_ERR: return -EINVAL;
723 case MLX5_CMD_STAT_BAD_PARAM_ERR: return -EINVAL;
724 case MLX5_CMD_STAT_BAD_SYS_STATE_ERR: return -EIO;
725 case MLX5_CMD_STAT_BAD_RES_ERR: return -EINVAL;
726 case MLX5_CMD_STAT_RES_BUSY: return -EBUSY;
727 case MLX5_CMD_STAT_LIM_ERR: return -ENOMEM;
728 case MLX5_CMD_STAT_BAD_RES_STATE_ERR: return -EINVAL;
729 case MLX5_CMD_STAT_IX_ERR: return -EINVAL;
730 case MLX5_CMD_STAT_NO_RES_ERR: return -EAGAIN;
731 case MLX5_CMD_STAT_BAD_INP_LEN_ERR: return -EIO;
732 case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR: return -EIO;
733 case MLX5_CMD_STAT_BAD_QP_STATE_ERR: return -EINVAL;
734 case MLX5_CMD_STAT_BAD_PKT_ERR: return -EINVAL;
735 case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR: return -EINVAL;
736 default: return -EIO;
737 }
738 }
739
740 struct mlx5_ifc_mbox_out_bits {
741 u8 status[0x8];
742 u8 reserved_at_8[0x18];
743
744 u8 syndrome[0x20];
745
746 u8 reserved_at_40[0x40];
747 };
748
749 struct mlx5_ifc_mbox_in_bits {
750 u8 opcode[0x10];
751 u8 uid[0x10];
752
753 u8 reserved_at_20[0x10];
754 u8 op_mod[0x10];
755
756 u8 reserved_at_40[0x40];
757 };
758
mlx5_cmd_mbox_status(void * out,u8 * status,u32 * syndrome)759 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome)
760 {
761 *status = MLX5_GET(mbox_out, out, status);
762 *syndrome = MLX5_GET(mbox_out, out, syndrome);
763 }
764
mlx5_cmd_check(struct mlx5_core_dev * dev,void * in,void * out)765 static int mlx5_cmd_check(struct mlx5_core_dev *dev, void *in, void *out)
766 {
767 u32 syndrome;
768 u8 status;
769 u16 opcode;
770 u16 op_mod;
771 u16 uid;
772
773 mlx5_cmd_mbox_status(out, &status, &syndrome);
774 if (!status)
775 return 0;
776
777 opcode = MLX5_GET(mbox_in, in, opcode);
778 op_mod = MLX5_GET(mbox_in, in, op_mod);
779 uid = MLX5_GET(mbox_in, in, uid);
780
781 if (!uid && opcode != MLX5_CMD_OP_DESTROY_MKEY)
782 mlx5_core_err_rl(dev,
783 "%s(0x%x) op_mod(0x%x) failed, status %s(0x%x), syndrome (0x%x)\n",
784 mlx5_command_str(opcode), opcode, op_mod,
785 cmd_status_str(status), status, syndrome);
786 else
787 mlx5_core_dbg(dev,
788 "%s(0x%x) op_mod(0x%x) failed, status %s(0x%x), syndrome (0x%x)\n",
789 mlx5_command_str(opcode),
790 opcode, op_mod,
791 cmd_status_str(status),
792 status,
793 syndrome);
794
795 return cmd_status_to_err(status);
796 }
797
dump_command(struct mlx5_core_dev * dev,struct mlx5_cmd_work_ent * ent,int input)798 static void dump_command(struct mlx5_core_dev *dev,
799 struct mlx5_cmd_work_ent *ent, int input)
800 {
801 struct mlx5_cmd_msg *msg = input ? ent->in : ent->out;
802 u16 op = MLX5_GET(mbox_in, ent->lay->in, opcode);
803 struct mlx5_cmd_mailbox *next = msg->next;
804 int n = mlx5_calc_cmd_blocks(msg);
805 int data_only;
806 u32 offset = 0;
807 int dump_len;
808 int i;
809
810 mlx5_core_dbg(dev, "cmd[%d]: start dump\n", ent->idx);
811 data_only = !!(mlx5_core_debug_mask & (1 << MLX5_CMD_DATA));
812
813 if (data_only)
814 mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_DATA,
815 "cmd[%d]: dump command data %s(0x%x) %s\n",
816 ent->idx, mlx5_command_str(op), op,
817 input ? "INPUT" : "OUTPUT");
818 else
819 mlx5_core_dbg(dev, "cmd[%d]: dump command %s(0x%x) %s\n",
820 ent->idx, mlx5_command_str(op), op,
821 input ? "INPUT" : "OUTPUT");
822
823 if (data_only) {
824 if (input) {
825 dump_buf(ent->lay->in, sizeof(ent->lay->in), 1, offset, ent->idx);
826 offset += sizeof(ent->lay->in);
827 } else {
828 dump_buf(ent->lay->out, sizeof(ent->lay->out), 1, offset, ent->idx);
829 offset += sizeof(ent->lay->out);
830 }
831 } else {
832 dump_buf(ent->lay, sizeof(*ent->lay), 0, offset, ent->idx);
833 offset += sizeof(*ent->lay);
834 }
835
836 for (i = 0; i < n && next; i++) {
837 if (data_only) {
838 dump_len = min_t(int, MLX5_CMD_DATA_BLOCK_SIZE, msg->len - offset);
839 dump_buf(next->buf, dump_len, 1, offset, ent->idx);
840 offset += MLX5_CMD_DATA_BLOCK_SIZE;
841 } else {
842 mlx5_core_dbg(dev, "cmd[%d]: command block:\n", ent->idx);
843 dump_buf(next->buf, sizeof(struct mlx5_cmd_prot_block), 0, offset,
844 ent->idx);
845 offset += sizeof(struct mlx5_cmd_prot_block);
846 }
847 next = next->next;
848 }
849
850 if (data_only)
851 pr_debug("\n");
852
853 mlx5_core_dbg(dev, "cmd[%d]: end dump\n", ent->idx);
854 }
855
msg_to_opcode(struct mlx5_cmd_msg * in)856 static u16 msg_to_opcode(struct mlx5_cmd_msg *in)
857 {
858 return MLX5_GET(mbox_in, in->first.data, opcode);
859 }
860
861 static void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec, bool forced);
862
cb_timeout_handler(struct work_struct * work)863 static void cb_timeout_handler(struct work_struct *work)
864 {
865 struct delayed_work *dwork = container_of(work, struct delayed_work,
866 work);
867 struct mlx5_cmd_work_ent *ent = container_of(dwork,
868 struct mlx5_cmd_work_ent,
869 cb_timeout_work);
870 struct mlx5_core_dev *dev = container_of(ent->cmd, struct mlx5_core_dev,
871 cmd);
872
873 mlx5_cmd_eq_recover(dev);
874
875 /* Maybe got handled by eq recover ? */
876 if (!test_bit(MLX5_CMD_ENT_STATE_PENDING_COMP, &ent->state)) {
877 mlx5_core_warn(dev, "cmd[%d]: %s(0x%x) Async, recovered after timeout\n", ent->idx,
878 mlx5_command_str(msg_to_opcode(ent->in)), msg_to_opcode(ent->in));
879 goto out; /* phew, already handled */
880 }
881
882 ent->ret = -ETIMEDOUT;
883 mlx5_core_warn(dev, "cmd[%d]: %s(0x%x) Async, timeout. Will cause a leak of a command resource\n",
884 ent->idx, mlx5_command_str(msg_to_opcode(ent->in)), msg_to_opcode(ent->in));
885 mlx5_cmd_comp_handler(dev, 1ULL << ent->idx, true);
886
887 out:
888 cmd_ent_put(ent); /* for the cmd_ent_get() took on schedule delayed work */
889 }
890
891 static void free_msg(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *msg);
892 static void mlx5_free_cmd_msg(struct mlx5_core_dev *dev,
893 struct mlx5_cmd_msg *msg);
894
opcode_allowed(struct mlx5_cmd * cmd,u16 opcode)895 static bool opcode_allowed(struct mlx5_cmd *cmd, u16 opcode)
896 {
897 if (cmd->allowed_opcode == CMD_ALLOWED_OPCODE_ALL)
898 return true;
899
900 return cmd->allowed_opcode == opcode;
901 }
902
cmd_alloc_index_retry(struct mlx5_cmd * cmd)903 static int cmd_alloc_index_retry(struct mlx5_cmd *cmd)
904 {
905 unsigned long alloc_end = jiffies + msecs_to_jiffies(1000);
906 int idx;
907
908 retry:
909 idx = cmd_alloc_index(cmd);
910 if (idx < 0 && time_before(jiffies, alloc_end)) {
911 /* Index allocation can fail on heavy load of commands. This is a temporary
912 * situation as the current command already holds the semaphore, meaning that
913 * another command completion is being handled and it is expected to release
914 * the entry index soon.
915 */
916 cpu_relax();
917 goto retry;
918 }
919 return idx;
920 }
921
mlx5_cmd_is_down(struct mlx5_core_dev * dev)922 bool mlx5_cmd_is_down(struct mlx5_core_dev *dev)
923 {
924 return pci_channel_offline(dev->pdev) ||
925 dev->cmd.state != MLX5_CMDIF_STATE_UP ||
926 dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR;
927 }
928
cmd_work_handler(struct work_struct * work)929 static void cmd_work_handler(struct work_struct *work)
930 {
931 struct mlx5_cmd_work_ent *ent = container_of(work, struct mlx5_cmd_work_ent, work);
932 struct mlx5_cmd *cmd = ent->cmd;
933 bool poll_cmd = ent->polling;
934 struct mlx5_cmd_layout *lay;
935 struct mlx5_core_dev *dev;
936 unsigned long cb_timeout;
937 struct semaphore *sem;
938 unsigned long flags;
939 int alloc_ret;
940 int cmd_mode;
941
942 dev = container_of(cmd, struct mlx5_core_dev, cmd);
943 cb_timeout = msecs_to_jiffies(mlx5_tout_ms(dev, CMD));
944
945 complete(&ent->handling);
946 sem = ent->page_queue ? &cmd->pages_sem : &cmd->sem;
947 down(sem);
948 if (!ent->page_queue) {
949 alloc_ret = cmd_alloc_index_retry(cmd);
950 if (alloc_ret < 0) {
951 mlx5_core_err_rl(dev, "failed to allocate command entry\n");
952 if (ent->callback) {
953 ent->callback(-EAGAIN, ent->context);
954 mlx5_free_cmd_msg(dev, ent->out);
955 free_msg(dev, ent->in);
956 cmd_ent_put(ent);
957 } else {
958 ent->ret = -EAGAIN;
959 complete(&ent->done);
960 }
961 up(sem);
962 return;
963 }
964 ent->idx = alloc_ret;
965 } else {
966 ent->idx = cmd->max_reg_cmds;
967 spin_lock_irqsave(&cmd->alloc_lock, flags);
968 clear_bit(ent->idx, &cmd->bitmask);
969 spin_unlock_irqrestore(&cmd->alloc_lock, flags);
970 }
971
972 cmd->ent_arr[ent->idx] = ent;
973 lay = get_inst(cmd, ent->idx);
974 ent->lay = lay;
975 memset(lay, 0, sizeof(*lay));
976 memcpy(lay->in, ent->in->first.data, sizeof(lay->in));
977 ent->op = be32_to_cpu(lay->in[0]) >> 16;
978 if (ent->in->next)
979 lay->in_ptr = cpu_to_be64(ent->in->next->dma);
980 lay->inlen = cpu_to_be32(ent->in->len);
981 if (ent->out->next)
982 lay->out_ptr = cpu_to_be64(ent->out->next->dma);
983 lay->outlen = cpu_to_be32(ent->out->len);
984 lay->type = MLX5_PCI_CMD_XPORT;
985 lay->token = ent->token;
986 lay->status_own = CMD_OWNER_HW;
987 set_signature(ent, !cmd->checksum_disabled);
988 dump_command(dev, ent, 1);
989 ent->ts1 = ktime_get_ns();
990 cmd_mode = cmd->mode;
991
992 if (ent->callback && schedule_delayed_work(&ent->cb_timeout_work, cb_timeout))
993 cmd_ent_get(ent);
994 set_bit(MLX5_CMD_ENT_STATE_PENDING_COMP, &ent->state);
995
996 /* Skip sending command to fw if internal error */
997 if (mlx5_cmd_is_down(dev) || !opcode_allowed(&dev->cmd, ent->op)) {
998 u8 status = 0;
999 u32 drv_synd;
1000
1001 ent->ret = mlx5_internal_err_ret_value(dev, msg_to_opcode(ent->in), &drv_synd, &status);
1002 MLX5_SET(mbox_out, ent->out, status, status);
1003 MLX5_SET(mbox_out, ent->out, syndrome, drv_synd);
1004
1005 mlx5_cmd_comp_handler(dev, 1ULL << ent->idx, true);
1006 return;
1007 }
1008
1009 cmd_ent_get(ent); /* for the _real_ FW event on completion */
1010 /* ring doorbell after the descriptor is valid */
1011 mlx5_core_dbg(dev, "writing 0x%x to command doorbell\n", 1 << ent->idx);
1012 wmb();
1013 iowrite32be(1 << ent->idx, &dev->iseg->cmd_dbell);
1014 /* if not in polling don't use ent after this point */
1015 if (cmd_mode == CMD_MODE_POLLING || poll_cmd) {
1016 poll_timeout(ent);
1017 /* make sure we read the descriptor after ownership is SW */
1018 rmb();
1019 mlx5_cmd_comp_handler(dev, 1ULL << ent->idx, (ent->ret == -ETIMEDOUT));
1020 }
1021 }
1022
deliv_status_to_str(u8 status)1023 static const char *deliv_status_to_str(u8 status)
1024 {
1025 switch (status) {
1026 case MLX5_CMD_DELIVERY_STAT_OK:
1027 return "no errors";
1028 case MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR:
1029 return "signature error";
1030 case MLX5_CMD_DELIVERY_STAT_TOK_ERR:
1031 return "token error";
1032 case MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR:
1033 return "bad block number";
1034 case MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR:
1035 return "output pointer not aligned to block size";
1036 case MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR:
1037 return "input pointer not aligned to block size";
1038 case MLX5_CMD_DELIVERY_STAT_FW_ERR:
1039 return "firmware internal error";
1040 case MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR:
1041 return "command input length error";
1042 case MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR:
1043 return "command output length error";
1044 case MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR:
1045 return "reserved fields not cleared";
1046 case MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR:
1047 return "bad command descriptor type";
1048 default:
1049 return "unknown status code";
1050 }
1051 }
1052
1053 enum {
1054 MLX5_CMD_TIMEOUT_RECOVER_MSEC = 5 * 1000,
1055 };
1056
wait_func_handle_exec_timeout(struct mlx5_core_dev * dev,struct mlx5_cmd_work_ent * ent)1057 static void wait_func_handle_exec_timeout(struct mlx5_core_dev *dev,
1058 struct mlx5_cmd_work_ent *ent)
1059 {
1060 unsigned long timeout = msecs_to_jiffies(MLX5_CMD_TIMEOUT_RECOVER_MSEC);
1061
1062 mlx5_cmd_eq_recover(dev);
1063
1064 /* Re-wait on the ent->done after executing the recovery flow. If the
1065 * recovery flow (or any other recovery flow running simultaneously)
1066 * has recovered an EQE, it should cause the entry to be completed by
1067 * the command interface.
1068 */
1069 if (wait_for_completion_timeout(&ent->done, timeout)) {
1070 mlx5_core_warn(dev, "cmd[%d]: %s(0x%x) recovered after timeout\n", ent->idx,
1071 mlx5_command_str(msg_to_opcode(ent->in)), msg_to_opcode(ent->in));
1072 return;
1073 }
1074
1075 mlx5_core_warn(dev, "cmd[%d]: %s(0x%x) No done completion\n", ent->idx,
1076 mlx5_command_str(msg_to_opcode(ent->in)), msg_to_opcode(ent->in));
1077
1078 ent->ret = -ETIMEDOUT;
1079 mlx5_cmd_comp_handler(dev, 1ULL << ent->idx, true);
1080 }
1081
wait_func(struct mlx5_core_dev * dev,struct mlx5_cmd_work_ent * ent)1082 static int wait_func(struct mlx5_core_dev *dev, struct mlx5_cmd_work_ent *ent)
1083 {
1084 unsigned long timeout = msecs_to_jiffies(mlx5_tout_ms(dev, CMD));
1085 struct mlx5_cmd *cmd = &dev->cmd;
1086 int err;
1087
1088 if (!wait_for_completion_timeout(&ent->handling, timeout) &&
1089 cancel_work_sync(&ent->work)) {
1090 ent->ret = -ECANCELED;
1091 goto out_err;
1092 }
1093 if (cmd->mode == CMD_MODE_POLLING || ent->polling)
1094 wait_for_completion(&ent->done);
1095 else if (!wait_for_completion_timeout(&ent->done, timeout))
1096 wait_func_handle_exec_timeout(dev, ent);
1097
1098 out_err:
1099 err = ent->ret;
1100
1101 if (err == -ETIMEDOUT) {
1102 mlx5_core_warn(dev, "%s(0x%x) timeout. Will cause a leak of a command resource\n",
1103 mlx5_command_str(msg_to_opcode(ent->in)),
1104 msg_to_opcode(ent->in));
1105 } else if (err == -ECANCELED) {
1106 mlx5_core_warn(dev, "%s(0x%x) canceled on out of queue timeout.\n",
1107 mlx5_command_str(msg_to_opcode(ent->in)),
1108 msg_to_opcode(ent->in));
1109 }
1110 mlx5_core_dbg(dev, "err %d, delivery status %s(%d)\n",
1111 err, deliv_status_to_str(ent->status), ent->status);
1112
1113 return err;
1114 }
1115
1116 /* Notes:
1117 * 1. Callback functions may not sleep
1118 * 2. page queue commands do not support asynchrous completion
1119 */
mlx5_cmd_invoke(struct mlx5_core_dev * dev,struct mlx5_cmd_msg * in,struct mlx5_cmd_msg * out,void * uout,int uout_size,mlx5_cmd_cbk_t callback,void * context,int page_queue,u8 * status,u8 token,bool force_polling)1120 static int mlx5_cmd_invoke(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *in,
1121 struct mlx5_cmd_msg *out, void *uout, int uout_size,
1122 mlx5_cmd_cbk_t callback,
1123 void *context, int page_queue, u8 *status,
1124 u8 token, bool force_polling)
1125 {
1126 struct mlx5_cmd *cmd = &dev->cmd;
1127 struct mlx5_cmd_work_ent *ent;
1128 struct mlx5_cmd_stats *stats;
1129 int err = 0;
1130 s64 ds;
1131 u16 op;
1132
1133 if (callback && page_queue)
1134 return -EINVAL;
1135
1136 ent = cmd_alloc_ent(cmd, in, out, uout, uout_size,
1137 callback, context, page_queue);
1138 if (IS_ERR(ent))
1139 return PTR_ERR(ent);
1140
1141 /* put for this ent is when consumed, depending on the use case
1142 * 1) (!callback) blocking flow: by caller after wait_func completes
1143 * 2) (callback) flow: by mlx5_cmd_comp_handler() when ent is handled
1144 */
1145
1146 ent->token = token;
1147 ent->polling = force_polling;
1148
1149 init_completion(&ent->handling);
1150 if (!callback)
1151 init_completion(&ent->done);
1152
1153 INIT_DELAYED_WORK(&ent->cb_timeout_work, cb_timeout_handler);
1154 INIT_WORK(&ent->work, cmd_work_handler);
1155 if (page_queue) {
1156 cmd_work_handler(&ent->work);
1157 } else if (!queue_work(cmd->wq, &ent->work)) {
1158 mlx5_core_warn(dev, "failed to queue work\n");
1159 err = -ENOMEM;
1160 goto out_free;
1161 }
1162
1163 if (callback)
1164 goto out; /* mlx5_cmd_comp_handler() will put(ent) */
1165
1166 err = wait_func(dev, ent);
1167 if (err == -ETIMEDOUT || err == -ECANCELED)
1168 goto out_free;
1169
1170 ds = ent->ts2 - ent->ts1;
1171 op = MLX5_GET(mbox_in, in->first.data, opcode);
1172 if (op < MLX5_CMD_OP_MAX) {
1173 stats = &cmd->stats[op];
1174 spin_lock_irq(&stats->lock);
1175 stats->sum += ds;
1176 ++stats->n;
1177 spin_unlock_irq(&stats->lock);
1178 }
1179 mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_TIME,
1180 "fw exec time for %s is %lld nsec\n",
1181 mlx5_command_str(op), ds);
1182 *status = ent->status;
1183
1184 out_free:
1185 cmd_ent_put(ent);
1186 out:
1187 return err;
1188 }
1189
dbg_write(struct file * filp,const char __user * buf,size_t count,loff_t * pos)1190 static ssize_t dbg_write(struct file *filp, const char __user *buf,
1191 size_t count, loff_t *pos)
1192 {
1193 struct mlx5_core_dev *dev = filp->private_data;
1194 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1195 char lbuf[3];
1196 int err;
1197
1198 if (!dbg->in_msg || !dbg->out_msg)
1199 return -ENOMEM;
1200
1201 if (count < sizeof(lbuf) - 1)
1202 return -EINVAL;
1203
1204 if (copy_from_user(lbuf, buf, sizeof(lbuf) - 1))
1205 return -EFAULT;
1206
1207 lbuf[sizeof(lbuf) - 1] = 0;
1208
1209 if (strcmp(lbuf, "go"))
1210 return -EINVAL;
1211
1212 err = mlx5_cmd_exec(dev, dbg->in_msg, dbg->inlen, dbg->out_msg, dbg->outlen);
1213
1214 return err ? err : count;
1215 }
1216
1217 static const struct file_operations fops = {
1218 .owner = THIS_MODULE,
1219 .open = simple_open,
1220 .write = dbg_write,
1221 };
1222
mlx5_copy_to_msg(struct mlx5_cmd_msg * to,void * from,int size,u8 token)1223 static int mlx5_copy_to_msg(struct mlx5_cmd_msg *to, void *from, int size,
1224 u8 token)
1225 {
1226 struct mlx5_cmd_prot_block *block;
1227 struct mlx5_cmd_mailbox *next;
1228 int copy;
1229
1230 if (!to || !from)
1231 return -ENOMEM;
1232
1233 copy = min_t(int, size, sizeof(to->first.data));
1234 memcpy(to->first.data, from, copy);
1235 size -= copy;
1236 from += copy;
1237
1238 next = to->next;
1239 while (size) {
1240 if (!next) {
1241 /* this is a BUG */
1242 return -ENOMEM;
1243 }
1244
1245 copy = min_t(int, size, MLX5_CMD_DATA_BLOCK_SIZE);
1246 block = next->buf;
1247 memcpy(block->data, from, copy);
1248 from += copy;
1249 size -= copy;
1250 block->token = token;
1251 next = next->next;
1252 }
1253
1254 return 0;
1255 }
1256
mlx5_copy_from_msg(void * to,struct mlx5_cmd_msg * from,int size)1257 static int mlx5_copy_from_msg(void *to, struct mlx5_cmd_msg *from, int size)
1258 {
1259 struct mlx5_cmd_prot_block *block;
1260 struct mlx5_cmd_mailbox *next;
1261 int copy;
1262
1263 if (!to || !from)
1264 return -ENOMEM;
1265
1266 copy = min_t(int, size, sizeof(from->first.data));
1267 memcpy(to, from->first.data, copy);
1268 size -= copy;
1269 to += copy;
1270
1271 next = from->next;
1272 while (size) {
1273 if (!next) {
1274 /* this is a BUG */
1275 return -ENOMEM;
1276 }
1277
1278 copy = min_t(int, size, MLX5_CMD_DATA_BLOCK_SIZE);
1279 block = next->buf;
1280
1281 memcpy(to, block->data, copy);
1282 to += copy;
1283 size -= copy;
1284 next = next->next;
1285 }
1286
1287 return 0;
1288 }
1289
alloc_cmd_box(struct mlx5_core_dev * dev,gfp_t flags)1290 static struct mlx5_cmd_mailbox *alloc_cmd_box(struct mlx5_core_dev *dev,
1291 gfp_t flags)
1292 {
1293 struct mlx5_cmd_mailbox *mailbox;
1294
1295 mailbox = kmalloc(sizeof(*mailbox), flags);
1296 if (!mailbox)
1297 return ERR_PTR(-ENOMEM);
1298
1299 mailbox->buf = dma_pool_zalloc(dev->cmd.pool, flags,
1300 &mailbox->dma);
1301 if (!mailbox->buf) {
1302 mlx5_core_dbg(dev, "failed allocation\n");
1303 kfree(mailbox);
1304 return ERR_PTR(-ENOMEM);
1305 }
1306 mailbox->next = NULL;
1307
1308 return mailbox;
1309 }
1310
free_cmd_box(struct mlx5_core_dev * dev,struct mlx5_cmd_mailbox * mailbox)1311 static void free_cmd_box(struct mlx5_core_dev *dev,
1312 struct mlx5_cmd_mailbox *mailbox)
1313 {
1314 dma_pool_free(dev->cmd.pool, mailbox->buf, mailbox->dma);
1315 kfree(mailbox);
1316 }
1317
mlx5_alloc_cmd_msg(struct mlx5_core_dev * dev,gfp_t flags,int size,u8 token)1318 static struct mlx5_cmd_msg *mlx5_alloc_cmd_msg(struct mlx5_core_dev *dev,
1319 gfp_t flags, int size,
1320 u8 token)
1321 {
1322 struct mlx5_cmd_mailbox *tmp, *head = NULL;
1323 struct mlx5_cmd_prot_block *block;
1324 struct mlx5_cmd_msg *msg;
1325 int err;
1326 int n;
1327 int i;
1328
1329 msg = kzalloc(sizeof(*msg), flags);
1330 if (!msg)
1331 return ERR_PTR(-ENOMEM);
1332
1333 msg->len = size;
1334 n = mlx5_calc_cmd_blocks(msg);
1335
1336 for (i = 0; i < n; i++) {
1337 tmp = alloc_cmd_box(dev, flags);
1338 if (IS_ERR(tmp)) {
1339 mlx5_core_warn(dev, "failed allocating block\n");
1340 err = PTR_ERR(tmp);
1341 goto err_alloc;
1342 }
1343
1344 block = tmp->buf;
1345 tmp->next = head;
1346 block->next = cpu_to_be64(tmp->next ? tmp->next->dma : 0);
1347 block->block_num = cpu_to_be32(n - i - 1);
1348 block->token = token;
1349 head = tmp;
1350 }
1351 msg->next = head;
1352 return msg;
1353
1354 err_alloc:
1355 while (head) {
1356 tmp = head->next;
1357 free_cmd_box(dev, head);
1358 head = tmp;
1359 }
1360 kfree(msg);
1361
1362 return ERR_PTR(err);
1363 }
1364
mlx5_free_cmd_msg(struct mlx5_core_dev * dev,struct mlx5_cmd_msg * msg)1365 static void mlx5_free_cmd_msg(struct mlx5_core_dev *dev,
1366 struct mlx5_cmd_msg *msg)
1367 {
1368 struct mlx5_cmd_mailbox *head = msg->next;
1369 struct mlx5_cmd_mailbox *next;
1370
1371 while (head) {
1372 next = head->next;
1373 free_cmd_box(dev, head);
1374 head = next;
1375 }
1376 kfree(msg);
1377 }
1378
data_write(struct file * filp,const char __user * buf,size_t count,loff_t * pos)1379 static ssize_t data_write(struct file *filp, const char __user *buf,
1380 size_t count, loff_t *pos)
1381 {
1382 struct mlx5_core_dev *dev = filp->private_data;
1383 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1384 void *ptr;
1385
1386 if (*pos != 0)
1387 return -EINVAL;
1388
1389 kfree(dbg->in_msg);
1390 dbg->in_msg = NULL;
1391 dbg->inlen = 0;
1392 ptr = memdup_user(buf, count);
1393 if (IS_ERR(ptr))
1394 return PTR_ERR(ptr);
1395 dbg->in_msg = ptr;
1396 dbg->inlen = count;
1397
1398 *pos = count;
1399
1400 return count;
1401 }
1402
data_read(struct file * filp,char __user * buf,size_t count,loff_t * pos)1403 static ssize_t data_read(struct file *filp, char __user *buf, size_t count,
1404 loff_t *pos)
1405 {
1406 struct mlx5_core_dev *dev = filp->private_data;
1407 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1408
1409 if (!dbg->out_msg)
1410 return -ENOMEM;
1411
1412 return simple_read_from_buffer(buf, count, pos, dbg->out_msg,
1413 dbg->outlen);
1414 }
1415
1416 static const struct file_operations dfops = {
1417 .owner = THIS_MODULE,
1418 .open = simple_open,
1419 .write = data_write,
1420 .read = data_read,
1421 };
1422
outlen_read(struct file * filp,char __user * buf,size_t count,loff_t * pos)1423 static ssize_t outlen_read(struct file *filp, char __user *buf, size_t count,
1424 loff_t *pos)
1425 {
1426 struct mlx5_core_dev *dev = filp->private_data;
1427 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1428 char outlen[8];
1429 int err;
1430
1431 err = snprintf(outlen, sizeof(outlen), "%d", dbg->outlen);
1432 if (err < 0)
1433 return err;
1434
1435 return simple_read_from_buffer(buf, count, pos, outlen, err);
1436 }
1437
outlen_write(struct file * filp,const char __user * buf,size_t count,loff_t * pos)1438 static ssize_t outlen_write(struct file *filp, const char __user *buf,
1439 size_t count, loff_t *pos)
1440 {
1441 struct mlx5_core_dev *dev = filp->private_data;
1442 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1443 char outlen_str[8] = {0};
1444 int outlen;
1445 void *ptr;
1446 int err;
1447
1448 if (*pos != 0 || count > 6)
1449 return -EINVAL;
1450
1451 kfree(dbg->out_msg);
1452 dbg->out_msg = NULL;
1453 dbg->outlen = 0;
1454
1455 if (copy_from_user(outlen_str, buf, count))
1456 return -EFAULT;
1457
1458 err = sscanf(outlen_str, "%d", &outlen);
1459 if (err < 0)
1460 return err;
1461
1462 ptr = kzalloc(outlen, GFP_KERNEL);
1463 if (!ptr)
1464 return -ENOMEM;
1465
1466 dbg->out_msg = ptr;
1467 dbg->outlen = outlen;
1468
1469 *pos = count;
1470
1471 return count;
1472 }
1473
1474 static const struct file_operations olfops = {
1475 .owner = THIS_MODULE,
1476 .open = simple_open,
1477 .write = outlen_write,
1478 .read = outlen_read,
1479 };
1480
set_wqname(struct mlx5_core_dev * dev)1481 static void set_wqname(struct mlx5_core_dev *dev)
1482 {
1483 struct mlx5_cmd *cmd = &dev->cmd;
1484
1485 snprintf(cmd->wq_name, sizeof(cmd->wq_name), "mlx5_cmd_%s",
1486 dev_name(dev->device));
1487 }
1488
clean_debug_files(struct mlx5_core_dev * dev)1489 static void clean_debug_files(struct mlx5_core_dev *dev)
1490 {
1491 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1492
1493 if (!mlx5_debugfs_root)
1494 return;
1495
1496 mlx5_cmdif_debugfs_cleanup(dev);
1497 debugfs_remove_recursive(dbg->dbg_root);
1498 }
1499
create_debugfs_files(struct mlx5_core_dev * dev)1500 static void create_debugfs_files(struct mlx5_core_dev *dev)
1501 {
1502 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1503
1504 dbg->dbg_root = debugfs_create_dir("cmd", dev->priv.dbg_root);
1505
1506 debugfs_create_file("in", 0400, dbg->dbg_root, dev, &dfops);
1507 debugfs_create_file("out", 0200, dbg->dbg_root, dev, &dfops);
1508 debugfs_create_file("out_len", 0600, dbg->dbg_root, dev, &olfops);
1509 debugfs_create_u8("status", 0600, dbg->dbg_root, &dbg->status);
1510 debugfs_create_file("run", 0200, dbg->dbg_root, dev, &fops);
1511
1512 mlx5_cmdif_debugfs_init(dev);
1513 }
1514
mlx5_cmd_allowed_opcode(struct mlx5_core_dev * dev,u16 opcode)1515 void mlx5_cmd_allowed_opcode(struct mlx5_core_dev *dev, u16 opcode)
1516 {
1517 struct mlx5_cmd *cmd = &dev->cmd;
1518 int i;
1519
1520 for (i = 0; i < cmd->max_reg_cmds; i++)
1521 down(&cmd->sem);
1522 down(&cmd->pages_sem);
1523
1524 cmd->allowed_opcode = opcode;
1525
1526 up(&cmd->pages_sem);
1527 for (i = 0; i < cmd->max_reg_cmds; i++)
1528 up(&cmd->sem);
1529 }
1530
mlx5_cmd_change_mod(struct mlx5_core_dev * dev,int mode)1531 static void mlx5_cmd_change_mod(struct mlx5_core_dev *dev, int mode)
1532 {
1533 struct mlx5_cmd *cmd = &dev->cmd;
1534 int i;
1535
1536 for (i = 0; i < cmd->max_reg_cmds; i++)
1537 down(&cmd->sem);
1538 down(&cmd->pages_sem);
1539
1540 cmd->mode = mode;
1541
1542 up(&cmd->pages_sem);
1543 for (i = 0; i < cmd->max_reg_cmds; i++)
1544 up(&cmd->sem);
1545 }
1546
cmd_comp_notifier(struct notifier_block * nb,unsigned long type,void * data)1547 static int cmd_comp_notifier(struct notifier_block *nb,
1548 unsigned long type, void *data)
1549 {
1550 struct mlx5_core_dev *dev;
1551 struct mlx5_cmd *cmd;
1552 struct mlx5_eqe *eqe;
1553
1554 cmd = mlx5_nb_cof(nb, struct mlx5_cmd, nb);
1555 dev = container_of(cmd, struct mlx5_core_dev, cmd);
1556 eqe = data;
1557
1558 mlx5_cmd_comp_handler(dev, be32_to_cpu(eqe->data.cmd.vector), false);
1559
1560 return NOTIFY_OK;
1561 }
mlx5_cmd_use_events(struct mlx5_core_dev * dev)1562 void mlx5_cmd_use_events(struct mlx5_core_dev *dev)
1563 {
1564 MLX5_NB_INIT(&dev->cmd.nb, cmd_comp_notifier, CMD);
1565 mlx5_eq_notifier_register(dev, &dev->cmd.nb);
1566 mlx5_cmd_change_mod(dev, CMD_MODE_EVENTS);
1567 }
1568
mlx5_cmd_use_polling(struct mlx5_core_dev * dev)1569 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev)
1570 {
1571 mlx5_cmd_change_mod(dev, CMD_MODE_POLLING);
1572 mlx5_eq_notifier_unregister(dev, &dev->cmd.nb);
1573 }
1574
free_msg(struct mlx5_core_dev * dev,struct mlx5_cmd_msg * msg)1575 static void free_msg(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *msg)
1576 {
1577 unsigned long flags;
1578
1579 if (msg->parent) {
1580 spin_lock_irqsave(&msg->parent->lock, flags);
1581 list_add_tail(&msg->list, &msg->parent->head);
1582 spin_unlock_irqrestore(&msg->parent->lock, flags);
1583 } else {
1584 mlx5_free_cmd_msg(dev, msg);
1585 }
1586 }
1587
mlx5_cmd_comp_handler(struct mlx5_core_dev * dev,u64 vec,bool forced)1588 static void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec, bool forced)
1589 {
1590 struct mlx5_cmd *cmd = &dev->cmd;
1591 struct mlx5_cmd_work_ent *ent;
1592 mlx5_cmd_cbk_t callback;
1593 void *context;
1594 int err;
1595 int i;
1596 s64 ds;
1597 struct mlx5_cmd_stats *stats;
1598 unsigned long flags;
1599 unsigned long vector;
1600
1601 /* there can be at most 32 command queues */
1602 vector = vec & 0xffffffff;
1603 for (i = 0; i < (1 << cmd->log_sz); i++) {
1604 if (test_bit(i, &vector)) {
1605 struct semaphore *sem;
1606
1607 ent = cmd->ent_arr[i];
1608
1609 /* if we already completed the command, ignore it */
1610 if (!test_and_clear_bit(MLX5_CMD_ENT_STATE_PENDING_COMP,
1611 &ent->state)) {
1612 /* only real completion can free the cmd slot */
1613 if (!forced) {
1614 mlx5_core_err(dev, "Command completion arrived after timeout (entry idx = %d).\n",
1615 ent->idx);
1616 cmd_ent_put(ent);
1617 }
1618 continue;
1619 }
1620
1621 if (ent->callback && cancel_delayed_work(&ent->cb_timeout_work))
1622 cmd_ent_put(ent); /* timeout work was canceled */
1623
1624 if (!forced || /* Real FW completion */
1625 pci_channel_offline(dev->pdev) || /* FW is inaccessible */
1626 dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR)
1627 cmd_ent_put(ent);
1628
1629 if (ent->page_queue)
1630 sem = &cmd->pages_sem;
1631 else
1632 sem = &cmd->sem;
1633 ent->ts2 = ktime_get_ns();
1634 memcpy(ent->out->first.data, ent->lay->out, sizeof(ent->lay->out));
1635 dump_command(dev, ent, 0);
1636 if (!ent->ret) {
1637 if (!cmd->checksum_disabled)
1638 ent->ret = verify_signature(ent);
1639 else
1640 ent->ret = 0;
1641 if (vec & MLX5_TRIGGERED_CMD_COMP)
1642 ent->status = MLX5_DRIVER_STATUS_ABORTED;
1643 else
1644 ent->status = ent->lay->status_own >> 1;
1645
1646 mlx5_core_dbg(dev, "command completed. ret 0x%x, delivery status %s(0x%x)\n",
1647 ent->ret, deliv_status_to_str(ent->status), ent->status);
1648 }
1649
1650 if (ent->callback) {
1651 ds = ent->ts2 - ent->ts1;
1652 if (ent->op < MLX5_CMD_OP_MAX) {
1653 stats = &cmd->stats[ent->op];
1654 spin_lock_irqsave(&stats->lock, flags);
1655 stats->sum += ds;
1656 ++stats->n;
1657 spin_unlock_irqrestore(&stats->lock, flags);
1658 }
1659
1660 callback = ent->callback;
1661 context = ent->context;
1662 err = ent->ret;
1663 if (!err) {
1664 err = mlx5_copy_from_msg(ent->uout,
1665 ent->out,
1666 ent->uout_size);
1667
1668 err = err ? err : mlx5_cmd_check(dev,
1669 ent->in->first.data,
1670 ent->uout);
1671 }
1672
1673 mlx5_free_cmd_msg(dev, ent->out);
1674 free_msg(dev, ent->in);
1675
1676 err = err ? err : ent->status;
1677 /* final consumer is done, release ent */
1678 cmd_ent_put(ent);
1679 callback(err, context);
1680 } else {
1681 /* release wait_func() so mlx5_cmd_invoke()
1682 * can make the final ent_put()
1683 */
1684 complete(&ent->done);
1685 }
1686 up(sem);
1687 }
1688 }
1689 }
1690
mlx5_cmd_trigger_completions(struct mlx5_core_dev * dev)1691 void mlx5_cmd_trigger_completions(struct mlx5_core_dev *dev)
1692 {
1693 struct mlx5_cmd *cmd = &dev->cmd;
1694 unsigned long bitmask;
1695 unsigned long flags;
1696 u64 vector;
1697 int i;
1698
1699 /* wait for pending handlers to complete */
1700 mlx5_eq_synchronize_cmd_irq(dev);
1701 spin_lock_irqsave(&dev->cmd.alloc_lock, flags);
1702 vector = ~dev->cmd.bitmask & ((1ul << (1 << dev->cmd.log_sz)) - 1);
1703 if (!vector)
1704 goto no_trig;
1705
1706 bitmask = vector;
1707 /* we must increment the allocated entries refcount before triggering the completions
1708 * to guarantee pending commands will not get freed in the meanwhile.
1709 * For that reason, it also has to be done inside the alloc_lock.
1710 */
1711 for_each_set_bit(i, &bitmask, (1 << cmd->log_sz))
1712 cmd_ent_get(cmd->ent_arr[i]);
1713 vector |= MLX5_TRIGGERED_CMD_COMP;
1714 spin_unlock_irqrestore(&dev->cmd.alloc_lock, flags);
1715
1716 mlx5_core_dbg(dev, "vector 0x%llx\n", vector);
1717 mlx5_cmd_comp_handler(dev, vector, true);
1718 for_each_set_bit(i, &bitmask, (1 << cmd->log_sz))
1719 cmd_ent_put(cmd->ent_arr[i]);
1720 return;
1721
1722 no_trig:
1723 spin_unlock_irqrestore(&dev->cmd.alloc_lock, flags);
1724 }
1725
mlx5_cmd_flush(struct mlx5_core_dev * dev)1726 void mlx5_cmd_flush(struct mlx5_core_dev *dev)
1727 {
1728 struct mlx5_cmd *cmd = &dev->cmd;
1729 int i;
1730
1731 for (i = 0; i < cmd->max_reg_cmds; i++)
1732 while (down_trylock(&cmd->sem))
1733 mlx5_cmd_trigger_completions(dev);
1734
1735 while (down_trylock(&cmd->pages_sem))
1736 mlx5_cmd_trigger_completions(dev);
1737
1738 /* Unlock cmdif */
1739 up(&cmd->pages_sem);
1740 for (i = 0; i < cmd->max_reg_cmds; i++)
1741 up(&cmd->sem);
1742 }
1743
status_to_err(u8 status)1744 static int status_to_err(u8 status)
1745 {
1746 switch (status) {
1747 case MLX5_CMD_DELIVERY_STAT_OK:
1748 case MLX5_DRIVER_STATUS_ABORTED:
1749 return 0;
1750 case MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR:
1751 case MLX5_CMD_DELIVERY_STAT_TOK_ERR:
1752 return -EBADR;
1753 case MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR:
1754 case MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR:
1755 case MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR:
1756 return -EFAULT; /* Bad address */
1757 case MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR:
1758 case MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR:
1759 case MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR:
1760 case MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR:
1761 return -ENOMSG;
1762 case MLX5_CMD_DELIVERY_STAT_FW_ERR:
1763 return -EIO;
1764 default:
1765 return -EINVAL;
1766 }
1767 }
1768
alloc_msg(struct mlx5_core_dev * dev,int in_size,gfp_t gfp)1769 static struct mlx5_cmd_msg *alloc_msg(struct mlx5_core_dev *dev, int in_size,
1770 gfp_t gfp)
1771 {
1772 struct mlx5_cmd_msg *msg = ERR_PTR(-ENOMEM);
1773 struct cmd_msg_cache *ch = NULL;
1774 struct mlx5_cmd *cmd = &dev->cmd;
1775 int i;
1776
1777 if (in_size <= 16)
1778 goto cache_miss;
1779
1780 for (i = 0; i < MLX5_NUM_COMMAND_CACHES; i++) {
1781 ch = &cmd->cache[i];
1782 if (in_size > ch->max_inbox_size)
1783 continue;
1784 spin_lock_irq(&ch->lock);
1785 if (list_empty(&ch->head)) {
1786 spin_unlock_irq(&ch->lock);
1787 continue;
1788 }
1789 msg = list_entry(ch->head.next, typeof(*msg), list);
1790 /* For cached lists, we must explicitly state what is
1791 * the real size
1792 */
1793 msg->len = in_size;
1794 list_del(&msg->list);
1795 spin_unlock_irq(&ch->lock);
1796 break;
1797 }
1798
1799 if (!IS_ERR(msg))
1800 return msg;
1801
1802 cache_miss:
1803 msg = mlx5_alloc_cmd_msg(dev, gfp, in_size, 0);
1804 return msg;
1805 }
1806
is_manage_pages(void * in)1807 static int is_manage_pages(void *in)
1808 {
1809 return MLX5_GET(mbox_in, in, opcode) == MLX5_CMD_OP_MANAGE_PAGES;
1810 }
1811
cmd_exec(struct mlx5_core_dev * dev,void * in,int in_size,void * out,int out_size,mlx5_cmd_cbk_t callback,void * context,bool force_polling)1812 static int cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1813 int out_size, mlx5_cmd_cbk_t callback, void *context,
1814 bool force_polling)
1815 {
1816 struct mlx5_cmd_msg *inb;
1817 struct mlx5_cmd_msg *outb;
1818 int pages_queue;
1819 gfp_t gfp;
1820 int err;
1821 u8 status = 0;
1822 u32 drv_synd;
1823 u16 opcode;
1824 u8 token;
1825
1826 opcode = MLX5_GET(mbox_in, in, opcode);
1827 if (mlx5_cmd_is_down(dev) || !opcode_allowed(&dev->cmd, opcode)) {
1828 err = mlx5_internal_err_ret_value(dev, opcode, &drv_synd, &status);
1829 MLX5_SET(mbox_out, out, status, status);
1830 MLX5_SET(mbox_out, out, syndrome, drv_synd);
1831 return err;
1832 }
1833
1834 pages_queue = is_manage_pages(in);
1835 gfp = callback ? GFP_ATOMIC : GFP_KERNEL;
1836
1837 inb = alloc_msg(dev, in_size, gfp);
1838 if (IS_ERR(inb)) {
1839 err = PTR_ERR(inb);
1840 return err;
1841 }
1842
1843 token = alloc_token(&dev->cmd);
1844
1845 err = mlx5_copy_to_msg(inb, in, in_size, token);
1846 if (err) {
1847 mlx5_core_warn(dev, "err %d\n", err);
1848 goto out_in;
1849 }
1850
1851 outb = mlx5_alloc_cmd_msg(dev, gfp, out_size, token);
1852 if (IS_ERR(outb)) {
1853 err = PTR_ERR(outb);
1854 goto out_in;
1855 }
1856
1857 err = mlx5_cmd_invoke(dev, inb, outb, out, out_size, callback, context,
1858 pages_queue, &status, token, force_polling);
1859 if (err)
1860 goto out_out;
1861
1862 mlx5_core_dbg(dev, "err %d, status %d\n", err, status);
1863 if (status) {
1864 err = status_to_err(status);
1865 goto out_out;
1866 }
1867
1868 if (!callback)
1869 err = mlx5_copy_from_msg(out, outb, out_size);
1870
1871 out_out:
1872 if (!callback)
1873 mlx5_free_cmd_msg(dev, outb);
1874
1875 out_in:
1876 if (!callback)
1877 free_msg(dev, inb);
1878 return err;
1879 }
1880
mlx5_cmd_exec(struct mlx5_core_dev * dev,void * in,int in_size,void * out,int out_size)1881 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1882 int out_size)
1883 {
1884 int err;
1885
1886 err = cmd_exec(dev, in, in_size, out, out_size, NULL, NULL, false);
1887 return err ? : mlx5_cmd_check(dev, in, out);
1888 }
1889 EXPORT_SYMBOL(mlx5_cmd_exec);
1890
mlx5_cmd_init_async_ctx(struct mlx5_core_dev * dev,struct mlx5_async_ctx * ctx)1891 void mlx5_cmd_init_async_ctx(struct mlx5_core_dev *dev,
1892 struct mlx5_async_ctx *ctx)
1893 {
1894 ctx->dev = dev;
1895 /* Starts at 1 to avoid doing wake_up if we are not cleaning up */
1896 atomic_set(&ctx->num_inflight, 1);
1897 init_waitqueue_head(&ctx->wait);
1898 }
1899 EXPORT_SYMBOL(mlx5_cmd_init_async_ctx);
1900
1901 /**
1902 * mlx5_cmd_cleanup_async_ctx - Clean up an async_ctx
1903 * @ctx: The ctx to clean
1904 *
1905 * Upon return all callbacks given to mlx5_cmd_exec_cb() have been called. The
1906 * caller must ensure that mlx5_cmd_exec_cb() is not called during or after
1907 * the call mlx5_cleanup_async_ctx().
1908 */
mlx5_cmd_cleanup_async_ctx(struct mlx5_async_ctx * ctx)1909 void mlx5_cmd_cleanup_async_ctx(struct mlx5_async_ctx *ctx)
1910 {
1911 atomic_dec(&ctx->num_inflight);
1912 wait_event(ctx->wait, atomic_read(&ctx->num_inflight) == 0);
1913 }
1914 EXPORT_SYMBOL(mlx5_cmd_cleanup_async_ctx);
1915
mlx5_cmd_exec_cb_handler(int status,void * _work)1916 static void mlx5_cmd_exec_cb_handler(int status, void *_work)
1917 {
1918 struct mlx5_async_work *work = _work;
1919 struct mlx5_async_ctx *ctx = work->ctx;
1920
1921 work->user_callback(status, work);
1922 if (atomic_dec_and_test(&ctx->num_inflight))
1923 wake_up(&ctx->wait);
1924 }
1925
mlx5_cmd_exec_cb(struct mlx5_async_ctx * ctx,void * in,int in_size,void * out,int out_size,mlx5_async_cbk_t callback,struct mlx5_async_work * work)1926 int mlx5_cmd_exec_cb(struct mlx5_async_ctx *ctx, void *in, int in_size,
1927 void *out, int out_size, mlx5_async_cbk_t callback,
1928 struct mlx5_async_work *work)
1929 {
1930 int ret;
1931
1932 work->ctx = ctx;
1933 work->user_callback = callback;
1934 if (WARN_ON(!atomic_inc_not_zero(&ctx->num_inflight)))
1935 return -EIO;
1936 ret = cmd_exec(ctx->dev, in, in_size, out, out_size,
1937 mlx5_cmd_exec_cb_handler, work, false);
1938 if (ret && atomic_dec_and_test(&ctx->num_inflight))
1939 wake_up(&ctx->wait);
1940
1941 return ret;
1942 }
1943 EXPORT_SYMBOL(mlx5_cmd_exec_cb);
1944
mlx5_cmd_exec_polling(struct mlx5_core_dev * dev,void * in,int in_size,void * out,int out_size)1945 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
1946 void *out, int out_size)
1947 {
1948 int err;
1949
1950 err = cmd_exec(dev, in, in_size, out, out_size, NULL, NULL, true);
1951
1952 return err ? : mlx5_cmd_check(dev, in, out);
1953 }
1954 EXPORT_SYMBOL(mlx5_cmd_exec_polling);
1955
destroy_msg_cache(struct mlx5_core_dev * dev)1956 static void destroy_msg_cache(struct mlx5_core_dev *dev)
1957 {
1958 struct cmd_msg_cache *ch;
1959 struct mlx5_cmd_msg *msg;
1960 struct mlx5_cmd_msg *n;
1961 int i;
1962
1963 for (i = 0; i < MLX5_NUM_COMMAND_CACHES; i++) {
1964 ch = &dev->cmd.cache[i];
1965 list_for_each_entry_safe(msg, n, &ch->head, list) {
1966 list_del(&msg->list);
1967 mlx5_free_cmd_msg(dev, msg);
1968 }
1969 }
1970 }
1971
1972 static unsigned cmd_cache_num_ent[MLX5_NUM_COMMAND_CACHES] = {
1973 512, 32, 16, 8, 2
1974 };
1975
1976 static unsigned cmd_cache_ent_size[MLX5_NUM_COMMAND_CACHES] = {
1977 16 + MLX5_CMD_DATA_BLOCK_SIZE,
1978 16 + MLX5_CMD_DATA_BLOCK_SIZE * 2,
1979 16 + MLX5_CMD_DATA_BLOCK_SIZE * 16,
1980 16 + MLX5_CMD_DATA_BLOCK_SIZE * 256,
1981 16 + MLX5_CMD_DATA_BLOCK_SIZE * 512,
1982 };
1983
create_msg_cache(struct mlx5_core_dev * dev)1984 static void create_msg_cache(struct mlx5_core_dev *dev)
1985 {
1986 struct mlx5_cmd *cmd = &dev->cmd;
1987 struct cmd_msg_cache *ch;
1988 struct mlx5_cmd_msg *msg;
1989 int i;
1990 int k;
1991
1992 /* Initialize and fill the caches with initial entries */
1993 for (k = 0; k < MLX5_NUM_COMMAND_CACHES; k++) {
1994 ch = &cmd->cache[k];
1995 spin_lock_init(&ch->lock);
1996 INIT_LIST_HEAD(&ch->head);
1997 ch->num_ent = cmd_cache_num_ent[k];
1998 ch->max_inbox_size = cmd_cache_ent_size[k];
1999 for (i = 0; i < ch->num_ent; i++) {
2000 msg = mlx5_alloc_cmd_msg(dev, GFP_KERNEL | __GFP_NOWARN,
2001 ch->max_inbox_size, 0);
2002 if (IS_ERR(msg))
2003 break;
2004 msg->parent = ch;
2005 list_add_tail(&msg->list, &ch->head);
2006 }
2007 }
2008 }
2009
alloc_cmd_page(struct mlx5_core_dev * dev,struct mlx5_cmd * cmd)2010 static int alloc_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd)
2011 {
2012 cmd->cmd_alloc_buf = dma_alloc_coherent(mlx5_core_dma_dev(dev), MLX5_ADAPTER_PAGE_SIZE,
2013 &cmd->alloc_dma, GFP_KERNEL);
2014 if (!cmd->cmd_alloc_buf)
2015 return -ENOMEM;
2016
2017 /* make sure it is aligned to 4K */
2018 if (!((uintptr_t)cmd->cmd_alloc_buf & (MLX5_ADAPTER_PAGE_SIZE - 1))) {
2019 cmd->cmd_buf = cmd->cmd_alloc_buf;
2020 cmd->dma = cmd->alloc_dma;
2021 cmd->alloc_size = MLX5_ADAPTER_PAGE_SIZE;
2022 return 0;
2023 }
2024
2025 dma_free_coherent(mlx5_core_dma_dev(dev), MLX5_ADAPTER_PAGE_SIZE, cmd->cmd_alloc_buf,
2026 cmd->alloc_dma);
2027 cmd->cmd_alloc_buf = dma_alloc_coherent(mlx5_core_dma_dev(dev),
2028 2 * MLX5_ADAPTER_PAGE_SIZE - 1,
2029 &cmd->alloc_dma, GFP_KERNEL);
2030 if (!cmd->cmd_alloc_buf)
2031 return -ENOMEM;
2032
2033 cmd->cmd_buf = PTR_ALIGN(cmd->cmd_alloc_buf, MLX5_ADAPTER_PAGE_SIZE);
2034 cmd->dma = ALIGN(cmd->alloc_dma, MLX5_ADAPTER_PAGE_SIZE);
2035 cmd->alloc_size = 2 * MLX5_ADAPTER_PAGE_SIZE - 1;
2036 return 0;
2037 }
2038
free_cmd_page(struct mlx5_core_dev * dev,struct mlx5_cmd * cmd)2039 static void free_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd)
2040 {
2041 dma_free_coherent(mlx5_core_dma_dev(dev), cmd->alloc_size, cmd->cmd_alloc_buf,
2042 cmd->alloc_dma);
2043 }
2044
cmdif_rev(struct mlx5_core_dev * dev)2045 static u16 cmdif_rev(struct mlx5_core_dev *dev)
2046 {
2047 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
2048 }
2049
mlx5_cmd_init(struct mlx5_core_dev * dev)2050 int mlx5_cmd_init(struct mlx5_core_dev *dev)
2051 {
2052 int size = sizeof(struct mlx5_cmd_prot_block);
2053 int align = roundup_pow_of_two(size);
2054 struct mlx5_cmd *cmd = &dev->cmd;
2055 u32 cmd_h, cmd_l;
2056 u16 cmd_if_rev;
2057 int err;
2058 int i;
2059
2060 memset(cmd, 0, sizeof(*cmd));
2061 cmd_if_rev = cmdif_rev(dev);
2062 if (cmd_if_rev != CMD_IF_REV) {
2063 mlx5_core_err(dev,
2064 "Driver cmdif rev(%d) differs from firmware's(%d)\n",
2065 CMD_IF_REV, cmd_if_rev);
2066 return -EINVAL;
2067 }
2068
2069 cmd->stats = kvcalloc(MLX5_CMD_OP_MAX, sizeof(*cmd->stats), GFP_KERNEL);
2070 if (!cmd->stats)
2071 return -ENOMEM;
2072
2073 cmd->pool = dma_pool_create("mlx5_cmd", mlx5_core_dma_dev(dev), size, align, 0);
2074 if (!cmd->pool) {
2075 err = -ENOMEM;
2076 goto dma_pool_err;
2077 }
2078
2079 err = alloc_cmd_page(dev, cmd);
2080 if (err)
2081 goto err_free_pool;
2082
2083 cmd_l = ioread32be(&dev->iseg->cmdq_addr_l_sz) & 0xff;
2084 cmd->log_sz = cmd_l >> 4 & 0xf;
2085 cmd->log_stride = cmd_l & 0xf;
2086 if (1 << cmd->log_sz > MLX5_MAX_COMMANDS) {
2087 mlx5_core_err(dev, "firmware reports too many outstanding commands %d\n",
2088 1 << cmd->log_sz);
2089 err = -EINVAL;
2090 goto err_free_page;
2091 }
2092
2093 if (cmd->log_sz + cmd->log_stride > MLX5_ADAPTER_PAGE_SHIFT) {
2094 mlx5_core_err(dev, "command queue size overflow\n");
2095 err = -EINVAL;
2096 goto err_free_page;
2097 }
2098
2099 cmd->state = MLX5_CMDIF_STATE_DOWN;
2100 cmd->checksum_disabled = 1;
2101 cmd->max_reg_cmds = (1 << cmd->log_sz) - 1;
2102 cmd->bitmask = (1UL << cmd->max_reg_cmds) - 1;
2103
2104 cmd->cmdif_rev = ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
2105 if (cmd->cmdif_rev > CMD_IF_REV) {
2106 mlx5_core_err(dev, "driver does not support command interface version. driver %d, firmware %d\n",
2107 CMD_IF_REV, cmd->cmdif_rev);
2108 err = -EOPNOTSUPP;
2109 goto err_free_page;
2110 }
2111
2112 spin_lock_init(&cmd->alloc_lock);
2113 spin_lock_init(&cmd->token_lock);
2114 for (i = 0; i < MLX5_CMD_OP_MAX; i++)
2115 spin_lock_init(&cmd->stats[i].lock);
2116
2117 sema_init(&cmd->sem, cmd->max_reg_cmds);
2118 sema_init(&cmd->pages_sem, 1);
2119
2120 cmd_h = (u32)((u64)(cmd->dma) >> 32);
2121 cmd_l = (u32)(cmd->dma);
2122 if (cmd_l & 0xfff) {
2123 mlx5_core_err(dev, "invalid command queue address\n");
2124 err = -ENOMEM;
2125 goto err_free_page;
2126 }
2127
2128 iowrite32be(cmd_h, &dev->iseg->cmdq_addr_h);
2129 iowrite32be(cmd_l, &dev->iseg->cmdq_addr_l_sz);
2130
2131 /* Make sure firmware sees the complete address before we proceed */
2132 wmb();
2133
2134 mlx5_core_dbg(dev, "descriptor at dma 0x%llx\n", (unsigned long long)(cmd->dma));
2135
2136 cmd->mode = CMD_MODE_POLLING;
2137 cmd->allowed_opcode = CMD_ALLOWED_OPCODE_ALL;
2138
2139 create_msg_cache(dev);
2140
2141 set_wqname(dev);
2142 cmd->wq = create_singlethread_workqueue(cmd->wq_name);
2143 if (!cmd->wq) {
2144 mlx5_core_err(dev, "failed to create command workqueue\n");
2145 err = -ENOMEM;
2146 goto err_cache;
2147 }
2148
2149 create_debugfs_files(dev);
2150
2151 return 0;
2152
2153 err_cache:
2154 destroy_msg_cache(dev);
2155
2156 err_free_page:
2157 free_cmd_page(dev, cmd);
2158
2159 err_free_pool:
2160 dma_pool_destroy(cmd->pool);
2161 dma_pool_err:
2162 kvfree(cmd->stats);
2163 return err;
2164 }
2165
mlx5_cmd_cleanup(struct mlx5_core_dev * dev)2166 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev)
2167 {
2168 struct mlx5_cmd *cmd = &dev->cmd;
2169
2170 clean_debug_files(dev);
2171 destroy_workqueue(cmd->wq);
2172 destroy_msg_cache(dev);
2173 free_cmd_page(dev, cmd);
2174 dma_pool_destroy(cmd->pool);
2175 kvfree(cmd->stats);
2176 }
2177
mlx5_cmd_set_state(struct mlx5_core_dev * dev,enum mlx5_cmdif_state cmdif_state)2178 void mlx5_cmd_set_state(struct mlx5_core_dev *dev,
2179 enum mlx5_cmdif_state cmdif_state)
2180 {
2181 dev->cmd.state = cmdif_state;
2182 }
2183