1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/highmem.h>
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/errno.h>
37 #include <linux/pci.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/slab.h>
40 #include <linux/io-mapping.h>
41 #include <linux/interrupt.h>
42 #include <linux/delay.h>
43 #include <linux/mlx5/driver.h>
44 #include <linux/mlx5/cq.h>
45 #include <linux/mlx5/qp.h>
46 #include <linux/debugfs.h>
47 #include <linux/kmod.h>
48 #include <linux/mlx5/mlx5_ifc.h>
49 #include <linux/mlx5/vport.h>
50 #ifdef CONFIG_RFS_ACCEL
51 #include <linux/cpu_rmap.h>
52 #endif
53 #include <linux/version.h>
54 #include <net/devlink.h>
55 #include "mlx5_core.h"
56 #include "lib/eq.h"
57 #include "fs_core.h"
58 #include "lib/mpfs.h"
59 #include "eswitch.h"
60 #include "devlink.h"
61 #include "fw_reset.h"
62 #include "lib/mlx5.h"
63 #include "lib/tout.h"
64 #include "fpga/core.h"
65 #include "fpga/ipsec.h"
66 #include "accel/ipsec.h"
67 #include "accel/tls.h"
68 #include "lib/clock.h"
69 #include "lib/vxlan.h"
70 #include "lib/geneve.h"
71 #include "lib/devcom.h"
72 #include "lib/pci_vsc.h"
73 #include "diag/fw_tracer.h"
74 #include "ecpf.h"
75 #include "lib/hv_vhca.h"
76 #include "diag/rsc_dump.h"
77 #include "sf/vhca_event.h"
78 #include "sf/dev/dev.h"
79 #include "sf/sf.h"
80 #include "mlx5_irq.h"
81
82 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
83 MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) core driver");
84 MODULE_LICENSE("Dual BSD/GPL");
85
86 unsigned int mlx5_core_debug_mask;
87 module_param_named(debug_mask, mlx5_core_debug_mask, uint, 0644);
88 MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
89
90 static unsigned int prof_sel = MLX5_DEFAULT_PROF;
91 module_param_named(prof_sel, prof_sel, uint, 0444);
92 MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
93
94 static u32 sw_owner_id[4];
95
96 enum {
97 MLX5_ATOMIC_REQ_MODE_BE = 0x0,
98 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1,
99 };
100
101 static struct mlx5_profile profile[] = {
102 [0] = {
103 .mask = 0,
104 },
105 [1] = {
106 .mask = MLX5_PROF_MASK_QP_SIZE,
107 .log_max_qp = 12,
108 },
109 [2] = {
110 .mask = MLX5_PROF_MASK_QP_SIZE |
111 MLX5_PROF_MASK_MR_CACHE,
112 .log_max_qp = 18,
113 .mr_cache[0] = {
114 .size = 500,
115 .limit = 250
116 },
117 .mr_cache[1] = {
118 .size = 500,
119 .limit = 250
120 },
121 .mr_cache[2] = {
122 .size = 500,
123 .limit = 250
124 },
125 .mr_cache[3] = {
126 .size = 500,
127 .limit = 250
128 },
129 .mr_cache[4] = {
130 .size = 500,
131 .limit = 250
132 },
133 .mr_cache[5] = {
134 .size = 500,
135 .limit = 250
136 },
137 .mr_cache[6] = {
138 .size = 500,
139 .limit = 250
140 },
141 .mr_cache[7] = {
142 .size = 500,
143 .limit = 250
144 },
145 .mr_cache[8] = {
146 .size = 500,
147 .limit = 250
148 },
149 .mr_cache[9] = {
150 .size = 500,
151 .limit = 250
152 },
153 .mr_cache[10] = {
154 .size = 500,
155 .limit = 250
156 },
157 .mr_cache[11] = {
158 .size = 500,
159 .limit = 250
160 },
161 .mr_cache[12] = {
162 .size = 64,
163 .limit = 32
164 },
165 .mr_cache[13] = {
166 .size = 32,
167 .limit = 16
168 },
169 .mr_cache[14] = {
170 .size = 16,
171 .limit = 8
172 },
173 .mr_cache[15] = {
174 .size = 8,
175 .limit = 4
176 },
177 },
178 };
179
fw_initializing(struct mlx5_core_dev * dev)180 static int fw_initializing(struct mlx5_core_dev *dev)
181 {
182 return ioread32be(&dev->iseg->initializing) >> 31;
183 }
184
wait_fw_init(struct mlx5_core_dev * dev,u32 max_wait_mili,u32 warn_time_mili)185 static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili,
186 u32 warn_time_mili)
187 {
188 unsigned long warn = jiffies + msecs_to_jiffies(warn_time_mili);
189 unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili);
190 int err = 0;
191
192 while (fw_initializing(dev)) {
193 if (time_after(jiffies, end)) {
194 err = -EBUSY;
195 break;
196 }
197 if (warn_time_mili && time_after(jiffies, warn)) {
198 mlx5_core_warn(dev, "Waiting for FW initialization, timeout abort in %ds\n",
199 jiffies_to_msecs(end - warn) / 1000);
200 warn = jiffies + msecs_to_jiffies(warn_time_mili);
201 }
202 msleep(mlx5_tout_ms(dev, FW_PRE_INIT_WAIT));
203 }
204
205 return err;
206 }
207
mlx5_set_driver_version(struct mlx5_core_dev * dev)208 static void mlx5_set_driver_version(struct mlx5_core_dev *dev)
209 {
210 int driver_ver_sz = MLX5_FLD_SZ_BYTES(set_driver_version_in,
211 driver_version);
212 u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {};
213 int remaining_size = driver_ver_sz;
214 char *string;
215
216 if (!MLX5_CAP_GEN(dev, driver_version))
217 return;
218
219 string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version);
220
221 strncpy(string, "Linux", remaining_size);
222
223 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
224 strncat(string, ",", remaining_size);
225
226 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
227 strncat(string, KBUILD_MODNAME, remaining_size);
228
229 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
230 strncat(string, ",", remaining_size);
231
232 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
233
234 snprintf(string + strlen(string), remaining_size, "%u.%u.%u",
235 LINUX_VERSION_MAJOR, LINUX_VERSION_PATCHLEVEL,
236 LINUX_VERSION_SUBLEVEL);
237
238 /*Send the command*/
239 MLX5_SET(set_driver_version_in, in, opcode,
240 MLX5_CMD_OP_SET_DRIVER_VERSION);
241
242 mlx5_cmd_exec_in(dev, set_driver_version, in);
243 }
244
set_dma_caps(struct pci_dev * pdev)245 static int set_dma_caps(struct pci_dev *pdev)
246 {
247 int err;
248
249 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
250 if (err) {
251 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
252 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
253 if (err) {
254 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
255 return err;
256 }
257 }
258
259 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
260 return err;
261 }
262
mlx5_pci_enable_device(struct mlx5_core_dev * dev)263 static int mlx5_pci_enable_device(struct mlx5_core_dev *dev)
264 {
265 struct pci_dev *pdev = dev->pdev;
266 int err = 0;
267
268 mutex_lock(&dev->pci_status_mutex);
269 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) {
270 err = pci_enable_device(pdev);
271 if (!err)
272 dev->pci_status = MLX5_PCI_STATUS_ENABLED;
273 }
274 mutex_unlock(&dev->pci_status_mutex);
275
276 return err;
277 }
278
mlx5_pci_disable_device(struct mlx5_core_dev * dev)279 static void mlx5_pci_disable_device(struct mlx5_core_dev *dev)
280 {
281 struct pci_dev *pdev = dev->pdev;
282
283 mutex_lock(&dev->pci_status_mutex);
284 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) {
285 pci_disable_device(pdev);
286 dev->pci_status = MLX5_PCI_STATUS_DISABLED;
287 }
288 mutex_unlock(&dev->pci_status_mutex);
289 }
290
request_bar(struct pci_dev * pdev)291 static int request_bar(struct pci_dev *pdev)
292 {
293 int err = 0;
294
295 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
296 dev_err(&pdev->dev, "Missing registers BAR, aborting\n");
297 return -ENODEV;
298 }
299
300 err = pci_request_regions(pdev, KBUILD_MODNAME);
301 if (err)
302 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
303
304 return err;
305 }
306
release_bar(struct pci_dev * pdev)307 static void release_bar(struct pci_dev *pdev)
308 {
309 pci_release_regions(pdev);
310 }
311
312 struct mlx5_reg_host_endianness {
313 u8 he;
314 u8 rsvd[15];
315 };
316
317 #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
318
319 enum {
320 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
321 MLX5_DEV_CAP_FLAG_DCT,
322 };
323
to_fw_pkey_sz(struct mlx5_core_dev * dev,u32 size)324 static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size)
325 {
326 switch (size) {
327 case 128:
328 return 0;
329 case 256:
330 return 1;
331 case 512:
332 return 2;
333 case 1024:
334 return 3;
335 case 2048:
336 return 4;
337 case 4096:
338 return 5;
339 default:
340 mlx5_core_warn(dev, "invalid pkey table size %d\n", size);
341 return 0;
342 }
343 }
344
mlx5_core_get_caps_mode(struct mlx5_core_dev * dev,enum mlx5_cap_type cap_type,enum mlx5_cap_mode cap_mode)345 static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev,
346 enum mlx5_cap_type cap_type,
347 enum mlx5_cap_mode cap_mode)
348 {
349 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
350 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
351 void *out, *hca_caps;
352 u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
353 int err;
354
355 memset(in, 0, sizeof(in));
356 out = kzalloc(out_sz, GFP_KERNEL);
357 if (!out)
358 return -ENOMEM;
359
360 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
361 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
362 err = mlx5_cmd_exec_inout(dev, query_hca_cap, in, out);
363 if (err) {
364 mlx5_core_warn(dev,
365 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
366 cap_type, cap_mode, err);
367 goto query_ex;
368 }
369
370 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
371
372 switch (cap_mode) {
373 case HCA_CAP_OPMOD_GET_MAX:
374 memcpy(dev->caps.hca[cap_type]->max, hca_caps,
375 MLX5_UN_SZ_BYTES(hca_cap_union));
376 break;
377 case HCA_CAP_OPMOD_GET_CUR:
378 memcpy(dev->caps.hca[cap_type]->cur, hca_caps,
379 MLX5_UN_SZ_BYTES(hca_cap_union));
380 break;
381 default:
382 mlx5_core_warn(dev,
383 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
384 cap_type, cap_mode);
385 err = -EINVAL;
386 break;
387 }
388 query_ex:
389 kfree(out);
390 return err;
391 }
392
mlx5_core_get_caps(struct mlx5_core_dev * dev,enum mlx5_cap_type cap_type)393 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type)
394 {
395 int ret;
396
397 ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR);
398 if (ret)
399 return ret;
400 return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX);
401 }
402
set_caps(struct mlx5_core_dev * dev,void * in,int opmod)403 static int set_caps(struct mlx5_core_dev *dev, void *in, int opmod)
404 {
405 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
406 MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1);
407 return mlx5_cmd_exec_in(dev, set_hca_cap, in);
408 }
409
handle_hca_cap_atomic(struct mlx5_core_dev * dev,void * set_ctx)410 static int handle_hca_cap_atomic(struct mlx5_core_dev *dev, void *set_ctx)
411 {
412 void *set_hca_cap;
413 int req_endianness;
414 int err;
415
416 if (!MLX5_CAP_GEN(dev, atomic))
417 return 0;
418
419 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC);
420 if (err)
421 return err;
422
423 req_endianness =
424 MLX5_CAP_ATOMIC(dev,
425 supported_atomic_req_8B_endianness_mode_1);
426
427 if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS)
428 return 0;
429
430 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
431
432 /* Set requestor to host endianness */
433 MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianness_mode,
434 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS);
435
436 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC);
437 }
438
handle_hca_cap_odp(struct mlx5_core_dev * dev,void * set_ctx)439 static int handle_hca_cap_odp(struct mlx5_core_dev *dev, void *set_ctx)
440 {
441 void *set_hca_cap;
442 bool do_set = false;
443 int err;
444
445 if (!IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) ||
446 !MLX5_CAP_GEN(dev, pg))
447 return 0;
448
449 err = mlx5_core_get_caps(dev, MLX5_CAP_ODP);
450 if (err)
451 return err;
452
453 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
454 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_ODP]->cur,
455 MLX5_ST_SZ_BYTES(odp_cap));
456
457 #define ODP_CAP_SET_MAX(dev, field) \
458 do { \
459 u32 _res = MLX5_CAP_ODP_MAX(dev, field); \
460 if (_res) { \
461 do_set = true; \
462 MLX5_SET(odp_cap, set_hca_cap, field, _res); \
463 } \
464 } while (0)
465
466 ODP_CAP_SET_MAX(dev, ud_odp_caps.srq_receive);
467 ODP_CAP_SET_MAX(dev, rc_odp_caps.srq_receive);
468 ODP_CAP_SET_MAX(dev, xrc_odp_caps.srq_receive);
469 ODP_CAP_SET_MAX(dev, xrc_odp_caps.send);
470 ODP_CAP_SET_MAX(dev, xrc_odp_caps.receive);
471 ODP_CAP_SET_MAX(dev, xrc_odp_caps.write);
472 ODP_CAP_SET_MAX(dev, xrc_odp_caps.read);
473 ODP_CAP_SET_MAX(dev, xrc_odp_caps.atomic);
474 ODP_CAP_SET_MAX(dev, dc_odp_caps.srq_receive);
475 ODP_CAP_SET_MAX(dev, dc_odp_caps.send);
476 ODP_CAP_SET_MAX(dev, dc_odp_caps.receive);
477 ODP_CAP_SET_MAX(dev, dc_odp_caps.write);
478 ODP_CAP_SET_MAX(dev, dc_odp_caps.read);
479 ODP_CAP_SET_MAX(dev, dc_odp_caps.atomic);
480
481 if (!do_set)
482 return 0;
483
484 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ODP);
485 }
486
handle_hca_cap(struct mlx5_core_dev * dev,void * set_ctx)487 static int handle_hca_cap(struct mlx5_core_dev *dev, void *set_ctx)
488 {
489 struct mlx5_profile *prof = &dev->profile;
490 void *set_hca_cap;
491 int err;
492
493 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL);
494 if (err)
495 return err;
496
497 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
498 capability);
499 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_GENERAL]->cur,
500 MLX5_ST_SZ_BYTES(cmd_hca_cap));
501
502 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n",
503 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)),
504 128);
505 /* we limit the size of the pkey table to 128 entries for now */
506 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size,
507 to_fw_pkey_sz(dev, 128));
508
509 /* Check log_max_qp from HCA caps to set in current profile */
510 if (MLX5_CAP_GEN_MAX(dev, log_max_qp) < prof->log_max_qp) {
511 mlx5_core_warn(dev, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n",
512 prof->log_max_qp,
513 MLX5_CAP_GEN_MAX(dev, log_max_qp));
514 prof->log_max_qp = MLX5_CAP_GEN_MAX(dev, log_max_qp);
515 }
516 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
517 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp,
518 prof->log_max_qp);
519
520 /* disable cmdif checksum */
521 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
522
523 /* Enable 4K UAR only when HCA supports it and page size is bigger
524 * than 4K.
525 */
526 if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096)
527 MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1);
528
529 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12);
530
531 if (MLX5_CAP_GEN_MAX(dev, cache_line_128byte))
532 MLX5_SET(cmd_hca_cap,
533 set_hca_cap,
534 cache_line_128byte,
535 cache_line_size() >= 128 ? 1 : 0);
536
537 if (MLX5_CAP_GEN_MAX(dev, dct))
538 MLX5_SET(cmd_hca_cap, set_hca_cap, dct, 1);
539
540 if (MLX5_CAP_GEN_MAX(dev, pci_sync_for_fw_update_event))
541 MLX5_SET(cmd_hca_cap, set_hca_cap, pci_sync_for_fw_update_event, 1);
542
543 if (MLX5_CAP_GEN_MAX(dev, num_vhca_ports))
544 MLX5_SET(cmd_hca_cap,
545 set_hca_cap,
546 num_vhca_ports,
547 MLX5_CAP_GEN_MAX(dev, num_vhca_ports));
548
549 if (MLX5_CAP_GEN_MAX(dev, release_all_pages))
550 MLX5_SET(cmd_hca_cap, set_hca_cap, release_all_pages, 1);
551
552 if (MLX5_CAP_GEN_MAX(dev, mkey_by_name))
553 MLX5_SET(cmd_hca_cap, set_hca_cap, mkey_by_name, 1);
554
555 mlx5_vhca_state_cap_handle(dev, set_hca_cap);
556
557 if (MLX5_CAP_GEN_MAX(dev, num_total_dynamic_vf_msix))
558 MLX5_SET(cmd_hca_cap, set_hca_cap, num_total_dynamic_vf_msix,
559 MLX5_CAP_GEN_MAX(dev, num_total_dynamic_vf_msix));
560
561 if (MLX5_CAP_GEN(dev, roce_rw_supported))
562 MLX5_SET(cmd_hca_cap, set_hca_cap, roce, mlx5_is_roce_init_enabled(dev));
563
564 return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE);
565 }
566
567 /* Cached MLX5_CAP_GEN(dev, roce) can be out of sync this early in the
568 * boot process.
569 * In case RoCE cap is writable in FW and user/devlink requested to change the
570 * cap, we are yet to query the final state of the above cap.
571 * Hence, the need for this function.
572 *
573 * Returns
574 * True:
575 * 1) RoCE cap is read only in FW and already disabled
576 * OR:
577 * 2) RoCE cap is writable in FW and user/devlink requested it off.
578 *
579 * In any other case, return False.
580 */
is_roce_fw_disabled(struct mlx5_core_dev * dev)581 static bool is_roce_fw_disabled(struct mlx5_core_dev *dev)
582 {
583 return (MLX5_CAP_GEN(dev, roce_rw_supported) && !mlx5_is_roce_init_enabled(dev)) ||
584 (!MLX5_CAP_GEN(dev, roce_rw_supported) && !MLX5_CAP_GEN(dev, roce));
585 }
586
handle_hca_cap_roce(struct mlx5_core_dev * dev,void * set_ctx)587 static int handle_hca_cap_roce(struct mlx5_core_dev *dev, void *set_ctx)
588 {
589 void *set_hca_cap;
590 int err;
591
592 if (is_roce_fw_disabled(dev))
593 return 0;
594
595 err = mlx5_core_get_caps(dev, MLX5_CAP_ROCE);
596 if (err)
597 return err;
598
599 if (MLX5_CAP_ROCE(dev, sw_r_roce_src_udp_port) ||
600 !MLX5_CAP_ROCE_MAX(dev, sw_r_roce_src_udp_port))
601 return 0;
602
603 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
604 memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_ROCE]->cur,
605 MLX5_ST_SZ_BYTES(roce_cap));
606 MLX5_SET(roce_cap, set_hca_cap, sw_r_roce_src_udp_port, 1);
607
608 err = set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ROCE);
609 return err;
610 }
611
set_hca_cap(struct mlx5_core_dev * dev)612 static int set_hca_cap(struct mlx5_core_dev *dev)
613 {
614 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
615 void *set_ctx;
616 int err;
617
618 set_ctx = kzalloc(set_sz, GFP_KERNEL);
619 if (!set_ctx)
620 return -ENOMEM;
621
622 err = handle_hca_cap(dev, set_ctx);
623 if (err) {
624 mlx5_core_err(dev, "handle_hca_cap failed\n");
625 goto out;
626 }
627
628 memset(set_ctx, 0, set_sz);
629 err = handle_hca_cap_atomic(dev, set_ctx);
630 if (err) {
631 mlx5_core_err(dev, "handle_hca_cap_atomic failed\n");
632 goto out;
633 }
634
635 memset(set_ctx, 0, set_sz);
636 err = handle_hca_cap_odp(dev, set_ctx);
637 if (err) {
638 mlx5_core_err(dev, "handle_hca_cap_odp failed\n");
639 goto out;
640 }
641
642 memset(set_ctx, 0, set_sz);
643 err = handle_hca_cap_roce(dev, set_ctx);
644 if (err) {
645 mlx5_core_err(dev, "handle_hca_cap_roce failed\n");
646 goto out;
647 }
648
649 out:
650 kfree(set_ctx);
651 return err;
652 }
653
set_hca_ctrl(struct mlx5_core_dev * dev)654 static int set_hca_ctrl(struct mlx5_core_dev *dev)
655 {
656 struct mlx5_reg_host_endianness he_in;
657 struct mlx5_reg_host_endianness he_out;
658 int err;
659
660 if (!mlx5_core_is_pf(dev))
661 return 0;
662
663 memset(&he_in, 0, sizeof(he_in));
664 he_in.he = MLX5_SET_HOST_ENDIANNESS;
665 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
666 &he_out, sizeof(he_out),
667 MLX5_REG_HOST_ENDIANNESS, 0, 1);
668 return err;
669 }
670
mlx5_core_set_hca_defaults(struct mlx5_core_dev * dev)671 static int mlx5_core_set_hca_defaults(struct mlx5_core_dev *dev)
672 {
673 int ret = 0;
674
675 /* Disable local_lb by default */
676 if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH)
677 ret = mlx5_nic_vport_update_local_lb(dev, false);
678
679 return ret;
680 }
681
mlx5_core_enable_hca(struct mlx5_core_dev * dev,u16 func_id)682 int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id)
683 {
684 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {};
685
686 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA);
687 MLX5_SET(enable_hca_in, in, function_id, func_id);
688 MLX5_SET(enable_hca_in, in, embedded_cpu_function,
689 dev->caps.embedded_cpu);
690 return mlx5_cmd_exec_in(dev, enable_hca, in);
691 }
692
mlx5_core_disable_hca(struct mlx5_core_dev * dev,u16 func_id)693 int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id)
694 {
695 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {};
696
697 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA);
698 MLX5_SET(disable_hca_in, in, function_id, func_id);
699 MLX5_SET(enable_hca_in, in, embedded_cpu_function,
700 dev->caps.embedded_cpu);
701 return mlx5_cmd_exec_in(dev, disable_hca, in);
702 }
703
mlx5_core_set_issi(struct mlx5_core_dev * dev)704 static int mlx5_core_set_issi(struct mlx5_core_dev *dev)
705 {
706 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {};
707 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {};
708 u32 sup_issi;
709 int err;
710
711 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI);
712 err = mlx5_cmd_exec_inout(dev, query_issi, query_in, query_out);
713 if (err) {
714 u32 syndrome;
715 u8 status;
716
717 mlx5_cmd_mbox_status(query_out, &status, &syndrome);
718 if (!status || syndrome == MLX5_DRIVER_SYND) {
719 mlx5_core_err(dev, "Failed to query ISSI err(%d) status(%d) synd(%d)\n",
720 err, status, syndrome);
721 return err;
722 }
723
724 mlx5_core_warn(dev, "Query ISSI is not supported by FW, ISSI is 0\n");
725 dev->issi = 0;
726 return 0;
727 }
728
729 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0);
730
731 if (sup_issi & (1 << 1)) {
732 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {};
733
734 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI);
735 MLX5_SET(set_issi_in, set_in, current_issi, 1);
736 err = mlx5_cmd_exec_in(dev, set_issi, set_in);
737 if (err) {
738 mlx5_core_err(dev, "Failed to set ISSI to 1 err(%d)\n",
739 err);
740 return err;
741 }
742
743 dev->issi = 1;
744
745 return 0;
746 } else if (sup_issi & (1 << 0) || !sup_issi) {
747 return 0;
748 }
749
750 return -EOPNOTSUPP;
751 }
752
mlx5_pci_init(struct mlx5_core_dev * dev,struct pci_dev * pdev,const struct pci_device_id * id)753 static int mlx5_pci_init(struct mlx5_core_dev *dev, struct pci_dev *pdev,
754 const struct pci_device_id *id)
755 {
756 int err = 0;
757
758 mutex_init(&dev->pci_status_mutex);
759 pci_set_drvdata(dev->pdev, dev);
760
761 dev->bar_addr = pci_resource_start(pdev, 0);
762
763 err = mlx5_pci_enable_device(dev);
764 if (err) {
765 mlx5_core_err(dev, "Cannot enable PCI device, aborting\n");
766 return err;
767 }
768
769 err = request_bar(pdev);
770 if (err) {
771 mlx5_core_err(dev, "error requesting BARs, aborting\n");
772 goto err_disable;
773 }
774
775 pci_set_master(pdev);
776
777 err = set_dma_caps(pdev);
778 if (err) {
779 mlx5_core_err(dev, "Failed setting DMA capabilities mask, aborting\n");
780 goto err_clr_master;
781 }
782
783 if (pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP32) &&
784 pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP64) &&
785 pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP128))
786 mlx5_core_dbg(dev, "Enabling pci atomics failed\n");
787
788 dev->iseg_base = dev->bar_addr;
789 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
790 if (!dev->iseg) {
791 err = -ENOMEM;
792 mlx5_core_err(dev, "Failed mapping initialization segment, aborting\n");
793 goto err_clr_master;
794 }
795
796 mlx5_pci_vsc_init(dev);
797 dev->caps.embedded_cpu = mlx5_read_embedded_cpu(dev);
798 return 0;
799
800 err_clr_master:
801 pci_clear_master(dev->pdev);
802 release_bar(dev->pdev);
803 err_disable:
804 mlx5_pci_disable_device(dev);
805 return err;
806 }
807
mlx5_pci_close(struct mlx5_core_dev * dev)808 static void mlx5_pci_close(struct mlx5_core_dev *dev)
809 {
810 /* health work might still be active, and it needs pci bar in
811 * order to know the NIC state. Therefore, drain the health WQ
812 * before removing the pci bars
813 */
814 mlx5_drain_health_wq(dev);
815 iounmap(dev->iseg);
816 pci_clear_master(dev->pdev);
817 release_bar(dev->pdev);
818 mlx5_pci_disable_device(dev);
819 }
820
mlx5_init_once(struct mlx5_core_dev * dev)821 static int mlx5_init_once(struct mlx5_core_dev *dev)
822 {
823 int err;
824
825 dev->priv.devcom = mlx5_devcom_register_device(dev);
826 if (IS_ERR(dev->priv.devcom))
827 mlx5_core_err(dev, "failed to register with devcom (0x%p)\n",
828 dev->priv.devcom);
829
830 err = mlx5_query_board_id(dev);
831 if (err) {
832 mlx5_core_err(dev, "query board id failed\n");
833 goto err_devcom;
834 }
835
836 err = mlx5_irq_table_init(dev);
837 if (err) {
838 mlx5_core_err(dev, "failed to initialize irq table\n");
839 goto err_devcom;
840 }
841
842 err = mlx5_eq_table_init(dev);
843 if (err) {
844 mlx5_core_err(dev, "failed to initialize eq\n");
845 goto err_irq_cleanup;
846 }
847
848 err = mlx5_events_init(dev);
849 if (err) {
850 mlx5_core_err(dev, "failed to initialize events\n");
851 goto err_eq_cleanup;
852 }
853
854 err = mlx5_fw_reset_init(dev);
855 if (err) {
856 mlx5_core_err(dev, "failed to initialize fw reset events\n");
857 goto err_events_cleanup;
858 }
859
860 mlx5_cq_debugfs_init(dev);
861
862 mlx5_init_reserved_gids(dev);
863
864 mlx5_init_clock(dev);
865
866 dev->vxlan = mlx5_vxlan_create(dev);
867 dev->geneve = mlx5_geneve_create(dev);
868
869 err = mlx5_init_rl_table(dev);
870 if (err) {
871 mlx5_core_err(dev, "Failed to init rate limiting\n");
872 goto err_tables_cleanup;
873 }
874
875 err = mlx5_mpfs_init(dev);
876 if (err) {
877 mlx5_core_err(dev, "Failed to init l2 table %d\n", err);
878 goto err_rl_cleanup;
879 }
880
881 err = mlx5_sriov_init(dev);
882 if (err) {
883 mlx5_core_err(dev, "Failed to init sriov %d\n", err);
884 goto err_mpfs_cleanup;
885 }
886
887 err = mlx5_eswitch_init(dev);
888 if (err) {
889 mlx5_core_err(dev, "Failed to init eswitch %d\n", err);
890 goto err_sriov_cleanup;
891 }
892
893 err = mlx5_fpga_init(dev);
894 if (err) {
895 mlx5_core_err(dev, "Failed to init fpga device %d\n", err);
896 goto err_eswitch_cleanup;
897 }
898
899 err = mlx5_vhca_event_init(dev);
900 if (err) {
901 mlx5_core_err(dev, "Failed to init vhca event notifier %d\n", err);
902 goto err_fpga_cleanup;
903 }
904
905 err = mlx5_sf_hw_table_init(dev);
906 if (err) {
907 mlx5_core_err(dev, "Failed to init SF HW table %d\n", err);
908 goto err_sf_hw_table_cleanup;
909 }
910
911 err = mlx5_sf_table_init(dev);
912 if (err) {
913 mlx5_core_err(dev, "Failed to init SF table %d\n", err);
914 goto err_sf_table_cleanup;
915 }
916
917 dev->dm = mlx5_dm_create(dev);
918 if (IS_ERR(dev->dm))
919 mlx5_core_warn(dev, "Failed to init device memory%d\n", err);
920
921 dev->tracer = mlx5_fw_tracer_create(dev);
922 dev->hv_vhca = mlx5_hv_vhca_create(dev);
923 dev->rsc_dump = mlx5_rsc_dump_create(dev);
924
925 return 0;
926
927 err_sf_table_cleanup:
928 mlx5_sf_hw_table_cleanup(dev);
929 err_sf_hw_table_cleanup:
930 mlx5_vhca_event_cleanup(dev);
931 err_fpga_cleanup:
932 mlx5_fpga_cleanup(dev);
933 err_eswitch_cleanup:
934 mlx5_eswitch_cleanup(dev->priv.eswitch);
935 err_sriov_cleanup:
936 mlx5_sriov_cleanup(dev);
937 err_mpfs_cleanup:
938 mlx5_mpfs_cleanup(dev);
939 err_rl_cleanup:
940 mlx5_cleanup_rl_table(dev);
941 err_tables_cleanup:
942 mlx5_geneve_destroy(dev->geneve);
943 mlx5_vxlan_destroy(dev->vxlan);
944 mlx5_cq_debugfs_cleanup(dev);
945 mlx5_fw_reset_cleanup(dev);
946 err_events_cleanup:
947 mlx5_events_cleanup(dev);
948 err_eq_cleanup:
949 mlx5_eq_table_cleanup(dev);
950 err_irq_cleanup:
951 mlx5_irq_table_cleanup(dev);
952 err_devcom:
953 mlx5_devcom_unregister_device(dev->priv.devcom);
954
955 return err;
956 }
957
mlx5_cleanup_once(struct mlx5_core_dev * dev)958 static void mlx5_cleanup_once(struct mlx5_core_dev *dev)
959 {
960 mlx5_rsc_dump_destroy(dev);
961 mlx5_hv_vhca_destroy(dev->hv_vhca);
962 mlx5_fw_tracer_destroy(dev->tracer);
963 mlx5_dm_cleanup(dev);
964 mlx5_sf_table_cleanup(dev);
965 mlx5_sf_hw_table_cleanup(dev);
966 mlx5_vhca_event_cleanup(dev);
967 mlx5_fpga_cleanup(dev);
968 mlx5_eswitch_cleanup(dev->priv.eswitch);
969 mlx5_sriov_cleanup(dev);
970 mlx5_mpfs_cleanup(dev);
971 mlx5_cleanup_rl_table(dev);
972 mlx5_geneve_destroy(dev->geneve);
973 mlx5_vxlan_destroy(dev->vxlan);
974 mlx5_cleanup_clock(dev);
975 mlx5_cleanup_reserved_gids(dev);
976 mlx5_cq_debugfs_cleanup(dev);
977 mlx5_fw_reset_cleanup(dev);
978 mlx5_events_cleanup(dev);
979 mlx5_eq_table_cleanup(dev);
980 mlx5_irq_table_cleanup(dev);
981 mlx5_devcom_unregister_device(dev->priv.devcom);
982 }
983
mlx5_function_setup(struct mlx5_core_dev * dev,bool boot)984 static int mlx5_function_setup(struct mlx5_core_dev *dev, bool boot)
985 {
986 int err;
987
988 mlx5_core_info(dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
989 fw_rev_min(dev), fw_rev_sub(dev));
990
991 /* Only PFs hold the relevant PCIe information for this query */
992 if (mlx5_core_is_pf(dev))
993 pcie_print_link_status(dev->pdev);
994
995 mlx5_tout_set_def_val(dev);
996
997 /* wait for firmware to accept initialization segments configurations
998 */
999 err = wait_fw_init(dev, mlx5_tout_ms(dev, FW_PRE_INIT_TIMEOUT),
1000 mlx5_tout_ms(dev, FW_PRE_INIT_WARN_MESSAGE_INTERVAL));
1001 if (err) {
1002 mlx5_core_err(dev, "Firmware over %llu MS in pre-initializing state, aborting\n",
1003 mlx5_tout_ms(dev, FW_PRE_INIT_TIMEOUT));
1004 return err;
1005 }
1006
1007 err = mlx5_cmd_init(dev);
1008 if (err) {
1009 mlx5_core_err(dev, "Failed initializing command interface, aborting\n");
1010 return err;
1011 }
1012
1013 mlx5_tout_query_iseg(dev);
1014
1015 err = wait_fw_init(dev, mlx5_tout_ms(dev, FW_INIT), 0);
1016 if (err) {
1017 mlx5_core_err(dev, "Firmware over %llu MS in initializing state, aborting\n",
1018 mlx5_tout_ms(dev, FW_INIT));
1019 goto err_cmd_cleanup;
1020 }
1021
1022 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_UP);
1023
1024 err = mlx5_core_enable_hca(dev, 0);
1025 if (err) {
1026 mlx5_core_err(dev, "enable hca failed\n");
1027 goto err_cmd_cleanup;
1028 }
1029
1030 err = mlx5_core_set_issi(dev);
1031 if (err) {
1032 mlx5_core_err(dev, "failed to set issi\n");
1033 goto err_disable_hca;
1034 }
1035
1036 err = mlx5_satisfy_startup_pages(dev, 1);
1037 if (err) {
1038 mlx5_core_err(dev, "failed to allocate boot pages\n");
1039 goto err_disable_hca;
1040 }
1041
1042 err = mlx5_tout_query_dtor(dev);
1043 if (err) {
1044 mlx5_core_err(dev, "failed to read dtor\n");
1045 goto reclaim_boot_pages;
1046 }
1047
1048 err = set_hca_ctrl(dev);
1049 if (err) {
1050 mlx5_core_err(dev, "set_hca_ctrl failed\n");
1051 goto reclaim_boot_pages;
1052 }
1053
1054 err = set_hca_cap(dev);
1055 if (err) {
1056 mlx5_core_err(dev, "set_hca_cap failed\n");
1057 goto reclaim_boot_pages;
1058 }
1059
1060 err = mlx5_satisfy_startup_pages(dev, 0);
1061 if (err) {
1062 mlx5_core_err(dev, "failed to allocate init pages\n");
1063 goto reclaim_boot_pages;
1064 }
1065
1066 err = mlx5_cmd_init_hca(dev, sw_owner_id);
1067 if (err) {
1068 mlx5_core_err(dev, "init hca failed\n");
1069 goto reclaim_boot_pages;
1070 }
1071
1072 mlx5_set_driver_version(dev);
1073
1074 err = mlx5_query_hca_caps(dev);
1075 if (err) {
1076 mlx5_core_err(dev, "query hca failed\n");
1077 goto reclaim_boot_pages;
1078 }
1079
1080 mlx5_start_health_poll(dev);
1081
1082 return 0;
1083
1084 reclaim_boot_pages:
1085 mlx5_reclaim_startup_pages(dev);
1086 err_disable_hca:
1087 mlx5_core_disable_hca(dev, 0);
1088 err_cmd_cleanup:
1089 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN);
1090 mlx5_cmd_cleanup(dev);
1091
1092 return err;
1093 }
1094
mlx5_function_teardown(struct mlx5_core_dev * dev,bool boot)1095 static int mlx5_function_teardown(struct mlx5_core_dev *dev, bool boot)
1096 {
1097 int err;
1098
1099 mlx5_stop_health_poll(dev, boot);
1100 err = mlx5_cmd_teardown_hca(dev);
1101 if (err) {
1102 mlx5_core_err(dev, "tear_down_hca failed, skip cleanup\n");
1103 return err;
1104 }
1105 mlx5_reclaim_startup_pages(dev);
1106 mlx5_core_disable_hca(dev, 0);
1107 mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN);
1108 mlx5_cmd_cleanup(dev);
1109
1110 return 0;
1111 }
1112
mlx5_load(struct mlx5_core_dev * dev)1113 static int mlx5_load(struct mlx5_core_dev *dev)
1114 {
1115 int err;
1116
1117 dev->priv.uar = mlx5_get_uars_page(dev);
1118 if (IS_ERR(dev->priv.uar)) {
1119 mlx5_core_err(dev, "Failed allocating uar, aborting\n");
1120 err = PTR_ERR(dev->priv.uar);
1121 return err;
1122 }
1123
1124 mlx5_events_start(dev);
1125 mlx5_pagealloc_start(dev);
1126
1127 err = mlx5_irq_table_create(dev);
1128 if (err) {
1129 mlx5_core_err(dev, "Failed to alloc IRQs\n");
1130 goto err_irq_table;
1131 }
1132
1133 err = mlx5_eq_table_create(dev);
1134 if (err) {
1135 mlx5_core_err(dev, "Failed to create EQs\n");
1136 goto err_eq_table;
1137 }
1138
1139 err = mlx5_fw_tracer_init(dev->tracer);
1140 if (err) {
1141 mlx5_core_err(dev, "Failed to init FW tracer %d\n", err);
1142 mlx5_fw_tracer_destroy(dev->tracer);
1143 dev->tracer = NULL;
1144 }
1145
1146 mlx5_fw_reset_events_start(dev);
1147 mlx5_hv_vhca_init(dev->hv_vhca);
1148
1149 err = mlx5_rsc_dump_init(dev);
1150 if (err) {
1151 mlx5_core_err(dev, "Failed to init Resource dump %d\n", err);
1152 mlx5_rsc_dump_destroy(dev);
1153 dev->rsc_dump = NULL;
1154 }
1155
1156 err = mlx5_fpga_device_start(dev);
1157 if (err) {
1158 mlx5_core_err(dev, "fpga device start failed %d\n", err);
1159 goto err_fpga_start;
1160 }
1161
1162 mlx5_accel_ipsec_init(dev);
1163
1164 err = mlx5_accel_tls_init(dev);
1165 if (err) {
1166 mlx5_core_err(dev, "TLS device start failed %d\n", err);
1167 goto err_tls_start;
1168 }
1169
1170 err = mlx5_init_fs(dev);
1171 if (err) {
1172 mlx5_core_err(dev, "Failed to init flow steering\n");
1173 goto err_fs;
1174 }
1175
1176 err = mlx5_core_set_hca_defaults(dev);
1177 if (err) {
1178 mlx5_core_err(dev, "Failed to set hca defaults\n");
1179 goto err_set_hca;
1180 }
1181
1182 mlx5_vhca_event_start(dev);
1183
1184 err = mlx5_sf_hw_table_create(dev);
1185 if (err) {
1186 mlx5_core_err(dev, "sf table create failed %d\n", err);
1187 goto err_vhca;
1188 }
1189
1190 err = mlx5_ec_init(dev);
1191 if (err) {
1192 mlx5_core_err(dev, "Failed to init embedded CPU\n");
1193 goto err_ec;
1194 }
1195
1196 mlx5_lag_add_mdev(dev);
1197 err = mlx5_sriov_attach(dev);
1198 if (err) {
1199 mlx5_core_err(dev, "sriov init failed %d\n", err);
1200 goto err_sriov;
1201 }
1202
1203 mlx5_sf_dev_table_create(dev);
1204
1205 return 0;
1206
1207 err_sriov:
1208 mlx5_lag_remove_mdev(dev);
1209 mlx5_ec_cleanup(dev);
1210 err_ec:
1211 mlx5_sf_hw_table_destroy(dev);
1212 err_vhca:
1213 mlx5_vhca_event_stop(dev);
1214 err_set_hca:
1215 mlx5_cleanup_fs(dev);
1216 err_fs:
1217 mlx5_accel_tls_cleanup(dev);
1218 err_tls_start:
1219 mlx5_accel_ipsec_cleanup(dev);
1220 mlx5_fpga_device_stop(dev);
1221 err_fpga_start:
1222 mlx5_rsc_dump_cleanup(dev);
1223 mlx5_hv_vhca_cleanup(dev->hv_vhca);
1224 mlx5_fw_reset_events_stop(dev);
1225 mlx5_fw_tracer_cleanup(dev->tracer);
1226 mlx5_eq_table_destroy(dev);
1227 err_eq_table:
1228 mlx5_irq_table_destroy(dev);
1229 err_irq_table:
1230 mlx5_pagealloc_stop(dev);
1231 mlx5_events_stop(dev);
1232 mlx5_put_uars_page(dev, dev->priv.uar);
1233 return err;
1234 }
1235
mlx5_unload(struct mlx5_core_dev * dev)1236 static void mlx5_unload(struct mlx5_core_dev *dev)
1237 {
1238 mlx5_sf_dev_table_destroy(dev);
1239 mlx5_sriov_detach(dev);
1240 mlx5_lag_remove_mdev(dev);
1241 mlx5_ec_cleanup(dev);
1242 mlx5_sf_hw_table_destroy(dev);
1243 mlx5_vhca_event_stop(dev);
1244 mlx5_cleanup_fs(dev);
1245 mlx5_accel_ipsec_cleanup(dev);
1246 mlx5_accel_tls_cleanup(dev);
1247 mlx5_fpga_device_stop(dev);
1248 mlx5_rsc_dump_cleanup(dev);
1249 mlx5_hv_vhca_cleanup(dev->hv_vhca);
1250 mlx5_fw_reset_events_stop(dev);
1251 mlx5_fw_tracer_cleanup(dev->tracer);
1252 mlx5_eq_table_destroy(dev);
1253 mlx5_irq_table_destroy(dev);
1254 mlx5_pagealloc_stop(dev);
1255 mlx5_events_stop(dev);
1256 mlx5_put_uars_page(dev, dev->priv.uar);
1257 }
1258
mlx5_init_one(struct mlx5_core_dev * dev)1259 int mlx5_init_one(struct mlx5_core_dev *dev)
1260 {
1261 int err = 0;
1262
1263 mutex_lock(&dev->intf_state_mutex);
1264 dev->state = MLX5_DEVICE_STATE_UP;
1265
1266 err = mlx5_function_setup(dev, true);
1267 if (err)
1268 goto err_function;
1269
1270 err = mlx5_init_once(dev);
1271 if (err) {
1272 mlx5_core_err(dev, "sw objs init failed\n");
1273 goto function_teardown;
1274 }
1275
1276 err = mlx5_load(dev);
1277 if (err)
1278 goto err_load;
1279
1280 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1281
1282 err = mlx5_devlink_register(priv_to_devlink(dev));
1283 if (err)
1284 goto err_devlink_reg;
1285
1286 err = mlx5_register_device(dev);
1287 if (err)
1288 goto err_register;
1289
1290 mutex_unlock(&dev->intf_state_mutex);
1291 return 0;
1292
1293 err_register:
1294 mlx5_devlink_unregister(priv_to_devlink(dev));
1295 err_devlink_reg:
1296 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1297 mlx5_unload(dev);
1298 err_load:
1299 mlx5_cleanup_once(dev);
1300 function_teardown:
1301 mlx5_function_teardown(dev, true);
1302 err_function:
1303 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1304 mutex_unlock(&dev->intf_state_mutex);
1305 return err;
1306 }
1307
mlx5_uninit_one(struct mlx5_core_dev * dev)1308 void mlx5_uninit_one(struct mlx5_core_dev *dev)
1309 {
1310 mutex_lock(&dev->intf_state_mutex);
1311
1312 mlx5_unregister_device(dev);
1313 mlx5_devlink_unregister(priv_to_devlink(dev));
1314
1315 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1316 mlx5_core_warn(dev, "%s: interface is down, NOP\n",
1317 __func__);
1318 mlx5_cleanup_once(dev);
1319 goto out;
1320 }
1321
1322 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1323 mlx5_unload(dev);
1324 mlx5_cleanup_once(dev);
1325 mlx5_function_teardown(dev, true);
1326 out:
1327 mutex_unlock(&dev->intf_state_mutex);
1328 }
1329
mlx5_load_one(struct mlx5_core_dev * dev)1330 int mlx5_load_one(struct mlx5_core_dev *dev)
1331 {
1332 int err = 0;
1333
1334 mutex_lock(&dev->intf_state_mutex);
1335 if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1336 mlx5_core_warn(dev, "interface is up, NOP\n");
1337 goto out;
1338 }
1339 /* remove any previous indication of internal error */
1340 dev->state = MLX5_DEVICE_STATE_UP;
1341
1342 err = mlx5_function_setup(dev, false);
1343 if (err)
1344 goto err_function;
1345
1346 err = mlx5_load(dev);
1347 if (err)
1348 goto err_load;
1349
1350 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1351
1352 err = mlx5_attach_device(dev);
1353 if (err)
1354 goto err_attach;
1355
1356 mutex_unlock(&dev->intf_state_mutex);
1357 return 0;
1358
1359 err_attach:
1360 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1361 mlx5_unload(dev);
1362 err_load:
1363 mlx5_function_teardown(dev, false);
1364 err_function:
1365 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1366 out:
1367 mutex_unlock(&dev->intf_state_mutex);
1368 return err;
1369 }
1370
mlx5_unload_one(struct mlx5_core_dev * dev)1371 void mlx5_unload_one(struct mlx5_core_dev *dev)
1372 {
1373 mutex_lock(&dev->intf_state_mutex);
1374
1375 mlx5_detach_device(dev);
1376
1377 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1378 mlx5_core_warn(dev, "%s: interface is down, NOP\n",
1379 __func__);
1380 goto out;
1381 }
1382
1383 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1384 mlx5_unload(dev);
1385 mlx5_function_teardown(dev, false);
1386 out:
1387 mutex_unlock(&dev->intf_state_mutex);
1388 }
1389
1390 static const int types[] = {
1391 MLX5_CAP_GENERAL,
1392 MLX5_CAP_GENERAL_2,
1393 MLX5_CAP_ETHERNET_OFFLOADS,
1394 MLX5_CAP_IPOIB_ENHANCED_OFFLOADS,
1395 MLX5_CAP_ODP,
1396 MLX5_CAP_ATOMIC,
1397 MLX5_CAP_ROCE,
1398 MLX5_CAP_IPOIB_OFFLOADS,
1399 MLX5_CAP_FLOW_TABLE,
1400 MLX5_CAP_ESWITCH_FLOW_TABLE,
1401 MLX5_CAP_ESWITCH,
1402 MLX5_CAP_VECTOR_CALC,
1403 MLX5_CAP_QOS,
1404 MLX5_CAP_DEBUG,
1405 MLX5_CAP_DEV_MEM,
1406 MLX5_CAP_DEV_EVENT,
1407 MLX5_CAP_TLS,
1408 MLX5_CAP_VDPA_EMULATION,
1409 MLX5_CAP_IPSEC,
1410 MLX5_CAP_PORT_SELECTION,
1411 MLX5_CAP_DEV_SHAMPO,
1412 };
1413
mlx5_hca_caps_free(struct mlx5_core_dev * dev)1414 static void mlx5_hca_caps_free(struct mlx5_core_dev *dev)
1415 {
1416 int type;
1417 int i;
1418
1419 for (i = 0; i < ARRAY_SIZE(types); i++) {
1420 type = types[i];
1421 kfree(dev->caps.hca[type]);
1422 }
1423 }
1424
mlx5_hca_caps_alloc(struct mlx5_core_dev * dev)1425 static int mlx5_hca_caps_alloc(struct mlx5_core_dev *dev)
1426 {
1427 struct mlx5_hca_cap *cap;
1428 int type;
1429 int i;
1430
1431 for (i = 0; i < ARRAY_SIZE(types); i++) {
1432 cap = kzalloc(sizeof(*cap), GFP_KERNEL);
1433 if (!cap)
1434 goto err;
1435 type = types[i];
1436 dev->caps.hca[type] = cap;
1437 }
1438
1439 return 0;
1440
1441 err:
1442 mlx5_hca_caps_free(dev);
1443 return -ENOMEM;
1444 }
1445
mlx5_mdev_init(struct mlx5_core_dev * dev,int profile_idx)1446 int mlx5_mdev_init(struct mlx5_core_dev *dev, int profile_idx)
1447 {
1448 struct mlx5_priv *priv = &dev->priv;
1449 int err;
1450
1451 memcpy(&dev->profile, &profile[profile_idx], sizeof(dev->profile));
1452 INIT_LIST_HEAD(&priv->ctx_list);
1453 spin_lock_init(&priv->ctx_lock);
1454 mutex_init(&dev->intf_state_mutex);
1455
1456 mutex_init(&priv->bfregs.reg_head.lock);
1457 mutex_init(&priv->bfregs.wc_head.lock);
1458 INIT_LIST_HEAD(&priv->bfregs.reg_head.list);
1459 INIT_LIST_HEAD(&priv->bfregs.wc_head.list);
1460
1461 mutex_init(&priv->alloc_mutex);
1462 mutex_init(&priv->pgdir_mutex);
1463 INIT_LIST_HEAD(&priv->pgdir_list);
1464
1465 priv->numa_node = dev_to_node(mlx5_core_dma_dev(dev));
1466 priv->dbg_root = debugfs_create_dir(dev_name(dev->device),
1467 mlx5_debugfs_root);
1468 INIT_LIST_HEAD(&priv->traps);
1469
1470 err = mlx5_tout_init(dev);
1471 if (err) {
1472 mlx5_core_err(dev, "Failed initializing timeouts, aborting\n");
1473 goto err_timeout_init;
1474 }
1475
1476 err = mlx5_health_init(dev);
1477 if (err)
1478 goto err_health_init;
1479
1480 err = mlx5_pagealloc_init(dev);
1481 if (err)
1482 goto err_pagealloc_init;
1483
1484 err = mlx5_adev_init(dev);
1485 if (err)
1486 goto err_adev_init;
1487
1488 err = mlx5_hca_caps_alloc(dev);
1489 if (err)
1490 goto err_hca_caps;
1491
1492 return 0;
1493
1494 err_hca_caps:
1495 mlx5_adev_cleanup(dev);
1496 err_adev_init:
1497 mlx5_pagealloc_cleanup(dev);
1498 err_pagealloc_init:
1499 mlx5_health_cleanup(dev);
1500 err_health_init:
1501 mlx5_tout_cleanup(dev);
1502 err_timeout_init:
1503 debugfs_remove(dev->priv.dbg_root);
1504 mutex_destroy(&priv->pgdir_mutex);
1505 mutex_destroy(&priv->alloc_mutex);
1506 mutex_destroy(&priv->bfregs.wc_head.lock);
1507 mutex_destroy(&priv->bfregs.reg_head.lock);
1508 mutex_destroy(&dev->intf_state_mutex);
1509 return err;
1510 }
1511
mlx5_mdev_uninit(struct mlx5_core_dev * dev)1512 void mlx5_mdev_uninit(struct mlx5_core_dev *dev)
1513 {
1514 struct mlx5_priv *priv = &dev->priv;
1515
1516 mlx5_hca_caps_free(dev);
1517 mlx5_adev_cleanup(dev);
1518 mlx5_pagealloc_cleanup(dev);
1519 mlx5_health_cleanup(dev);
1520 mlx5_tout_cleanup(dev);
1521 debugfs_remove_recursive(dev->priv.dbg_root);
1522 mutex_destroy(&priv->pgdir_mutex);
1523 mutex_destroy(&priv->alloc_mutex);
1524 mutex_destroy(&priv->bfregs.wc_head.lock);
1525 mutex_destroy(&priv->bfregs.reg_head.lock);
1526 mutex_destroy(&dev->intf_state_mutex);
1527 }
1528
probe_one(struct pci_dev * pdev,const struct pci_device_id * id)1529 static int probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1530 {
1531 struct mlx5_core_dev *dev;
1532 struct devlink *devlink;
1533 int err;
1534
1535 devlink = mlx5_devlink_alloc(&pdev->dev);
1536 if (!devlink) {
1537 dev_err(&pdev->dev, "devlink alloc failed\n");
1538 return -ENOMEM;
1539 }
1540
1541 dev = devlink_priv(devlink);
1542 dev->device = &pdev->dev;
1543 dev->pdev = pdev;
1544
1545 dev->coredev_type = id->driver_data & MLX5_PCI_DEV_IS_VF ?
1546 MLX5_COREDEV_VF : MLX5_COREDEV_PF;
1547
1548 dev->priv.adev_idx = mlx5_adev_idx_alloc();
1549 if (dev->priv.adev_idx < 0) {
1550 err = dev->priv.adev_idx;
1551 goto adev_init_err;
1552 }
1553
1554 err = mlx5_mdev_init(dev, prof_sel);
1555 if (err)
1556 goto mdev_init_err;
1557
1558 err = mlx5_pci_init(dev, pdev, id);
1559 if (err) {
1560 mlx5_core_err(dev, "mlx5_pci_init failed with error code %d\n",
1561 err);
1562 goto pci_init_err;
1563 }
1564
1565 err = mlx5_init_one(dev);
1566 if (err) {
1567 mlx5_core_err(dev, "mlx5_init_one failed with error code %d\n",
1568 err);
1569 goto err_init_one;
1570 }
1571
1572 err = mlx5_crdump_enable(dev);
1573 if (err)
1574 dev_err(&pdev->dev, "mlx5_crdump_enable failed with error code %d\n", err);
1575
1576 pci_save_state(pdev);
1577 devlink_register(devlink);
1578 return 0;
1579
1580 err_init_one:
1581 mlx5_pci_close(dev);
1582 pci_init_err:
1583 mlx5_mdev_uninit(dev);
1584 mdev_init_err:
1585 mlx5_adev_idx_free(dev->priv.adev_idx);
1586 adev_init_err:
1587 mlx5_devlink_free(devlink);
1588
1589 return err;
1590 }
1591
remove_one(struct pci_dev * pdev)1592 static void remove_one(struct pci_dev *pdev)
1593 {
1594 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1595 struct devlink *devlink = priv_to_devlink(dev);
1596
1597 devlink_unregister(devlink);
1598 mlx5_crdump_disable(dev);
1599 mlx5_drain_health_wq(dev);
1600 mlx5_uninit_one(dev);
1601 mlx5_pci_close(dev);
1602 mlx5_mdev_uninit(dev);
1603 mlx5_adev_idx_free(dev->priv.adev_idx);
1604 mlx5_devlink_free(devlink);
1605 }
1606
mlx5_pci_err_detected(struct pci_dev * pdev,pci_channel_state_t state)1607 static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev,
1608 pci_channel_state_t state)
1609 {
1610 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1611
1612 mlx5_core_info(dev, "%s was called\n", __func__);
1613
1614 mlx5_enter_error_state(dev, false);
1615 mlx5_error_sw_reset(dev);
1616 mlx5_unload_one(dev);
1617 mlx5_drain_health_wq(dev);
1618 mlx5_pci_disable_device(dev);
1619
1620 return state == pci_channel_io_perm_failure ?
1621 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
1622 }
1623
1624 /* wait for the device to show vital signs by waiting
1625 * for the health counter to start counting.
1626 */
wait_vital(struct pci_dev * pdev)1627 static int wait_vital(struct pci_dev *pdev)
1628 {
1629 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1630 struct mlx5_core_health *health = &dev->priv.health;
1631 const int niter = 100;
1632 u32 last_count = 0;
1633 u32 count;
1634 int i;
1635
1636 for (i = 0; i < niter; i++) {
1637 count = ioread32be(health->health_counter);
1638 if (count && count != 0xffffffff) {
1639 if (last_count && last_count != count) {
1640 mlx5_core_info(dev,
1641 "wait vital counter value 0x%x after %d iterations\n",
1642 count, i);
1643 return 0;
1644 }
1645 last_count = count;
1646 }
1647 msleep(50);
1648 }
1649
1650 return -ETIMEDOUT;
1651 }
1652
mlx5_pci_slot_reset(struct pci_dev * pdev)1653 static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev)
1654 {
1655 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1656 int err;
1657
1658 mlx5_core_info(dev, "%s was called\n", __func__);
1659
1660 err = mlx5_pci_enable_device(dev);
1661 if (err) {
1662 mlx5_core_err(dev, "%s: mlx5_pci_enable_device failed with error code: %d\n",
1663 __func__, err);
1664 return PCI_ERS_RESULT_DISCONNECT;
1665 }
1666
1667 pci_set_master(pdev);
1668 pci_restore_state(pdev);
1669 pci_save_state(pdev);
1670
1671 if (wait_vital(pdev)) {
1672 mlx5_core_err(dev, "%s: wait_vital timed out\n", __func__);
1673 return PCI_ERS_RESULT_DISCONNECT;
1674 }
1675
1676 return PCI_ERS_RESULT_RECOVERED;
1677 }
1678
mlx5_pci_resume(struct pci_dev * pdev)1679 static void mlx5_pci_resume(struct pci_dev *pdev)
1680 {
1681 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1682 int err;
1683
1684 mlx5_core_info(dev, "%s was called\n", __func__);
1685
1686 err = mlx5_load_one(dev);
1687 if (err)
1688 mlx5_core_err(dev, "%s: mlx5_load_one failed with error code: %d\n",
1689 __func__, err);
1690 else
1691 mlx5_core_info(dev, "%s: device recovered\n", __func__);
1692 }
1693
1694 static const struct pci_error_handlers mlx5_err_handler = {
1695 .error_detected = mlx5_pci_err_detected,
1696 .slot_reset = mlx5_pci_slot_reset,
1697 .resume = mlx5_pci_resume
1698 };
1699
mlx5_try_fast_unload(struct mlx5_core_dev * dev)1700 static int mlx5_try_fast_unload(struct mlx5_core_dev *dev)
1701 {
1702 bool fast_teardown = false, force_teardown = false;
1703 int ret = 1;
1704
1705 fast_teardown = MLX5_CAP_GEN(dev, fast_teardown);
1706 force_teardown = MLX5_CAP_GEN(dev, force_teardown);
1707
1708 mlx5_core_dbg(dev, "force teardown firmware support=%d\n", force_teardown);
1709 mlx5_core_dbg(dev, "fast teardown firmware support=%d\n", fast_teardown);
1710
1711 if (!fast_teardown && !force_teardown)
1712 return -EOPNOTSUPP;
1713
1714 if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1715 mlx5_core_dbg(dev, "Device in internal error state, giving up\n");
1716 return -EAGAIN;
1717 }
1718
1719 /* Panic tear down fw command will stop the PCI bus communication
1720 * with the HCA, so the health polll is no longer needed.
1721 */
1722 mlx5_drain_health_wq(dev);
1723 mlx5_stop_health_poll(dev, false);
1724
1725 ret = mlx5_cmd_fast_teardown_hca(dev);
1726 if (!ret)
1727 goto succeed;
1728
1729 ret = mlx5_cmd_force_teardown_hca(dev);
1730 if (!ret)
1731 goto succeed;
1732
1733 mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", ret);
1734 mlx5_start_health_poll(dev);
1735 return ret;
1736
1737 succeed:
1738 mlx5_enter_error_state(dev, true);
1739
1740 /* Some platforms requiring freeing the IRQ's in the shutdown
1741 * flow. If they aren't freed they can't be allocated after
1742 * kexec. There is no need to cleanup the mlx5_core software
1743 * contexts.
1744 */
1745 mlx5_core_eq_free_irqs(dev);
1746
1747 return 0;
1748 }
1749
shutdown(struct pci_dev * pdev)1750 static void shutdown(struct pci_dev *pdev)
1751 {
1752 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1753 int err;
1754
1755 mlx5_core_info(dev, "Shutdown was called\n");
1756 err = mlx5_try_fast_unload(dev);
1757 if (err)
1758 mlx5_unload_one(dev);
1759 mlx5_pci_disable_device(dev);
1760 }
1761
mlx5_suspend(struct pci_dev * pdev,pm_message_t state)1762 static int mlx5_suspend(struct pci_dev *pdev, pm_message_t state)
1763 {
1764 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1765
1766 mlx5_unload_one(dev);
1767
1768 return 0;
1769 }
1770
mlx5_resume(struct pci_dev * pdev)1771 static int mlx5_resume(struct pci_dev *pdev)
1772 {
1773 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1774
1775 return mlx5_load_one(dev);
1776 }
1777
1778 static const struct pci_device_id mlx5_core_pci_table[] = {
1779 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTIB) },
1780 { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */
1781 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4) },
1782 { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */
1783 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) },
1784 { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */
1785 { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */
1786 { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */
1787 { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5 Ex */
1788 { PCI_VDEVICE(MELLANOX, 0x101a), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 Ex VF */
1789 { PCI_VDEVICE(MELLANOX, 0x101b) }, /* ConnectX-6 */
1790 { PCI_VDEVICE(MELLANOX, 0x101c), MLX5_PCI_DEV_IS_VF}, /* ConnectX-6 VF */
1791 { PCI_VDEVICE(MELLANOX, 0x101d) }, /* ConnectX-6 Dx */
1792 { PCI_VDEVICE(MELLANOX, 0x101e), MLX5_PCI_DEV_IS_VF}, /* ConnectX Family mlx5Gen Virtual Function */
1793 { PCI_VDEVICE(MELLANOX, 0x101f) }, /* ConnectX-6 LX */
1794 { PCI_VDEVICE(MELLANOX, 0x1021) }, /* ConnectX-7 */
1795 { PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */
1796 { PCI_VDEVICE(MELLANOX, 0xa2d3), MLX5_PCI_DEV_IS_VF}, /* BlueField integrated ConnectX-5 network controller VF */
1797 { PCI_VDEVICE(MELLANOX, 0xa2d6) }, /* BlueField-2 integrated ConnectX-6 Dx network controller */
1798 { PCI_VDEVICE(MELLANOX, 0xa2dc) }, /* BlueField-3 integrated ConnectX-7 network controller */
1799 { 0, }
1800 };
1801
1802 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
1803
mlx5_disable_device(struct mlx5_core_dev * dev)1804 void mlx5_disable_device(struct mlx5_core_dev *dev)
1805 {
1806 mlx5_error_sw_reset(dev);
1807 mlx5_unload_one(dev);
1808 }
1809
mlx5_recover_device(struct mlx5_core_dev * dev)1810 int mlx5_recover_device(struct mlx5_core_dev *dev)
1811 {
1812 if (!mlx5_core_is_sf(dev)) {
1813 mlx5_pci_disable_device(dev);
1814 if (mlx5_pci_slot_reset(dev->pdev) != PCI_ERS_RESULT_RECOVERED)
1815 return -EIO;
1816 }
1817
1818 return mlx5_load_one(dev);
1819 }
1820
1821 static struct pci_driver mlx5_core_driver = {
1822 .name = KBUILD_MODNAME,
1823 .id_table = mlx5_core_pci_table,
1824 .probe = probe_one,
1825 .remove = remove_one,
1826 .suspend = mlx5_suspend,
1827 .resume = mlx5_resume,
1828 .shutdown = shutdown,
1829 .err_handler = &mlx5_err_handler,
1830 .sriov_configure = mlx5_core_sriov_configure,
1831 .sriov_get_vf_total_msix = mlx5_sriov_get_vf_total_msix,
1832 .sriov_set_msix_vec_count = mlx5_core_sriov_set_msix_vec_count,
1833 };
1834
mlx5_core_verify_params(void)1835 static void mlx5_core_verify_params(void)
1836 {
1837 if (prof_sel >= ARRAY_SIZE(profile)) {
1838 pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n",
1839 prof_sel,
1840 ARRAY_SIZE(profile) - 1,
1841 MLX5_DEFAULT_PROF);
1842 prof_sel = MLX5_DEFAULT_PROF;
1843 }
1844 }
1845
init(void)1846 static int __init init(void)
1847 {
1848 int err;
1849
1850 WARN_ONCE(strcmp(MLX5_ADEV_NAME, KBUILD_MODNAME),
1851 "mlx5_core name not in sync with kernel module name");
1852
1853 get_random_bytes(&sw_owner_id, sizeof(sw_owner_id));
1854
1855 mlx5_core_verify_params();
1856 mlx5_fpga_ipsec_build_fs_cmds();
1857 mlx5_register_debugfs();
1858
1859 err = pci_register_driver(&mlx5_core_driver);
1860 if (err)
1861 goto err_debug;
1862
1863 err = mlx5_sf_driver_register();
1864 if (err)
1865 goto err_sf;
1866
1867 err = mlx5e_init();
1868 if (err)
1869 goto err_en;
1870
1871 return 0;
1872
1873 err_en:
1874 mlx5_sf_driver_unregister();
1875 err_sf:
1876 pci_unregister_driver(&mlx5_core_driver);
1877 err_debug:
1878 mlx5_unregister_debugfs();
1879 return err;
1880 }
1881
cleanup(void)1882 static void __exit cleanup(void)
1883 {
1884 mlx5e_cleanup();
1885 mlx5_sf_driver_unregister();
1886 pci_unregister_driver(&mlx5_core_driver);
1887 mlx5_unregister_debugfs();
1888 }
1889
1890 module_init(init);
1891 module_exit(cleanup);
1892