1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */
2 /* Copyright (c) 2016-2018 Mellanox Technologies. All rights reserved */
3
4 #ifndef _MLXSW_RESOURCES_H
5 #define _MLXSW_RESOURCES_H
6
7 #include <linux/kernel.h>
8 #include <linux/types.h>
9
10 enum mlxsw_res_id {
11 MLXSW_RES_ID_KVD_SIZE,
12 MLXSW_RES_ID_KVD_SINGLE_MIN_SIZE,
13 MLXSW_RES_ID_KVD_DOUBLE_MIN_SIZE,
14 MLXSW_RES_ID_MAX_KVD_LINEAR_RANGE,
15 MLXSW_RES_ID_MAX_KVD_ACTION_SETS,
16 MLXSW_RES_ID_MAX_TRAP_GROUPS,
17 MLXSW_RES_ID_CQE_V0,
18 MLXSW_RES_ID_CQE_V1,
19 MLXSW_RES_ID_CQE_V2,
20 MLXSW_RES_ID_COUNTER_POOL_SIZE,
21 MLXSW_RES_ID_COUNTER_BANK_SIZE,
22 MLXSW_RES_ID_MAX_SPAN,
23 MLXSW_RES_ID_COUNTER_SIZE_PACKETS_BYTES,
24 MLXSW_RES_ID_COUNTER_SIZE_ROUTER_BASIC,
25 MLXSW_RES_ID_MAX_SYSTEM_PORT,
26 MLXSW_RES_ID_MAX_LAG,
27 MLXSW_RES_ID_MAX_LAG_MEMBERS,
28 MLXSW_RES_ID_GUARANTEED_SHARED_BUFFER,
29 MLXSW_RES_ID_CELL_SIZE,
30 MLXSW_RES_ID_MAX_HEADROOM_SIZE,
31 MLXSW_RES_ID_ACL_MAX_TCAM_REGIONS,
32 MLXSW_RES_ID_ACL_MAX_TCAM_RULES,
33 MLXSW_RES_ID_ACL_MAX_REGIONS,
34 MLXSW_RES_ID_ACL_MAX_GROUPS,
35 MLXSW_RES_ID_ACL_MAX_GROUP_SIZE,
36 MLXSW_RES_ID_ACL_FLEX_KEYS,
37 MLXSW_RES_ID_ACL_MAX_ACTION_PER_RULE,
38 MLXSW_RES_ID_ACL_ACTIONS_PER_SET,
39 MLXSW_RES_ID_ACL_MAX_ERPT_BANKS,
40 MLXSW_RES_ID_ACL_MAX_ERPT_BANK_SIZE,
41 MLXSW_RES_ID_ACL_MAX_LARGE_KEY_ID,
42 MLXSW_RES_ID_ACL_ERPT_ENTRIES_2KB,
43 MLXSW_RES_ID_ACL_ERPT_ENTRIES_4KB,
44 MLXSW_RES_ID_ACL_ERPT_ENTRIES_8KB,
45 MLXSW_RES_ID_ACL_ERPT_ENTRIES_12KB,
46 MLXSW_RES_ID_ACL_MAX_BF_LOG,
47 MLXSW_RES_ID_MAX_GLOBAL_POLICERS,
48 MLXSW_RES_ID_MAX_CPU_POLICERS,
49 MLXSW_RES_ID_MAX_VRS,
50 MLXSW_RES_ID_MAX_RIFS,
51 MLXSW_RES_ID_MC_ERIF_LIST_ENTRIES,
52 MLXSW_RES_ID_MAX_RIF_MAC_PROFILES,
53 MLXSW_RES_ID_MAX_LPM_TREES,
54 MLXSW_RES_ID_MAX_NVE_MC_ENTRIES_IPV4,
55 MLXSW_RES_ID_MAX_NVE_MC_ENTRIES_IPV6,
56
57 /* Internal resources.
58 * Determined by the SW, not queried from the HW.
59 */
60 MLXSW_RES_ID_KVD_SINGLE_SIZE,
61 MLXSW_RES_ID_KVD_DOUBLE_SIZE,
62 MLXSW_RES_ID_KVD_LINEAR_SIZE,
63
64 __MLXSW_RES_ID_MAX,
65 };
66
67 static u16 mlxsw_res_ids[] = {
68 [MLXSW_RES_ID_KVD_SIZE] = 0x1001,
69 [MLXSW_RES_ID_KVD_SINGLE_MIN_SIZE] = 0x1002,
70 [MLXSW_RES_ID_KVD_DOUBLE_MIN_SIZE] = 0x1003,
71 [MLXSW_RES_ID_MAX_KVD_LINEAR_RANGE] = 0x1005,
72 [MLXSW_RES_ID_MAX_KVD_ACTION_SETS] = 0x1007,
73 [MLXSW_RES_ID_MAX_TRAP_GROUPS] = 0x2201,
74 [MLXSW_RES_ID_CQE_V0] = 0x2210,
75 [MLXSW_RES_ID_CQE_V1] = 0x2211,
76 [MLXSW_RES_ID_CQE_V2] = 0x2212,
77 [MLXSW_RES_ID_COUNTER_POOL_SIZE] = 0x2410,
78 [MLXSW_RES_ID_COUNTER_BANK_SIZE] = 0x2411,
79 [MLXSW_RES_ID_MAX_SPAN] = 0x2420,
80 [MLXSW_RES_ID_COUNTER_SIZE_PACKETS_BYTES] = 0x2443,
81 [MLXSW_RES_ID_COUNTER_SIZE_ROUTER_BASIC] = 0x2449,
82 [MLXSW_RES_ID_MAX_SYSTEM_PORT] = 0x2502,
83 [MLXSW_RES_ID_MAX_LAG] = 0x2520,
84 [MLXSW_RES_ID_MAX_LAG_MEMBERS] = 0x2521,
85 [MLXSW_RES_ID_GUARANTEED_SHARED_BUFFER] = 0x2805, /* Bytes */
86 [MLXSW_RES_ID_CELL_SIZE] = 0x2803, /* Bytes */
87 [MLXSW_RES_ID_MAX_HEADROOM_SIZE] = 0x2811, /* Bytes */
88 [MLXSW_RES_ID_ACL_MAX_TCAM_REGIONS] = 0x2901,
89 [MLXSW_RES_ID_ACL_MAX_TCAM_RULES] = 0x2902,
90 [MLXSW_RES_ID_ACL_MAX_REGIONS] = 0x2903,
91 [MLXSW_RES_ID_ACL_MAX_GROUPS] = 0x2904,
92 [MLXSW_RES_ID_ACL_MAX_GROUP_SIZE] = 0x2905,
93 [MLXSW_RES_ID_ACL_FLEX_KEYS] = 0x2910,
94 [MLXSW_RES_ID_ACL_MAX_ACTION_PER_RULE] = 0x2911,
95 [MLXSW_RES_ID_ACL_ACTIONS_PER_SET] = 0x2912,
96 [MLXSW_RES_ID_ACL_MAX_ERPT_BANKS] = 0x2940,
97 [MLXSW_RES_ID_ACL_MAX_ERPT_BANK_SIZE] = 0x2941,
98 [MLXSW_RES_ID_ACL_MAX_LARGE_KEY_ID] = 0x2942,
99 [MLXSW_RES_ID_ACL_ERPT_ENTRIES_2KB] = 0x2950,
100 [MLXSW_RES_ID_ACL_ERPT_ENTRIES_4KB] = 0x2951,
101 [MLXSW_RES_ID_ACL_ERPT_ENTRIES_8KB] = 0x2952,
102 [MLXSW_RES_ID_ACL_ERPT_ENTRIES_12KB] = 0x2953,
103 [MLXSW_RES_ID_ACL_MAX_BF_LOG] = 0x2960,
104 [MLXSW_RES_ID_MAX_GLOBAL_POLICERS] = 0x2A10,
105 [MLXSW_RES_ID_MAX_CPU_POLICERS] = 0x2A13,
106 [MLXSW_RES_ID_MAX_VRS] = 0x2C01,
107 [MLXSW_RES_ID_MAX_RIFS] = 0x2C02,
108 [MLXSW_RES_ID_MC_ERIF_LIST_ENTRIES] = 0x2C10,
109 [MLXSW_RES_ID_MAX_RIF_MAC_PROFILES] = 0x2C14,
110 [MLXSW_RES_ID_MAX_LPM_TREES] = 0x2C30,
111 [MLXSW_RES_ID_MAX_NVE_MC_ENTRIES_IPV4] = 0x2E02,
112 [MLXSW_RES_ID_MAX_NVE_MC_ENTRIES_IPV6] = 0x2E03,
113 };
114
115 struct mlxsw_res {
116 bool valid[__MLXSW_RES_ID_MAX];
117 u64 values[__MLXSW_RES_ID_MAX];
118 };
119
mlxsw_res_valid(struct mlxsw_res * res,enum mlxsw_res_id res_id)120 static inline bool mlxsw_res_valid(struct mlxsw_res *res,
121 enum mlxsw_res_id res_id)
122 {
123 return res->valid[res_id];
124 }
125
126 #define MLXSW_RES_VALID(res, short_res_id) \
127 mlxsw_res_valid(res, MLXSW_RES_ID_##short_res_id)
128
mlxsw_res_get(struct mlxsw_res * res,enum mlxsw_res_id res_id)129 static inline u64 mlxsw_res_get(struct mlxsw_res *res,
130 enum mlxsw_res_id res_id)
131 {
132 if (WARN_ON(!res->valid[res_id]))
133 return 0;
134 return res->values[res_id];
135 }
136
137 #define MLXSW_RES_GET(res, short_res_id) \
138 mlxsw_res_get(res, MLXSW_RES_ID_##short_res_id)
139
mlxsw_res_set(struct mlxsw_res * res,enum mlxsw_res_id res_id,u64 value)140 static inline void mlxsw_res_set(struct mlxsw_res *res,
141 enum mlxsw_res_id res_id, u64 value)
142 {
143 res->valid[res_id] = true;
144 res->values[res_id] = value;
145 }
146
147 #define MLXSW_RES_SET(res, short_res_id, value) \
148 mlxsw_res_set(res, MLXSW_RES_ID_##short_res_id, value)
149
mlxsw_res_parse(struct mlxsw_res * res,u16 id,u64 value)150 static inline void mlxsw_res_parse(struct mlxsw_res *res, u16 id, u64 value)
151 {
152 int i;
153
154 for (i = 0; i < ARRAY_SIZE(mlxsw_res_ids); i++) {
155 if (mlxsw_res_ids[i] == id) {
156 mlxsw_res_set(res, i, value);
157 return;
158 }
159 }
160 }
161
162 #endif
163