1 // SPDX-License-Identifier: GPL-2.0
2 
3 /* Copyright (C) 2021 Linaro Ltd. */
4 
5 #include <linux/log2.h>
6 
7 #include "gsi.h"
8 #include "ipa_data.h"
9 #include "ipa_endpoint.h"
10 #include "ipa_mem.h"
11 
12 /** enum ipa_resource_type - IPA resource types for an SoC having IPA v4.9 */
13 enum ipa_resource_type {
14 	/* Source resource types; first must have value 0 */
15 	IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS		= 0,
16 	IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS,
17 	IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF,
18 	IPA_RESOURCE_TYPE_SRC_HPS_DMARS,
19 	IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES,
20 
21 	/* Destination resource types; first must have value 0 */
22 	IPA_RESOURCE_TYPE_DST_DATA_SECTORS		= 0,
23 	IPA_RESOURCE_TYPE_DST_DPS_DMARS,
24 };
25 
26 /* Resource groups used for an SoC having IPA v4.9 */
27 enum ipa_rsrc_group_id {
28 	/* Source resource group identifiers */
29 	IPA_RSRC_GROUP_SRC_UL_DL			= 0,
30 	IPA_RSRC_GROUP_SRC_DMA,
31 	IPA_RSRC_GROUP_SRC_UC_RX_Q,
32 	IPA_RSRC_GROUP_SRC_COUNT,	/* Last in set; not a source group */
33 
34 	/* Destination resource group identifiers */
35 	IPA_RSRC_GROUP_DST_UL_DL_DPL			= 0,
36 	IPA_RSRC_GROUP_DST_DMA,
37 	IPA_RSRC_GROUP_DST_UC,
38 	IPA_RSRC_GROUP_DST_DRB_IP,
39 	IPA_RSRC_GROUP_DST_COUNT,	/* Last; not a destination group */
40 };
41 
42 /* QSB configuration data for an SoC having IPA v4.9 */
43 static const struct ipa_qsb_data ipa_qsb_data[] = {
44 	[IPA_QSB_MASTER_DDR] = {
45 		.max_writes		= 8,
46 		.max_reads		= 0,	/* no limit (hardware max) */
47 		.max_reads_beats	= 120,
48 	},
49 };
50 
51 /* Endpoint configuration data for an SoC having IPA v4.9 */
52 static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = {
53 	[IPA_ENDPOINT_AP_COMMAND_TX] = {
54 		.ee_id		= GSI_EE_AP,
55 		.channel_id	= 6,
56 		.endpoint_id	= 7,
57 		.toward_ipa	= true,
58 		.channel = {
59 			.tre_count	= 256,
60 			.event_count	= 256,
61 			.tlv_count	= 20,
62 		},
63 		.endpoint = {
64 			.config = {
65 				.resource_group	= IPA_RSRC_GROUP_SRC_UL_DL,
66 				.dma_mode	= true,
67 				.dma_endpoint	= IPA_ENDPOINT_AP_LAN_RX,
68 				.tx = {
69 					.seq_type = IPA_SEQ_DMA,
70 				},
71 			},
72 		},
73 	},
74 	[IPA_ENDPOINT_AP_LAN_RX] = {
75 		.ee_id		= GSI_EE_AP,
76 		.channel_id	= 7,
77 		.endpoint_id	= 11,
78 		.toward_ipa	= false,
79 		.channel = {
80 			.tre_count	= 256,
81 			.event_count	= 256,
82 			.tlv_count	= 9,
83 		},
84 		.endpoint = {
85 			.config = {
86 				.resource_group	= IPA_RSRC_GROUP_DST_UL_DL_DPL,
87 				.aggregation	= true,
88 				.status_enable	= true,
89 				.rx = {
90 					.pad_align	= ilog2(sizeof(u32)),
91 				},
92 			},
93 		},
94 	},
95 	[IPA_ENDPOINT_AP_MODEM_TX] = {
96 		.ee_id		= GSI_EE_AP,
97 		.channel_id	= 2,
98 		.endpoint_id	= 2,
99 		.toward_ipa	= true,
100 		.channel = {
101 			.tre_count	= 512,
102 			.event_count	= 512,
103 			.tlv_count	= 16,
104 		},
105 		.endpoint = {
106 			.filter_support	= true,
107 			.config = {
108 				.resource_group	= IPA_RSRC_GROUP_SRC_UL_DL,
109 				.checksum       = true,
110 				.qmap		= true,
111 				.status_enable	= true,
112 				.tx = {
113 					.seq_type = IPA_SEQ_2_PASS_SKIP_LAST_UC,
114 					.status_endpoint =
115 						IPA_ENDPOINT_MODEM_AP_RX,
116 				},
117 			},
118 		},
119 	},
120 	[IPA_ENDPOINT_AP_MODEM_RX] = {
121 		.ee_id		= GSI_EE_AP,
122 		.channel_id	= 12,
123 		.endpoint_id	= 20,
124 		.toward_ipa	= false,
125 		.channel = {
126 			.tre_count	= 256,
127 			.event_count	= 256,
128 			.tlv_count	= 9,
129 		},
130 		.endpoint = {
131 			.config = {
132 				.resource_group	= IPA_RSRC_GROUP_DST_UL_DL_DPL,
133 				.checksum       = true,
134 				.qmap		= true,
135 				.aggregation	= true,
136 				.rx = {
137 					.aggr_close_eof	= true,
138 				},
139 			},
140 		},
141 	},
142 	[IPA_ENDPOINT_MODEM_AP_TX] = {
143 		.ee_id		= GSI_EE_MODEM,
144 		.channel_id	= 0,
145 		.endpoint_id	= 5,
146 		.toward_ipa	= true,
147 		.endpoint = {
148 			.filter_support	= true,
149 		},
150 	},
151 	[IPA_ENDPOINT_MODEM_AP_RX] = {
152 		.ee_id		= GSI_EE_MODEM,
153 		.channel_id	= 7,
154 		.endpoint_id	= 16,
155 		.toward_ipa	= false,
156 	},
157 	[IPA_ENDPOINT_MODEM_DL_NLO_TX] = {
158 		.ee_id		= GSI_EE_MODEM,
159 		.channel_id	= 2,
160 		.endpoint_id	= 8,
161 		.toward_ipa	= true,
162 		.endpoint = {
163 			.filter_support	= true,
164 		},
165 	},
166 };
167 
168 /* Source resource configuration data for an SoC having IPA v4.9 */
169 static const struct ipa_resource ipa_resource_src[] = {
170 	[IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS] = {
171 		.limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
172 			.min = 1,	.max = 12,
173 		},
174 		.limits[IPA_RSRC_GROUP_SRC_DMA] = {
175 			.min = 1,	.max = 1,
176 		},
177 		.limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
178 			.min = 1,	.max = 12,
179 		},
180 	},
181 	[IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS] = {
182 		.limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
183 			.min = 20,	.max = 20,
184 		},
185 		.limits[IPA_RSRC_GROUP_SRC_DMA] = {
186 			.min = 2,	.max = 2,
187 		},
188 		.limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
189 			.min = 3,	.max = 3,
190 		},
191 	},
192 	[IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF] = {
193 		.limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
194 			.min = 38,	.max = 38,
195 		},
196 		.limits[IPA_RSRC_GROUP_SRC_DMA] = {
197 			.min = 4,	.max = 4,
198 		},
199 		.limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
200 			.min = 8,	.max = 8,
201 		},
202 	},
203 	[IPA_RESOURCE_TYPE_SRC_HPS_DMARS] = {
204 		.limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
205 			.min = 0,	.max = 4,
206 		},
207 		.limits[IPA_RSRC_GROUP_SRC_DMA] = {
208 			.min = 0,	.max = 4,
209 		},
210 		.limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
211 			.min = 0,	.max = 4,
212 		},
213 	},
214 	[IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES] = {
215 		.limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
216 			.min = 30,	.max = 30,
217 		},
218 		.limits[IPA_RSRC_GROUP_SRC_DMA] = {
219 			.min = 8,	.max = 8,
220 		},
221 		.limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
222 			.min = 8,	.max = 8,
223 		},
224 	},
225 };
226 
227 /* Destination resource configuration data for an SoC having IPA v4.9 */
228 static const struct ipa_resource ipa_resource_dst[] = {
229 	[IPA_RESOURCE_TYPE_DST_DATA_SECTORS] = {
230 		.limits[IPA_RSRC_GROUP_DST_UL_DL_DPL] = {
231 			.min = 9,	.max = 9,
232 		},
233 		.limits[IPA_RSRC_GROUP_DST_DMA] = {
234 			.min = 1,	.max = 1,
235 		},
236 		.limits[IPA_RSRC_GROUP_DST_UC] = {
237 			.min = 1,	.max = 1,
238 		},
239 		.limits[IPA_RSRC_GROUP_DST_DRB_IP] = {
240 			.min = 39,	.max = 39,
241 		},
242 	},
243 	[IPA_RESOURCE_TYPE_DST_DPS_DMARS] = {
244 		.limits[IPA_RSRC_GROUP_DST_UL_DL_DPL] = {
245 			.min = 2,	.max = 3,
246 		},
247 		.limits[IPA_RSRC_GROUP_DST_DMA] = {
248 			.min = 1,	.max = 2,
249 		},
250 		.limits[IPA_RSRC_GROUP_DST_UC] = {
251 			.min = 0,	.max = 2,
252 		},
253 	},
254 };
255 
256 /* Resource configuration data for an SoC having IPA v4.9 */
257 static const struct ipa_resource_data ipa_resource_data = {
258 	.rsrc_group_dst_count	= IPA_RSRC_GROUP_DST_COUNT,
259 	.rsrc_group_src_count	= IPA_RSRC_GROUP_SRC_COUNT,
260 	.resource_src_count	= ARRAY_SIZE(ipa_resource_src),
261 	.resource_src		= ipa_resource_src,
262 	.resource_dst_count	= ARRAY_SIZE(ipa_resource_dst),
263 	.resource_dst		= ipa_resource_dst,
264 };
265 
266 /* IPA-resident memory region data for an SoC having IPA v4.9 */
267 static const struct ipa_mem ipa_mem_local_data[] = {
268 	{
269 		.id		= IPA_MEM_UC_SHARED,
270 		.offset		= 0x0000,
271 		.size		= 0x0080,
272 		.canary_count	= 0,
273 	},
274 	{
275 		.id		= IPA_MEM_UC_INFO,
276 		.offset		= 0x0080,
277 		.size		= 0x0200,
278 		.canary_count	= 0,
279 	},
280 	{
281 		.id		= IPA_MEM_V4_FILTER_HASHED,
282 		.offset		= 0x0288,
283 		.size		= 0x0078,
284 		.canary_count	= 2,
285 	},
286 	{
287 		.id		= IPA_MEM_V4_FILTER,
288 		.offset		= 0x0308,
289 		.size		= 0x0078,
290 		.canary_count	= 2,
291 	},
292 	{
293 		.id		= IPA_MEM_V6_FILTER_HASHED,
294 		.offset		= 0x0388,
295 		.size		= 0x0078,
296 		.canary_count	= 2,
297 	},
298 	{
299 		.id		= IPA_MEM_V6_FILTER,
300 		.offset		= 0x0408,
301 		.size		= 0x0078,
302 		.canary_count	= 2,
303 	},
304 	{
305 		.id		= IPA_MEM_V4_ROUTE_HASHED,
306 		.offset		= 0x0488,
307 		.size		= 0x0078,
308 		.canary_count	= 2,
309 	},
310 	{
311 		.id		= IPA_MEM_V4_ROUTE,
312 		.offset		= 0x0508,
313 		.size		= 0x0078,
314 		.canary_count	= 2,
315 	},
316 	{
317 		.id		= IPA_MEM_V6_ROUTE_HASHED,
318 		.offset		= 0x0588,
319 		.size		= 0x0078,
320 		.canary_count	= 2,
321 	},
322 	{
323 		.id		= IPA_MEM_V6_ROUTE,
324 		.offset		= 0x0608,
325 		.size		= 0x0078,
326 		.canary_count	= 2,
327 	},
328 	{
329 		.id		= IPA_MEM_MODEM_HEADER,
330 		.offset		= 0x0688,
331 		.size		= 0x0240,
332 		.canary_count	= 2,
333 	},
334 	{
335 		.id		= IPA_MEM_AP_HEADER,
336 		.offset		= 0x08c8,
337 		.size		= 0x0200,
338 		.canary_count	= 0,
339 	},
340 	{
341 		.id		= IPA_MEM_MODEM_PROC_CTX,
342 		.offset		= 0x0ad0,
343 		.size		= 0x0b20,
344 		.canary_count	= 2,
345 	},
346 	{
347 		.id		= IPA_MEM_AP_PROC_CTX,
348 		.offset		= 0x15f0,
349 		.size		= 0x0200,
350 		.canary_count	= 0,
351 	},
352 	{
353 		.id		= IPA_MEM_NAT_TABLE,
354 		.offset		= 0x1800,
355 		.size		= 0x0d00,
356 		.canary_count	= 4,
357 	},
358 	{
359 		.id		= IPA_MEM_STATS_QUOTA_MODEM,
360 		.offset		= 0x2510,
361 		.size		= 0x0030,
362 		.canary_count	= 4,
363 	},
364 	{
365 		.id		= IPA_MEM_STATS_QUOTA_AP,
366 		.offset		= 0x2540,
367 		.size		= 0x0048,
368 		.canary_count	= 0,
369 	},
370 	{
371 		.id		= IPA_MEM_STATS_TETHERING,
372 		.offset		= 0x2588,
373 		.size		= 0x0238,
374 		.canary_count	= 0,
375 	},
376 	{
377 		.id		= IPA_MEM_STATS_FILTER_ROUTE,
378 		.offset		= 0x27c0,
379 		.size		= 0x0800,
380 		.canary_count	= 0,
381 	},
382 	{
383 		.id		= IPA_MEM_STATS_DROP,
384 		.offset		= 0x2fc0,
385 		.size		= 0x0020,
386 		.canary_count	= 0,
387 	},
388 	{
389 		.id		= IPA_MEM_MODEM,
390 		.offset		= 0x2fe8,
391 		.size		= 0x0800,
392 		.canary_count	= 2,
393 	},
394 	{
395 		.id		= IPA_MEM_UC_EVENT_RING,
396 		.offset		= 0x3800,
397 		.size		= 0x1000,
398 		.canary_count	= 1,
399 	},
400 	{
401 		.id		= IPA_MEM_PDN_CONFIG,
402 		.offset		= 0x4800,
403 		.size		= 0x0050,
404 		.canary_count	= 0,
405 	},
406 };
407 
408 /* Memory configuration data for an SoC having IPA v4.9 */
409 static const struct ipa_mem_data ipa_mem_data = {
410 	.local_count	= ARRAY_SIZE(ipa_mem_local_data),
411 	.local		= ipa_mem_local_data,
412 	.imem_addr	= 0x146bd000,
413 	.imem_size	= 0x00002000,
414 	.smem_id	= 497,
415 	.smem_size	= 0x00009000,
416 };
417 
418 /* Interconnect rates are in 1000 byte/second units */
419 static const struct ipa_interconnect_data ipa_interconnect_data[] = {
420 	{
421 		.name			= "memory",
422 		.peak_bandwidth		= 600000,	/* 600 MBps */
423 		.average_bandwidth	= 150000,	/* 150 MBps */
424 	},
425 	/* Average rate is unused for the next interconnect */
426 	{
427 		.name			= "config",
428 		.peak_bandwidth		= 74000,	/* 74 MBps */
429 		.average_bandwidth	= 0,		/* unused */
430 	},
431 
432 };
433 
434 /* Clock and interconnect configuration data for an SoC having IPA v4.9 */
435 static const struct ipa_power_data ipa_power_data = {
436 	.core_clock_rate	= 60 * 1000 * 1000,	/* Hz */
437 	.interconnect_count	= ARRAY_SIZE(ipa_interconnect_data),
438 	.interconnect_data	= ipa_interconnect_data,
439 };
440 
441 /* Configuration data for an SoC having IPA v4.9. */
442 const struct ipa_data ipa_data_v4_9 = {
443 	.version	= IPA_VERSION_4_9,
444 	.qsb_count	= ARRAY_SIZE(ipa_qsb_data),
445 	.qsb_data	= ipa_qsb_data,
446 	.endpoint_count	= ARRAY_SIZE(ipa_gsi_endpoint_data),
447 	.endpoint_data	= ipa_gsi_endpoint_data,
448 	.resource_data	= &ipa_resource_data,
449 	.mem_data	= &ipa_mem_data,
450 	.power_data	= &ipa_power_data,
451 };
452