1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2018-2019 Realtek Corporation
3 */
4
5 #ifndef __RTK_MAIN_H_
6 #define __RTK_MAIN_H_
7
8 #include <net/mac80211.h>
9 #include <linux/vmalloc.h>
10 #include <linux/firmware.h>
11 #include <linux/average.h>
12 #include <linux/bitops.h>
13 #include <linux/bitfield.h>
14 #include <linux/iopoll.h>
15 #include <linux/interrupt.h>
16 #include <linux/workqueue.h>
17
18 #include "util.h"
19
20 #define RTW_NAPI_WEIGHT_NUM 64
21 #define RTW_MAX_MAC_ID_NUM 32
22 #define RTW_MAX_SEC_CAM_NUM 32
23 #define MAX_PG_CAM_BACKUP_NUM 8
24
25 #define RTW_MAX_PATTERN_NUM 12
26 #define RTW_MAX_PATTERN_MASK_SIZE 16
27 #define RTW_MAX_PATTERN_SIZE 128
28
29 #define RTW_WATCH_DOG_DELAY_TIME round_jiffies_relative(HZ * 2)
30
31 #define RFREG_MASK 0xfffff
32 #define INV_RF_DATA 0xffffffff
33 #define TX_PAGE_SIZE_SHIFT 7
34
35 #define RTW_CHANNEL_WIDTH_MAX 3
36 #define RTW_RF_PATH_MAX 4
37 #define HW_FEATURE_LEN 13
38
39 #define RTW_TP_SHIFT 18 /* bytes/2s --> Mbps */
40
41 extern bool rtw_bf_support;
42 extern bool rtw_disable_lps_deep_mode;
43 extern unsigned int rtw_debug_mask;
44 extern bool rtw_edcca_enabled;
45 extern const struct ieee80211_ops rtw_ops;
46
47 #define RTW_MAX_CHANNEL_NUM_2G 14
48 #define RTW_MAX_CHANNEL_NUM_5G 49
49
50 struct rtw_dev;
51
52 enum rtw_hci_type {
53 RTW_HCI_TYPE_PCIE,
54 RTW_HCI_TYPE_USB,
55 RTW_HCI_TYPE_SDIO,
56
57 RTW_HCI_TYPE_UNDEFINE,
58 };
59
60 struct rtw_hci {
61 struct rtw_hci_ops *ops;
62 enum rtw_hci_type type;
63
64 u32 rpwm_addr;
65 u32 cpwm_addr;
66
67 u8 bulkout_num;
68 };
69
70 #define IS_CH_5G_BAND_1(channel) ((channel) >= 36 && (channel <= 48))
71 #define IS_CH_5G_BAND_2(channel) ((channel) >= 52 && (channel <= 64))
72 #define IS_CH_5G_BAND_3(channel) ((channel) >= 100 && (channel <= 144))
73 #define IS_CH_5G_BAND_4(channel) ((channel) >= 149 && (channel <= 177))
74
75 #define IS_CH_5G_BAND_MID(channel) \
76 (IS_CH_5G_BAND_2(channel) || IS_CH_5G_BAND_3(channel))
77
78 #define IS_CH_2G_BAND(channel) ((channel) <= 14)
79 #define IS_CH_5G_BAND(channel) \
80 (IS_CH_5G_BAND_1(channel) || IS_CH_5G_BAND_2(channel) || \
81 IS_CH_5G_BAND_3(channel) || IS_CH_5G_BAND_4(channel))
82
83 enum rtw_supported_band {
84 RTW_BAND_2G = 1 << 0,
85 RTW_BAND_5G = 1 << 1,
86 RTW_BAND_60G = 1 << 2,
87
88 RTW_BAND_MAX,
89 };
90
91 /* now, support upto 80M bw */
92 #define RTW_MAX_CHANNEL_WIDTH RTW_CHANNEL_WIDTH_80
93
94 enum rtw_bandwidth {
95 RTW_CHANNEL_WIDTH_20 = 0,
96 RTW_CHANNEL_WIDTH_40 = 1,
97 RTW_CHANNEL_WIDTH_80 = 2,
98 RTW_CHANNEL_WIDTH_160 = 3,
99 RTW_CHANNEL_WIDTH_80_80 = 4,
100 RTW_CHANNEL_WIDTH_5 = 5,
101 RTW_CHANNEL_WIDTH_10 = 6,
102 };
103
104 enum rtw_sc_offset {
105 RTW_SC_DONT_CARE = 0,
106 RTW_SC_20_UPPER = 1,
107 RTW_SC_20_LOWER = 2,
108 RTW_SC_20_UPMOST = 3,
109 RTW_SC_20_LOWEST = 4,
110 RTW_SC_40_UPPER = 9,
111 RTW_SC_40_LOWER = 10,
112 };
113
114 enum rtw_net_type {
115 RTW_NET_NO_LINK = 0,
116 RTW_NET_AD_HOC = 1,
117 RTW_NET_MGD_LINKED = 2,
118 RTW_NET_AP_MODE = 3,
119 };
120
121 enum rtw_rf_type {
122 RF_1T1R = 0,
123 RF_1T2R = 1,
124 RF_2T2R = 2,
125 RF_2T3R = 3,
126 RF_2T4R = 4,
127 RF_3T3R = 5,
128 RF_3T4R = 6,
129 RF_4T4R = 7,
130 RF_TYPE_MAX,
131 };
132
133 enum rtw_rf_path {
134 RF_PATH_A = 0,
135 RF_PATH_B = 1,
136 RF_PATH_C = 2,
137 RF_PATH_D = 3,
138 };
139
140 enum rtw_bb_path {
141 BB_PATH_A = BIT(0),
142 BB_PATH_B = BIT(1),
143 BB_PATH_C = BIT(2),
144 BB_PATH_D = BIT(3),
145
146 BB_PATH_AB = (BB_PATH_A | BB_PATH_B),
147 BB_PATH_AC = (BB_PATH_A | BB_PATH_C),
148 BB_PATH_AD = (BB_PATH_A | BB_PATH_D),
149 BB_PATH_BC = (BB_PATH_B | BB_PATH_C),
150 BB_PATH_BD = (BB_PATH_B | BB_PATH_D),
151 BB_PATH_CD = (BB_PATH_C | BB_PATH_D),
152
153 BB_PATH_ABC = (BB_PATH_A | BB_PATH_B | BB_PATH_C),
154 BB_PATH_ABD = (BB_PATH_A | BB_PATH_B | BB_PATH_D),
155 BB_PATH_ACD = (BB_PATH_A | BB_PATH_C | BB_PATH_D),
156 BB_PATH_BCD = (BB_PATH_B | BB_PATH_C | BB_PATH_D),
157
158 BB_PATH_ABCD = (BB_PATH_A | BB_PATH_B | BB_PATH_C | BB_PATH_D),
159 };
160
161 enum rtw_rate_section {
162 RTW_RATE_SECTION_CCK = 0,
163 RTW_RATE_SECTION_OFDM,
164 RTW_RATE_SECTION_HT_1S,
165 RTW_RATE_SECTION_HT_2S,
166 RTW_RATE_SECTION_VHT_1S,
167 RTW_RATE_SECTION_VHT_2S,
168
169 /* keep last */
170 RTW_RATE_SECTION_MAX,
171 };
172
173 enum rtw_wireless_set {
174 WIRELESS_CCK = 0x00000001,
175 WIRELESS_OFDM = 0x00000002,
176 WIRELESS_HT = 0x00000004,
177 WIRELESS_VHT = 0x00000008,
178 };
179
180 #define HT_STBC_EN BIT(0)
181 #define VHT_STBC_EN BIT(1)
182 #define HT_LDPC_EN BIT(0)
183 #define VHT_LDPC_EN BIT(1)
184
185 enum rtw_chip_type {
186 RTW_CHIP_TYPE_8822B,
187 RTW_CHIP_TYPE_8822C,
188 RTW_CHIP_TYPE_8723D,
189 RTW_CHIP_TYPE_8821C,
190 };
191
192 enum rtw_tx_queue_type {
193 /* the order of AC queues matters */
194 RTW_TX_QUEUE_BK = 0x0,
195 RTW_TX_QUEUE_BE = 0x1,
196 RTW_TX_QUEUE_VI = 0x2,
197 RTW_TX_QUEUE_VO = 0x3,
198
199 RTW_TX_QUEUE_BCN = 0x4,
200 RTW_TX_QUEUE_MGMT = 0x5,
201 RTW_TX_QUEUE_HI0 = 0x6,
202 RTW_TX_QUEUE_H2C = 0x7,
203 /* keep it last */
204 RTK_MAX_TX_QUEUE_NUM
205 };
206
207 enum rtw_rx_queue_type {
208 RTW_RX_QUEUE_MPDU = 0x0,
209 RTW_RX_QUEUE_C2H = 0x1,
210 /* keep it last */
211 RTK_MAX_RX_QUEUE_NUM
212 };
213
214 enum rtw_fw_type {
215 RTW_NORMAL_FW = 0x0,
216 RTW_WOWLAN_FW = 0x1,
217 };
218
219 enum rtw_rate_index {
220 RTW_RATEID_BGN_40M_2SS = 0,
221 RTW_RATEID_BGN_40M_1SS = 1,
222 RTW_RATEID_BGN_20M_2SS = 2,
223 RTW_RATEID_BGN_20M_1SS = 3,
224 RTW_RATEID_GN_N2SS = 4,
225 RTW_RATEID_GN_N1SS = 5,
226 RTW_RATEID_BG = 6,
227 RTW_RATEID_G = 7,
228 RTW_RATEID_B_20M = 8,
229 RTW_RATEID_ARFR0_AC_2SS = 9,
230 RTW_RATEID_ARFR1_AC_1SS = 10,
231 RTW_RATEID_ARFR2_AC_2G_1SS = 11,
232 RTW_RATEID_ARFR3_AC_2G_2SS = 12,
233 RTW_RATEID_ARFR4_AC_3SS = 13,
234 RTW_RATEID_ARFR5_N_3SS = 14,
235 RTW_RATEID_ARFR7_N_4SS = 15,
236 RTW_RATEID_ARFR6_AC_4SS = 16
237 };
238
239 enum rtw_trx_desc_rate {
240 DESC_RATE1M = 0x00,
241 DESC_RATE2M = 0x01,
242 DESC_RATE5_5M = 0x02,
243 DESC_RATE11M = 0x03,
244
245 DESC_RATE6M = 0x04,
246 DESC_RATE9M = 0x05,
247 DESC_RATE12M = 0x06,
248 DESC_RATE18M = 0x07,
249 DESC_RATE24M = 0x08,
250 DESC_RATE36M = 0x09,
251 DESC_RATE48M = 0x0a,
252 DESC_RATE54M = 0x0b,
253
254 DESC_RATEMCS0 = 0x0c,
255 DESC_RATEMCS1 = 0x0d,
256 DESC_RATEMCS2 = 0x0e,
257 DESC_RATEMCS3 = 0x0f,
258 DESC_RATEMCS4 = 0x10,
259 DESC_RATEMCS5 = 0x11,
260 DESC_RATEMCS6 = 0x12,
261 DESC_RATEMCS7 = 0x13,
262 DESC_RATEMCS8 = 0x14,
263 DESC_RATEMCS9 = 0x15,
264 DESC_RATEMCS10 = 0x16,
265 DESC_RATEMCS11 = 0x17,
266 DESC_RATEMCS12 = 0x18,
267 DESC_RATEMCS13 = 0x19,
268 DESC_RATEMCS14 = 0x1a,
269 DESC_RATEMCS15 = 0x1b,
270 DESC_RATEMCS16 = 0x1c,
271 DESC_RATEMCS17 = 0x1d,
272 DESC_RATEMCS18 = 0x1e,
273 DESC_RATEMCS19 = 0x1f,
274 DESC_RATEMCS20 = 0x20,
275 DESC_RATEMCS21 = 0x21,
276 DESC_RATEMCS22 = 0x22,
277 DESC_RATEMCS23 = 0x23,
278 DESC_RATEMCS24 = 0x24,
279 DESC_RATEMCS25 = 0x25,
280 DESC_RATEMCS26 = 0x26,
281 DESC_RATEMCS27 = 0x27,
282 DESC_RATEMCS28 = 0x28,
283 DESC_RATEMCS29 = 0x29,
284 DESC_RATEMCS30 = 0x2a,
285 DESC_RATEMCS31 = 0x2b,
286
287 DESC_RATEVHT1SS_MCS0 = 0x2c,
288 DESC_RATEVHT1SS_MCS1 = 0x2d,
289 DESC_RATEVHT1SS_MCS2 = 0x2e,
290 DESC_RATEVHT1SS_MCS3 = 0x2f,
291 DESC_RATEVHT1SS_MCS4 = 0x30,
292 DESC_RATEVHT1SS_MCS5 = 0x31,
293 DESC_RATEVHT1SS_MCS6 = 0x32,
294 DESC_RATEVHT1SS_MCS7 = 0x33,
295 DESC_RATEVHT1SS_MCS8 = 0x34,
296 DESC_RATEVHT1SS_MCS9 = 0x35,
297
298 DESC_RATEVHT2SS_MCS0 = 0x36,
299 DESC_RATEVHT2SS_MCS1 = 0x37,
300 DESC_RATEVHT2SS_MCS2 = 0x38,
301 DESC_RATEVHT2SS_MCS3 = 0x39,
302 DESC_RATEVHT2SS_MCS4 = 0x3a,
303 DESC_RATEVHT2SS_MCS5 = 0x3b,
304 DESC_RATEVHT2SS_MCS6 = 0x3c,
305 DESC_RATEVHT2SS_MCS7 = 0x3d,
306 DESC_RATEVHT2SS_MCS8 = 0x3e,
307 DESC_RATEVHT2SS_MCS9 = 0x3f,
308
309 DESC_RATEVHT3SS_MCS0 = 0x40,
310 DESC_RATEVHT3SS_MCS1 = 0x41,
311 DESC_RATEVHT3SS_MCS2 = 0x42,
312 DESC_RATEVHT3SS_MCS3 = 0x43,
313 DESC_RATEVHT3SS_MCS4 = 0x44,
314 DESC_RATEVHT3SS_MCS5 = 0x45,
315 DESC_RATEVHT3SS_MCS6 = 0x46,
316 DESC_RATEVHT3SS_MCS7 = 0x47,
317 DESC_RATEVHT3SS_MCS8 = 0x48,
318 DESC_RATEVHT3SS_MCS9 = 0x49,
319
320 DESC_RATEVHT4SS_MCS0 = 0x4a,
321 DESC_RATEVHT4SS_MCS1 = 0x4b,
322 DESC_RATEVHT4SS_MCS2 = 0x4c,
323 DESC_RATEVHT4SS_MCS3 = 0x4d,
324 DESC_RATEVHT4SS_MCS4 = 0x4e,
325 DESC_RATEVHT4SS_MCS5 = 0x4f,
326 DESC_RATEVHT4SS_MCS6 = 0x50,
327 DESC_RATEVHT4SS_MCS7 = 0x51,
328 DESC_RATEVHT4SS_MCS8 = 0x52,
329 DESC_RATEVHT4SS_MCS9 = 0x53,
330
331 DESC_RATE_MAX,
332 };
333
334 enum rtw_regulatory_domains {
335 RTW_REGD_FCC = 0,
336 RTW_REGD_MKK = 1,
337 RTW_REGD_ETSI = 2,
338 RTW_REGD_IC = 3,
339 RTW_REGD_KCC = 4,
340 RTW_REGD_ACMA = 5,
341 RTW_REGD_CHILE = 6,
342 RTW_REGD_UKRAINE = 7,
343 RTW_REGD_MEXICO = 8,
344 RTW_REGD_CN = 9,
345 RTW_REGD_WW,
346
347 RTW_REGD_MAX
348 };
349
350 enum rtw_txq_flags {
351 RTW_TXQ_AMPDU,
352 RTW_TXQ_BLOCK_BA,
353 };
354
355 enum rtw_flags {
356 RTW_FLAG_RUNNING,
357 RTW_FLAG_FW_RUNNING,
358 RTW_FLAG_SCANNING,
359 RTW_FLAG_INACTIVE_PS,
360 RTW_FLAG_LEISURE_PS,
361 RTW_FLAG_LEISURE_PS_DEEP,
362 RTW_FLAG_DIG_DISABLE,
363 RTW_FLAG_BUSY_TRAFFIC,
364 RTW_FLAG_WOWLAN,
365 RTW_FLAG_RESTARTING,
366 RTW_FLAG_RESTART_TRIGGERING,
367
368 NUM_OF_RTW_FLAGS,
369 };
370
371 enum rtw_evm {
372 RTW_EVM_OFDM = 0,
373 RTW_EVM_1SS,
374 RTW_EVM_2SS_A,
375 RTW_EVM_2SS_B,
376 /* keep it last */
377 RTW_EVM_NUM
378 };
379
380 enum rtw_snr {
381 RTW_SNR_OFDM_A = 0,
382 RTW_SNR_OFDM_B,
383 RTW_SNR_OFDM_C,
384 RTW_SNR_OFDM_D,
385 RTW_SNR_1SS_A,
386 RTW_SNR_1SS_B,
387 RTW_SNR_1SS_C,
388 RTW_SNR_1SS_D,
389 RTW_SNR_2SS_A,
390 RTW_SNR_2SS_B,
391 RTW_SNR_2SS_C,
392 RTW_SNR_2SS_D,
393 /* keep it last */
394 RTW_SNR_NUM
395 };
396
397 enum rtw_wow_flags {
398 RTW_WOW_FLAG_EN_MAGIC_PKT,
399 RTW_WOW_FLAG_EN_REKEY_PKT,
400 RTW_WOW_FLAG_EN_DISCONNECT,
401
402 /* keep it last */
403 RTW_WOW_FLAG_MAX,
404 };
405
406 /* the power index is represented by differences, which cck-1s & ht40-1s are
407 * the base values, so for 1s's differences, there are only ht20 & ofdm
408 */
409 struct rtw_2g_1s_pwr_idx_diff {
410 #ifdef __LITTLE_ENDIAN
411 s8 ofdm:4;
412 s8 bw20:4;
413 #else
414 s8 bw20:4;
415 s8 ofdm:4;
416 #endif
417 } __packed;
418
419 struct rtw_2g_ns_pwr_idx_diff {
420 #ifdef __LITTLE_ENDIAN
421 s8 bw20:4;
422 s8 bw40:4;
423 s8 cck:4;
424 s8 ofdm:4;
425 #else
426 s8 ofdm:4;
427 s8 cck:4;
428 s8 bw40:4;
429 s8 bw20:4;
430 #endif
431 } __packed;
432
433 struct rtw_2g_txpwr_idx {
434 u8 cck_base[6];
435 u8 bw40_base[5];
436 struct rtw_2g_1s_pwr_idx_diff ht_1s_diff;
437 struct rtw_2g_ns_pwr_idx_diff ht_2s_diff;
438 struct rtw_2g_ns_pwr_idx_diff ht_3s_diff;
439 struct rtw_2g_ns_pwr_idx_diff ht_4s_diff;
440 };
441
442 struct rtw_5g_ht_1s_pwr_idx_diff {
443 #ifdef __LITTLE_ENDIAN
444 s8 ofdm:4;
445 s8 bw20:4;
446 #else
447 s8 bw20:4;
448 s8 ofdm:4;
449 #endif
450 } __packed;
451
452 struct rtw_5g_ht_ns_pwr_idx_diff {
453 #ifdef __LITTLE_ENDIAN
454 s8 bw20:4;
455 s8 bw40:4;
456 #else
457 s8 bw40:4;
458 s8 bw20:4;
459 #endif
460 } __packed;
461
462 struct rtw_5g_ofdm_ns_pwr_idx_diff {
463 #ifdef __LITTLE_ENDIAN
464 s8 ofdm_3s:4;
465 s8 ofdm_2s:4;
466 s8 ofdm_4s:4;
467 s8 res:4;
468 #else
469 s8 res:4;
470 s8 ofdm_4s:4;
471 s8 ofdm_2s:4;
472 s8 ofdm_3s:4;
473 #endif
474 } __packed;
475
476 struct rtw_5g_vht_ns_pwr_idx_diff {
477 #ifdef __LITTLE_ENDIAN
478 s8 bw160:4;
479 s8 bw80:4;
480 #else
481 s8 bw80:4;
482 s8 bw160:4;
483 #endif
484 } __packed;
485
486 struct rtw_5g_txpwr_idx {
487 u8 bw40_base[14];
488 struct rtw_5g_ht_1s_pwr_idx_diff ht_1s_diff;
489 struct rtw_5g_ht_ns_pwr_idx_diff ht_2s_diff;
490 struct rtw_5g_ht_ns_pwr_idx_diff ht_3s_diff;
491 struct rtw_5g_ht_ns_pwr_idx_diff ht_4s_diff;
492 struct rtw_5g_ofdm_ns_pwr_idx_diff ofdm_diff;
493 struct rtw_5g_vht_ns_pwr_idx_diff vht_1s_diff;
494 struct rtw_5g_vht_ns_pwr_idx_diff vht_2s_diff;
495 struct rtw_5g_vht_ns_pwr_idx_diff vht_3s_diff;
496 struct rtw_5g_vht_ns_pwr_idx_diff vht_4s_diff;
497 };
498
499 struct rtw_txpwr_idx {
500 struct rtw_2g_txpwr_idx pwr_idx_2g;
501 struct rtw_5g_txpwr_idx pwr_idx_5g;
502 };
503
504 struct rtw_timer_list {
505 struct timer_list timer;
506 void (*function)(void *data);
507 void *args;
508 };
509
510 struct rtw_channel_params {
511 u8 center_chan;
512 u8 bandwidth;
513 u8 primary_chan_idx;
514 /* center channel by different available bandwidth,
515 * val of (bw > current bandwidth) is invalid
516 */
517 u8 cch_by_bw[RTW_MAX_CHANNEL_WIDTH + 1];
518 };
519
520 struct rtw_hw_reg {
521 u32 addr;
522 u32 mask;
523 };
524
525 struct rtw_ltecoex_addr {
526 u32 ctrl;
527 u32 wdata;
528 u32 rdata;
529 };
530
531 struct rtw_reg_domain {
532 u32 addr;
533 u32 mask;
534 #define RTW_REG_DOMAIN_MAC32 0
535 #define RTW_REG_DOMAIN_MAC16 1
536 #define RTW_REG_DOMAIN_MAC8 2
537 #define RTW_REG_DOMAIN_RF_A 3
538 #define RTW_REG_DOMAIN_RF_B 4
539 #define RTW_REG_DOMAIN_NL 0xFF
540 u8 domain;
541 };
542
543 struct rtw_rf_sipi_addr {
544 u32 hssi_1;
545 u32 hssi_2;
546 u32 lssi_read;
547 u32 lssi_read_pi;
548 };
549
550 struct rtw_hw_reg_offset {
551 struct rtw_hw_reg hw_reg;
552 u8 offset;
553 };
554
555 struct rtw_backup_info {
556 u8 len;
557 u32 reg;
558 u32 val;
559 };
560
561 enum rtw_vif_port_set {
562 PORT_SET_MAC_ADDR = BIT(0),
563 PORT_SET_BSSID = BIT(1),
564 PORT_SET_NET_TYPE = BIT(2),
565 PORT_SET_AID = BIT(3),
566 PORT_SET_BCN_CTRL = BIT(4),
567 };
568
569 struct rtw_vif_port {
570 struct rtw_hw_reg mac_addr;
571 struct rtw_hw_reg bssid;
572 struct rtw_hw_reg net_type;
573 struct rtw_hw_reg aid;
574 struct rtw_hw_reg bcn_ctrl;
575 };
576
577 struct rtw_tx_pkt_info {
578 u32 tx_pkt_size;
579 u8 offset;
580 u8 pkt_offset;
581 u8 mac_id;
582 u8 rate_id;
583 u8 rate;
584 u8 qsel;
585 u8 bw;
586 u8 sec_type;
587 u8 sn;
588 bool ampdu_en;
589 u8 ampdu_factor;
590 u8 ampdu_density;
591 u16 seq;
592 bool stbc;
593 bool ldpc;
594 bool dis_rate_fallback;
595 bool bmc;
596 bool use_rate;
597 bool ls;
598 bool fs;
599 bool short_gi;
600 bool report;
601 bool rts;
602 bool dis_qselseq;
603 bool en_hwseq;
604 u8 hw_ssn_sel;
605 bool nav_use_hdr;
606 bool bt_null;
607 };
608
609 struct rtw_rx_pkt_stat {
610 bool phy_status;
611 bool icv_err;
612 bool crc_err;
613 bool decrypted;
614 bool is_c2h;
615
616 s32 signal_power;
617 u16 pkt_len;
618 u8 bw;
619 u8 drv_info_sz;
620 u8 shift;
621 u8 rate;
622 u8 mac_id;
623 u8 cam_id;
624 u8 ppdu_cnt;
625 u32 tsf_low;
626 s8 rx_power[RTW_RF_PATH_MAX];
627 u8 rssi;
628 u8 rxsc;
629 s8 rx_snr[RTW_RF_PATH_MAX];
630 u8 rx_evm[RTW_RF_PATH_MAX];
631 s8 cfo_tail[RTW_RF_PATH_MAX];
632
633 struct rtw_sta_info *si;
634 struct ieee80211_vif *vif;
635 struct ieee80211_hdr *hdr;
636 };
637
638 DECLARE_EWMA(tp, 10, 2);
639
640 struct rtw_traffic_stats {
641 /* units in bytes */
642 u64 tx_unicast;
643 u64 rx_unicast;
644
645 /* count for packets */
646 u64 tx_cnt;
647 u64 rx_cnt;
648
649 /* units in Mbps */
650 u32 tx_throughput;
651 u32 rx_throughput;
652 struct ewma_tp tx_ewma_tp;
653 struct ewma_tp rx_ewma_tp;
654 };
655
656 enum rtw_lps_mode {
657 RTW_MODE_ACTIVE = 0,
658 RTW_MODE_LPS = 1,
659 RTW_MODE_WMM_PS = 2,
660 };
661
662 enum rtw_lps_deep_mode {
663 LPS_DEEP_MODE_NONE = 0,
664 LPS_DEEP_MODE_LCLK = 1,
665 LPS_DEEP_MODE_PG = 2,
666 };
667
668 enum rtw_pwr_state {
669 RTW_RF_OFF = 0x0,
670 RTW_RF_ON = 0x4,
671 RTW_ALL_ON = 0xc,
672 };
673
674 struct rtw_lps_conf {
675 enum rtw_lps_mode mode;
676 enum rtw_lps_deep_mode deep_mode;
677 enum rtw_lps_deep_mode wow_deep_mode;
678 enum rtw_pwr_state state;
679 u8 awake_interval;
680 u8 rlbm;
681 u8 smart_ps;
682 u8 port_id;
683 bool sec_cam_backup;
684 bool pattern_cam_backup;
685 };
686
687 enum rtw_hw_key_type {
688 RTW_CAM_NONE = 0,
689 RTW_CAM_WEP40 = 1,
690 RTW_CAM_TKIP = 2,
691 RTW_CAM_AES = 4,
692 RTW_CAM_WEP104 = 5,
693 };
694
695 struct rtw_cam_entry {
696 bool valid;
697 bool group;
698 u8 addr[ETH_ALEN];
699 u8 hw_key_type;
700 struct ieee80211_key_conf *key;
701 };
702
703 struct rtw_sec_desc {
704 /* search strategy */
705 bool default_key_search;
706
707 u32 total_cam_num;
708 struct rtw_cam_entry cam_table[RTW_MAX_SEC_CAM_NUM];
709 DECLARE_BITMAP(cam_map, RTW_MAX_SEC_CAM_NUM);
710 };
711
712 struct rtw_tx_report {
713 /* protect the tx report queue */
714 spinlock_t q_lock;
715 struct sk_buff_head queue;
716 atomic_t sn;
717 struct timer_list purge_timer;
718 };
719
720 struct rtw_ra_report {
721 struct rate_info txrate;
722 u32 bit_rate;
723 u8 desc_rate;
724 };
725
726 struct rtw_txq {
727 struct list_head list;
728
729 unsigned long flags;
730 unsigned long last_push;
731 };
732
733 #define RTW_BC_MC_MACID 1
734 DECLARE_EWMA(rssi, 10, 16);
735
736 struct rtw_sta_info {
737 struct ieee80211_sta *sta;
738 struct ieee80211_vif *vif;
739
740 struct ewma_rssi avg_rssi;
741 u8 rssi_level;
742
743 u8 mac_id;
744 u8 rate_id;
745 enum rtw_bandwidth bw_mode;
746 enum rtw_rf_type rf_type;
747 enum rtw_wireless_set wireless_set;
748 u8 stbc_en:2;
749 u8 ldpc_en:2;
750 bool sgi_enable;
751 bool vht_enable;
752 bool updated;
753 u8 init_ra_lv;
754 u64 ra_mask;
755
756 DECLARE_BITMAP(tid_ba, IEEE80211_NUM_TIDS);
757
758 struct rtw_ra_report ra_report;
759
760 bool use_cfg_mask;
761 struct cfg80211_bitrate_mask *mask;
762 };
763
764 enum rtw_bfee_role {
765 RTW_BFEE_NONE,
766 RTW_BFEE_SU,
767 RTW_BFEE_MU
768 };
769
770 struct rtw_bfee {
771 enum rtw_bfee_role role;
772
773 u16 p_aid;
774 u8 g_id;
775 u8 mac_addr[ETH_ALEN];
776 u8 sound_dim;
777
778 /* SU-MIMO */
779 u8 su_reg_index;
780
781 /* MU-MIMO */
782 u16 aid;
783 };
784
785 struct rtw_bf_info {
786 u8 bfer_mu_cnt;
787 u8 bfer_su_cnt;
788 DECLARE_BITMAP(bfer_su_reg_maping, 2);
789 u8 cur_csi_rpt_rate;
790 };
791
792 struct rtw_vif {
793 enum rtw_net_type net_type;
794 u16 aid;
795 u8 mac_addr[ETH_ALEN];
796 u8 bssid[ETH_ALEN];
797 u8 port;
798 u8 bcn_ctrl;
799 struct list_head rsvd_page_list;
800 struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS];
801 const struct rtw_vif_port *conf;
802
803 struct rtw_traffic_stats stats;
804
805 struct rtw_bfee bfee;
806 };
807
808 struct rtw_regulatory {
809 char alpha2[2];
810 u8 txpwr_regd_2g;
811 u8 txpwr_regd_5g;
812 };
813
814 enum rtw_regd_state {
815 RTW_REGD_STATE_WORLDWIDE,
816 RTW_REGD_STATE_PROGRAMMED,
817 RTW_REGD_STATE_SETTING,
818
819 RTW_REGD_STATE_NR,
820 };
821
822 struct rtw_regd {
823 enum rtw_regd_state state;
824 const struct rtw_regulatory *regulatory;
825 enum nl80211_dfs_regions dfs_region;
826 };
827
828 struct rtw_chip_ops {
829 int (*mac_init)(struct rtw_dev *rtwdev);
830 int (*dump_fw_crash)(struct rtw_dev *rtwdev);
831 void (*shutdown)(struct rtw_dev *rtwdev);
832 int (*read_efuse)(struct rtw_dev *rtwdev, u8 *map);
833 void (*phy_set_param)(struct rtw_dev *rtwdev);
834 void (*set_channel)(struct rtw_dev *rtwdev, u8 channel,
835 u8 bandwidth, u8 primary_chan_idx);
836 void (*query_rx_desc)(struct rtw_dev *rtwdev, u8 *rx_desc,
837 struct rtw_rx_pkt_stat *pkt_stat,
838 struct ieee80211_rx_status *rx_status);
839 u32 (*read_rf)(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
840 u32 addr, u32 mask);
841 bool (*write_rf)(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
842 u32 addr, u32 mask, u32 data);
843 void (*set_tx_power_index)(struct rtw_dev *rtwdev);
844 int (*rsvd_page_dump)(struct rtw_dev *rtwdev, u8 *buf, u32 offset,
845 u32 size);
846 int (*set_antenna)(struct rtw_dev *rtwdev,
847 u32 antenna_tx,
848 u32 antenna_rx);
849 void (*cfg_ldo25)(struct rtw_dev *rtwdev, bool enable);
850 void (*efuse_grant)(struct rtw_dev *rtwdev, bool enable);
851 void (*false_alarm_statistics)(struct rtw_dev *rtwdev);
852 void (*phy_calibration)(struct rtw_dev *rtwdev);
853 void (*dpk_track)(struct rtw_dev *rtwdev);
854 void (*cck_pd_set)(struct rtw_dev *rtwdev, u8 level);
855 void (*pwr_track)(struct rtw_dev *rtwdev);
856 void (*config_bfee)(struct rtw_dev *rtwdev, struct rtw_vif *vif,
857 struct rtw_bfee *bfee, bool enable);
858 void (*set_gid_table)(struct rtw_dev *rtwdev,
859 struct ieee80211_vif *vif,
860 struct ieee80211_bss_conf *conf);
861 void (*cfg_csi_rate)(struct rtw_dev *rtwdev, u8 rssi, u8 cur_rate,
862 u8 fixrate_en, u8 *new_rate);
863 void (*adaptivity_init)(struct rtw_dev *rtwdev);
864 void (*adaptivity)(struct rtw_dev *rtwdev);
865 void (*cfo_init)(struct rtw_dev *rtwdev);
866 void (*cfo_track)(struct rtw_dev *rtwdev);
867 void (*config_tx_path)(struct rtw_dev *rtwdev, u8 tx_path,
868 enum rtw_bb_path tx_path_1ss,
869 enum rtw_bb_path tx_path_cck,
870 bool is_tx2_path);
871
872 /* for coex */
873 void (*coex_set_init)(struct rtw_dev *rtwdev);
874 void (*coex_set_ant_switch)(struct rtw_dev *rtwdev,
875 u8 ctrl_type, u8 pos_type);
876 void (*coex_set_gnt_fix)(struct rtw_dev *rtwdev);
877 void (*coex_set_gnt_debug)(struct rtw_dev *rtwdev);
878 void (*coex_set_rfe_type)(struct rtw_dev *rtwdev);
879 void (*coex_set_wl_tx_power)(struct rtw_dev *rtwdev, u8 wl_pwr);
880 void (*coex_set_wl_rx_gain)(struct rtw_dev *rtwdev, bool low_gain);
881 };
882
883 #define RTW_PWR_POLLING_CNT 20000
884
885 #define RTW_PWR_CMD_READ 0x00
886 #define RTW_PWR_CMD_WRITE 0x01
887 #define RTW_PWR_CMD_POLLING 0x02
888 #define RTW_PWR_CMD_DELAY 0x03
889 #define RTW_PWR_CMD_END 0x04
890
891 /* define the base address of each block */
892 #define RTW_PWR_ADDR_MAC 0x00
893 #define RTW_PWR_ADDR_USB 0x01
894 #define RTW_PWR_ADDR_PCIE 0x02
895 #define RTW_PWR_ADDR_SDIO 0x03
896
897 #define RTW_PWR_INTF_SDIO_MSK BIT(0)
898 #define RTW_PWR_INTF_USB_MSK BIT(1)
899 #define RTW_PWR_INTF_PCI_MSK BIT(2)
900 #define RTW_PWR_INTF_ALL_MSK (BIT(0) | BIT(1) | BIT(2) | BIT(3))
901
902 #define RTW_PWR_CUT_TEST_MSK BIT(0)
903 #define RTW_PWR_CUT_A_MSK BIT(1)
904 #define RTW_PWR_CUT_B_MSK BIT(2)
905 #define RTW_PWR_CUT_C_MSK BIT(3)
906 #define RTW_PWR_CUT_D_MSK BIT(4)
907 #define RTW_PWR_CUT_E_MSK BIT(5)
908 #define RTW_PWR_CUT_F_MSK BIT(6)
909 #define RTW_PWR_CUT_G_MSK BIT(7)
910 #define RTW_PWR_CUT_ALL_MSK 0xFF
911
912 enum rtw_pwr_seq_cmd_delay_unit {
913 RTW_PWR_DELAY_US,
914 RTW_PWR_DELAY_MS,
915 };
916
917 struct rtw_pwr_seq_cmd {
918 u16 offset;
919 u8 cut_mask;
920 u8 intf_mask;
921 u8 base:4;
922 u8 cmd:4;
923 u8 mask;
924 u8 value;
925 };
926
927 enum rtw_chip_ver {
928 RTW_CHIP_VER_CUT_A = 0x00,
929 RTW_CHIP_VER_CUT_B = 0x01,
930 RTW_CHIP_VER_CUT_C = 0x02,
931 RTW_CHIP_VER_CUT_D = 0x03,
932 RTW_CHIP_VER_CUT_E = 0x04,
933 RTW_CHIP_VER_CUT_F = 0x05,
934 RTW_CHIP_VER_CUT_G = 0x06,
935 };
936
937 #define RTW_INTF_PHY_PLATFORM_ALL 0
938
939 enum rtw_intf_phy_cut {
940 RTW_INTF_PHY_CUT_A = BIT(0),
941 RTW_INTF_PHY_CUT_B = BIT(1),
942 RTW_INTF_PHY_CUT_C = BIT(2),
943 RTW_INTF_PHY_CUT_D = BIT(3),
944 RTW_INTF_PHY_CUT_E = BIT(4),
945 RTW_INTF_PHY_CUT_F = BIT(5),
946 RTW_INTF_PHY_CUT_G = BIT(6),
947 RTW_INTF_PHY_CUT_ALL = 0xFFFF,
948 };
949
950 enum rtw_ip_sel {
951 RTW_IP_SEL_PHY = 0,
952 RTW_IP_SEL_MAC = 1,
953 RTW_IP_SEL_DBI = 2,
954
955 RTW_IP_SEL_UNDEF = 0xFFFF
956 };
957
958 enum rtw_pq_map_id {
959 RTW_PQ_MAP_VO = 0x0,
960 RTW_PQ_MAP_VI = 0x1,
961 RTW_PQ_MAP_BE = 0x2,
962 RTW_PQ_MAP_BK = 0x3,
963 RTW_PQ_MAP_MG = 0x4,
964 RTW_PQ_MAP_HI = 0x5,
965 RTW_PQ_MAP_NUM = 0x6,
966
967 RTW_PQ_MAP_UNDEF,
968 };
969
970 enum rtw_dma_mapping {
971 RTW_DMA_MAPPING_EXTRA = 0,
972 RTW_DMA_MAPPING_LOW = 1,
973 RTW_DMA_MAPPING_NORMAL = 2,
974 RTW_DMA_MAPPING_HIGH = 3,
975
976 RTW_DMA_MAPPING_MAX,
977 RTW_DMA_MAPPING_UNDEF,
978 };
979
980 struct rtw_rqpn {
981 enum rtw_dma_mapping dma_map_vo;
982 enum rtw_dma_mapping dma_map_vi;
983 enum rtw_dma_mapping dma_map_be;
984 enum rtw_dma_mapping dma_map_bk;
985 enum rtw_dma_mapping dma_map_mg;
986 enum rtw_dma_mapping dma_map_hi;
987 };
988
989 struct rtw_prioq_addr {
990 u32 rsvd;
991 u32 avail;
992 };
993
994 struct rtw_prioq_addrs {
995 struct rtw_prioq_addr prio[RTW_DMA_MAPPING_MAX];
996 bool wsize;
997 };
998
999 struct rtw_page_table {
1000 u16 hq_num;
1001 u16 nq_num;
1002 u16 lq_num;
1003 u16 exq_num;
1004 u16 gapq_num;
1005 };
1006
1007 struct rtw_intf_phy_para {
1008 u16 offset;
1009 u16 value;
1010 u16 ip_sel;
1011 u16 cut_mask;
1012 u16 platform;
1013 };
1014
1015 struct rtw_wow_pattern {
1016 u16 crc;
1017 u8 type;
1018 u8 valid;
1019 u8 mask[RTW_MAX_PATTERN_MASK_SIZE];
1020 };
1021
1022 struct rtw_pno_request {
1023 bool inited;
1024 u32 match_set_cnt;
1025 struct cfg80211_match_set *match_sets;
1026 u8 channel_cnt;
1027 struct ieee80211_channel *channels;
1028 struct cfg80211_sched_scan_plan scan_plan;
1029 };
1030
1031 struct rtw_wow_param {
1032 struct ieee80211_vif *wow_vif;
1033 DECLARE_BITMAP(flags, RTW_WOW_FLAG_MAX);
1034 u8 txpause;
1035 u8 pattern_cnt;
1036 struct rtw_wow_pattern patterns[RTW_MAX_PATTERN_NUM];
1037
1038 bool ips_enabled;
1039 struct rtw_pno_request pno_req;
1040 };
1041
1042 struct rtw_intf_phy_para_table {
1043 const struct rtw_intf_phy_para *usb2_para;
1044 const struct rtw_intf_phy_para *usb3_para;
1045 const struct rtw_intf_phy_para *gen1_para;
1046 const struct rtw_intf_phy_para *gen2_para;
1047 u8 n_usb2_para;
1048 u8 n_usb3_para;
1049 u8 n_gen1_para;
1050 u8 n_gen2_para;
1051 };
1052
1053 struct rtw_table {
1054 const void *data;
1055 const u32 size;
1056 void (*parse)(struct rtw_dev *rtwdev, const struct rtw_table *tbl);
1057 void (*do_cfg)(struct rtw_dev *rtwdev, const struct rtw_table *tbl,
1058 u32 addr, u32 data);
1059 enum rtw_rf_path rf_path;
1060 };
1061
rtw_load_table(struct rtw_dev * rtwdev,const struct rtw_table * tbl)1062 static inline void rtw_load_table(struct rtw_dev *rtwdev,
1063 const struct rtw_table *tbl)
1064 {
1065 (*tbl->parse)(rtwdev, tbl);
1066 }
1067
1068 enum rtw_rfe_fem {
1069 RTW_RFE_IFEM,
1070 RTW_RFE_EFEM,
1071 RTW_RFE_IFEM2G_EFEM5G,
1072 RTW_RFE_NUM,
1073 };
1074
1075 struct rtw_rfe_def {
1076 const struct rtw_table *phy_pg_tbl;
1077 const struct rtw_table *txpwr_lmt_tbl;
1078 const struct rtw_table *agc_btg_tbl;
1079 };
1080
1081 #define RTW_DEF_RFE(chip, bb_pg, pwrlmt) { \
1082 .phy_pg_tbl = &rtw ## chip ## _bb_pg_type ## bb_pg ## _tbl, \
1083 .txpwr_lmt_tbl = &rtw ## chip ## _txpwr_lmt_type ## pwrlmt ## _tbl, \
1084 }
1085
1086 #define RTW_DEF_RFE_EXT(chip, bb_pg, pwrlmt, btg) { \
1087 .phy_pg_tbl = &rtw ## chip ## _bb_pg_type ## bb_pg ## _tbl, \
1088 .txpwr_lmt_tbl = &rtw ## chip ## _txpwr_lmt_type ## pwrlmt ## _tbl, \
1089 .agc_btg_tbl = &rtw ## chip ## _agc_btg_type ## btg ## _tbl, \
1090 }
1091
1092 #define RTW_PWR_TRK_5G_1 0
1093 #define RTW_PWR_TRK_5G_2 1
1094 #define RTW_PWR_TRK_5G_3 2
1095 #define RTW_PWR_TRK_5G_NUM 3
1096
1097 #define RTW_PWR_TRK_TBL_SZ 30
1098
1099 /* This table stores the values of TX power that will be adjusted by power
1100 * tracking.
1101 *
1102 * For 5G bands, there are 3 different settings.
1103 * For 2G there are cck rate and ofdm rate with different settings.
1104 */
1105 struct rtw_pwr_track_tbl {
1106 const u8 *pwrtrk_5gb_n[RTW_PWR_TRK_5G_NUM];
1107 const u8 *pwrtrk_5gb_p[RTW_PWR_TRK_5G_NUM];
1108 const u8 *pwrtrk_5ga_n[RTW_PWR_TRK_5G_NUM];
1109 const u8 *pwrtrk_5ga_p[RTW_PWR_TRK_5G_NUM];
1110 const u8 *pwrtrk_2gb_n;
1111 const u8 *pwrtrk_2gb_p;
1112 const u8 *pwrtrk_2ga_n;
1113 const u8 *pwrtrk_2ga_p;
1114 const u8 *pwrtrk_2g_cckb_n;
1115 const u8 *pwrtrk_2g_cckb_p;
1116 const u8 *pwrtrk_2g_ccka_n;
1117 const u8 *pwrtrk_2g_ccka_p;
1118 const s8 *pwrtrk_xtal_n;
1119 const s8 *pwrtrk_xtal_p;
1120 };
1121
1122 enum rtw_wlan_cpu {
1123 RTW_WCPU_11AC,
1124 RTW_WCPU_11N,
1125 };
1126
1127 enum rtw_fw_fifo_sel {
1128 RTW_FW_FIFO_SEL_TX,
1129 RTW_FW_FIFO_SEL_RX,
1130 RTW_FW_FIFO_SEL_RSVD_PAGE,
1131 RTW_FW_FIFO_SEL_REPORT,
1132 RTW_FW_FIFO_SEL_LLT,
1133 RTW_FW_FIFO_SEL_RXBUF_FW,
1134
1135 RTW_FW_FIFO_MAX,
1136 };
1137
1138 enum rtw_fwcd_item {
1139 RTW_FWCD_TLV,
1140 RTW_FWCD_REG,
1141 RTW_FWCD_ROM,
1142 RTW_FWCD_IMEM,
1143 RTW_FWCD_DMEM,
1144 RTW_FWCD_EMEM,
1145 };
1146
1147 /* hardware configuration for each IC */
1148 struct rtw_chip_info {
1149 struct rtw_chip_ops *ops;
1150 u8 id;
1151
1152 const char *fw_name;
1153 enum rtw_wlan_cpu wlan_cpu;
1154 u8 tx_pkt_desc_sz;
1155 u8 tx_buf_desc_sz;
1156 u8 rx_pkt_desc_sz;
1157 u8 rx_buf_desc_sz;
1158 u32 phy_efuse_size;
1159 u32 log_efuse_size;
1160 u32 ptct_efuse_size;
1161 u32 txff_size;
1162 u32 rxff_size;
1163 u32 fw_rxff_size;
1164 u8 band;
1165 u8 page_size;
1166 u8 csi_buf_pg_num;
1167 u8 dig_max;
1168 u8 dig_min;
1169 u8 txgi_factor;
1170 bool is_pwr_by_rate_dec;
1171 bool rx_ldpc;
1172 bool tx_stbc;
1173 u8 max_power_index;
1174
1175 u16 fw_fifo_addr[RTW_FW_FIFO_MAX];
1176 const struct rtw_fwcd_segs *fwcd_segs;
1177
1178 u8 default_1ss_tx_path;
1179
1180 bool path_div_supported;
1181 bool ht_supported;
1182 bool vht_supported;
1183 u8 lps_deep_mode_supported;
1184
1185 /* init values */
1186 u8 sys_func_en;
1187 const struct rtw_pwr_seq_cmd **pwr_on_seq;
1188 const struct rtw_pwr_seq_cmd **pwr_off_seq;
1189 const struct rtw_rqpn *rqpn_table;
1190 const struct rtw_prioq_addrs *prioq_addrs;
1191 const struct rtw_page_table *page_table;
1192 const struct rtw_intf_phy_para_table *intf_table;
1193
1194 const struct rtw_hw_reg *dig;
1195 const struct rtw_hw_reg *dig_cck;
1196 u32 rf_base_addr[2];
1197 u32 rf_sipi_addr[2];
1198 const struct rtw_rf_sipi_addr *rf_sipi_read_addr;
1199 u8 fix_rf_phy_num;
1200 const struct rtw_ltecoex_addr *ltecoex_addr;
1201
1202 const struct rtw_table *mac_tbl;
1203 const struct rtw_table *agc_tbl;
1204 const struct rtw_table *bb_tbl;
1205 const struct rtw_table *rf_tbl[RTW_RF_PATH_MAX];
1206 const struct rtw_table *rfk_init_tbl;
1207
1208 const struct rtw_rfe_def *rfe_defs;
1209 u32 rfe_defs_size;
1210
1211 bool en_dis_dpd;
1212 u16 dpd_ratemask;
1213 u8 iqk_threshold;
1214 u8 lck_threshold;
1215 const struct rtw_pwr_track_tbl *pwr_track_tbl;
1216
1217 u8 bfer_su_max_num;
1218 u8 bfer_mu_max_num;
1219
1220 struct rtw_hw_reg_offset *edcca_th;
1221 s8 l2h_th_ini_cs;
1222 s8 l2h_th_ini_ad;
1223
1224 const char *wow_fw_name;
1225 const struct wiphy_wowlan_support *wowlan_stub;
1226 const u8 max_sched_scan_ssids;
1227
1228 /* for 8821c set channel */
1229 u32 ch_param[3];
1230
1231 /* coex paras */
1232 u32 coex_para_ver;
1233 u8 bt_desired_ver;
1234 bool scbd_support;
1235 bool new_scbd10_def; /* true: fix 2M(8822c) */
1236 bool ble_hid_profile_support;
1237 u8 pstdma_type; /* 0: LPSoff, 1:LPSon */
1238 u8 bt_rssi_type;
1239 u8 ant_isolation;
1240 u8 rssi_tolerance;
1241 u8 table_sant_num;
1242 u8 table_nsant_num;
1243 u8 tdma_sant_num;
1244 u8 tdma_nsant_num;
1245 u8 bt_afh_span_bw20;
1246 u8 bt_afh_span_bw40;
1247 u8 afh_5g_num;
1248 u8 wl_rf_para_num;
1249 u8 coex_info_hw_regs_num;
1250 const u8 *bt_rssi_step;
1251 const u8 *wl_rssi_step;
1252 const struct coex_table_para *table_nsant;
1253 const struct coex_table_para *table_sant;
1254 const struct coex_tdma_para *tdma_sant;
1255 const struct coex_tdma_para *tdma_nsant;
1256 const struct coex_rf_para *wl_rf_para_tx;
1257 const struct coex_rf_para *wl_rf_para_rx;
1258 const struct coex_5g_afh_map *afh_5g;
1259 const struct rtw_hw_reg *btg_reg;
1260 const struct rtw_reg_domain *coex_info_hw_regs;
1261 u32 wl_fw_desired_ver;
1262 };
1263
1264 enum rtw_coex_bt_state_cnt {
1265 COEX_CNT_BT_RETRY,
1266 COEX_CNT_BT_REINIT,
1267 COEX_CNT_BT_REENABLE,
1268 COEX_CNT_BT_POPEVENT,
1269 COEX_CNT_BT_SETUPLINK,
1270 COEX_CNT_BT_IGNWLANACT,
1271 COEX_CNT_BT_INQ,
1272 COEX_CNT_BT_PAGE,
1273 COEX_CNT_BT_ROLESWITCH,
1274 COEX_CNT_BT_AFHUPDATE,
1275 COEX_CNT_BT_INFOUPDATE,
1276 COEX_CNT_BT_IQK,
1277 COEX_CNT_BT_IQKFAIL,
1278
1279 COEX_CNT_BT_MAX
1280 };
1281
1282 enum rtw_coex_wl_state_cnt {
1283 COEX_CNT_WL_SCANAP,
1284 COEX_CNT_WL_CONNPKT,
1285 COEX_CNT_WL_COEXRUN,
1286 COEX_CNT_WL_NOISY0,
1287 COEX_CNT_WL_NOISY1,
1288 COEX_CNT_WL_NOISY2,
1289 COEX_CNT_WL_5MS_NOEXTEND,
1290 COEX_CNT_WL_FW_NOTIFY,
1291
1292 COEX_CNT_WL_MAX
1293 };
1294
1295 struct rtw_coex_rfe {
1296 bool ant_switch_exist;
1297 bool ant_switch_diversity;
1298 bool ant_switch_with_bt;
1299 u8 rfe_module_type;
1300 u8 ant_switch_polarity;
1301
1302 /* true if WLG at BTG, else at WLAG */
1303 bool wlg_at_btg;
1304 };
1305
1306 #define COEX_WL_TDMA_PARA_LENGTH 5
1307
1308 struct rtw_coex_dm {
1309 bool cur_ps_tdma_on;
1310 bool cur_wl_rx_low_gain_en;
1311 bool ignore_wl_act;
1312
1313 u8 reason;
1314 u8 bt_rssi_state[4];
1315 u8 wl_rssi_state[4];
1316 u8 wl_ch_info[3];
1317 u8 cur_ps_tdma;
1318 u8 cur_table;
1319 u8 ps_tdma_para[5];
1320 u8 cur_bt_pwr_lvl;
1321 u8 cur_bt_lna_lvl;
1322 u8 cur_wl_pwr_lvl;
1323 u8 bt_status;
1324 u32 cur_ant_pos_type;
1325 u32 cur_switch_status;
1326 u32 setting_tdma;
1327 u8 fw_tdma_para[COEX_WL_TDMA_PARA_LENGTH];
1328 };
1329
1330 #define COEX_BTINFO_SRC_WL_FW 0x0
1331 #define COEX_BTINFO_SRC_BT_RSP 0x1
1332 #define COEX_BTINFO_SRC_BT_ACT 0x2
1333 #define COEX_BTINFO_SRC_BT_IQK 0x3
1334 #define COEX_BTINFO_SRC_BT_SCBD 0x4
1335 #define COEX_BTINFO_SRC_H2C60 0x5
1336 #define COEX_BTINFO_SRC_MAX 0x6
1337
1338 #define COEX_INFO_FTP BIT(7)
1339 #define COEX_INFO_A2DP BIT(6)
1340 #define COEX_INFO_HID BIT(5)
1341 #define COEX_INFO_SCO_BUSY BIT(4)
1342 #define COEX_INFO_ACL_BUSY BIT(3)
1343 #define COEX_INFO_INQ_PAGE BIT(2)
1344 #define COEX_INFO_SCO_ESCO BIT(1)
1345 #define COEX_INFO_CONNECTION BIT(0)
1346 #define COEX_BTINFO_LENGTH_MAX 10
1347 #define COEX_BTINFO_LENGTH 7
1348
1349 struct rtw_coex_stat {
1350 bool bt_disabled;
1351 bool bt_disabled_pre;
1352 bool bt_link_exist;
1353 bool bt_whck_test;
1354 bool bt_inq_page;
1355 bool bt_inq_remain;
1356 bool bt_inq;
1357 bool bt_page;
1358 bool bt_ble_voice;
1359 bool bt_ble_exist;
1360 bool bt_hfp_exist;
1361 bool bt_a2dp_exist;
1362 bool bt_hid_exist;
1363 bool bt_pan_exist; /* PAN or OPP */
1364 bool bt_opp_exist; /* OPP only */
1365 bool bt_acl_busy;
1366 bool bt_fix_2M;
1367 bool bt_setup_link;
1368 bool bt_multi_link;
1369 bool bt_multi_link_pre;
1370 bool bt_multi_link_remain;
1371 bool bt_a2dp_sink;
1372 bool bt_a2dp_active;
1373 bool bt_reenable;
1374 bool bt_ble_scan_en;
1375 bool bt_init_scan;
1376 bool bt_slave;
1377 bool bt_418_hid_exist;
1378 bool bt_ble_hid_exist;
1379 bool bt_mailbox_reply;
1380
1381 bool wl_under_lps;
1382 bool wl_under_ips;
1383 bool wl_hi_pri_task1;
1384 bool wl_hi_pri_task2;
1385 bool wl_force_lps_ctrl;
1386 bool wl_gl_busy;
1387 bool wl_linkscan_proc;
1388 bool wl_ps_state_fail;
1389 bool wl_tx_limit_en;
1390 bool wl_ampdu_limit_en;
1391 bool wl_connected;
1392 bool wl_slot_extend;
1393 bool wl_cck_lock;
1394 bool wl_cck_lock_pre;
1395 bool wl_cck_lock_ever;
1396 bool wl_connecting;
1397 bool wl_slot_toggle;
1398 bool wl_slot_toggle_change; /* if toggle to no-toggle */
1399
1400 u32 bt_supported_version;
1401 u32 bt_supported_feature;
1402 u32 hi_pri_tx;
1403 u32 hi_pri_rx;
1404 u32 lo_pri_tx;
1405 u32 lo_pri_rx;
1406 u32 patch_ver;
1407 u16 bt_reg_vendor_ae;
1408 u16 bt_reg_vendor_ac;
1409 s8 bt_rssi;
1410 u8 kt_ver;
1411 u8 gnt_workaround_state;
1412 u8 tdma_timer_base;
1413 u8 bt_profile_num;
1414 u8 bt_info_c2h[COEX_BTINFO_SRC_MAX][COEX_BTINFO_LENGTH_MAX];
1415 u8 bt_info_lb2;
1416 u8 bt_info_lb3;
1417 u8 bt_info_hb0;
1418 u8 bt_info_hb1;
1419 u8 bt_info_hb2;
1420 u8 bt_info_hb3;
1421 u8 bt_ble_scan_type;
1422 u8 bt_hid_pair_num;
1423 u8 bt_hid_slot;
1424 u8 bt_a2dp_bitpool;
1425 u8 bt_iqk_state;
1426
1427 u16 wl_beacon_interval;
1428 u8 wl_noisy_level;
1429 u8 wl_fw_dbg_info[10];
1430 u8 wl_fw_dbg_info_pre[10];
1431 u8 wl_rx_rate;
1432 u8 wl_tx_rate;
1433 u8 wl_rts_rx_rate;
1434 u8 wl_coex_mode;
1435 u8 wl_iot_peer;
1436 u8 ampdu_max_time;
1437 u8 wl_tput_dir;
1438
1439 u8 wl_toggle_para[6];
1440 u8 wl_toggle_interval;
1441
1442 u16 score_board;
1443 u16 retry_limit;
1444
1445 /* counters to record bt states */
1446 u32 cnt_bt[COEX_CNT_BT_MAX];
1447
1448 /* counters to record wifi states */
1449 u32 cnt_wl[COEX_CNT_WL_MAX];
1450
1451 /* counters to record bt c2h data */
1452 u32 cnt_bt_info_c2h[COEX_BTINFO_SRC_MAX];
1453
1454 u32 darfrc;
1455 u32 darfrch;
1456 };
1457
1458 struct rtw_coex {
1459 /* protects coex info request section */
1460 struct mutex mutex;
1461 struct sk_buff_head queue;
1462 wait_queue_head_t wait;
1463
1464 bool under_5g;
1465 bool stop_dm;
1466 bool freeze;
1467 bool freerun;
1468 bool wl_rf_off;
1469 bool manual_control;
1470
1471 struct rtw_coex_stat stat;
1472 struct rtw_coex_dm dm;
1473 struct rtw_coex_rfe rfe;
1474
1475 struct delayed_work bt_relink_work;
1476 struct delayed_work bt_reenable_work;
1477 struct delayed_work defreeze_work;
1478 struct delayed_work wl_remain_work;
1479 struct delayed_work bt_remain_work;
1480 struct delayed_work wl_connecting_work;
1481 struct delayed_work bt_multi_link_remain_work;
1482 struct delayed_work wl_ccklock_work;
1483
1484 };
1485
1486 #define DPK_RF_REG_NUM 7
1487 #define DPK_RF_PATH_NUM 2
1488 #define DPK_BB_REG_NUM 18
1489 #define DPK_CHANNEL_WIDTH_80 1
1490
1491 DECLARE_EWMA(thermal, 10, 4);
1492
1493 struct rtw_dpk_info {
1494 bool is_dpk_pwr_on;
1495 bool is_reload;
1496
1497 DECLARE_BITMAP(dpk_path_ok, DPK_RF_PATH_NUM);
1498
1499 u8 thermal_dpk[DPK_RF_PATH_NUM];
1500 struct ewma_thermal avg_thermal[DPK_RF_PATH_NUM];
1501
1502 u32 gnt_control;
1503 u32 gnt_value;
1504
1505 u8 result[RTW_RF_PATH_MAX];
1506 u8 dpk_txagc[RTW_RF_PATH_MAX];
1507 u32 coef[RTW_RF_PATH_MAX][20];
1508 u16 dpk_gs[RTW_RF_PATH_MAX];
1509 u8 thermal_dpk_delta[RTW_RF_PATH_MAX];
1510 u8 pre_pwsf[RTW_RF_PATH_MAX];
1511
1512 u8 dpk_band;
1513 u8 dpk_ch;
1514 u8 dpk_bw;
1515 };
1516
1517 struct rtw_phy_cck_pd_reg {
1518 u32 reg_pd;
1519 u32 mask_pd;
1520 u32 reg_cs;
1521 u32 mask_cs;
1522 };
1523
1524 #define DACK_MSBK_BACKUP_NUM 0xf
1525 #define DACK_DCK_BACKUP_NUM 0x2
1526
1527 struct rtw_swing_table {
1528 const u8 *p[RTW_RF_PATH_MAX];
1529 const u8 *n[RTW_RF_PATH_MAX];
1530 };
1531
1532 struct rtw_pkt_count {
1533 u16 num_bcn_pkt;
1534 u16 num_qry_pkt[DESC_RATE_MAX];
1535 };
1536
1537 DECLARE_EWMA(evm, 10, 4);
1538 DECLARE_EWMA(snr, 10, 4);
1539
1540 struct rtw_iqk_info {
1541 bool done;
1542 struct {
1543 u32 s1_x;
1544 u32 s1_y;
1545 u32 s0_x;
1546 u32 s0_y;
1547 } result;
1548 };
1549
1550 enum rtw_rf_band {
1551 RF_BAND_2G_CCK,
1552 RF_BAND_2G_OFDM,
1553 RF_BAND_5G_L,
1554 RF_BAND_5G_M,
1555 RF_BAND_5G_H,
1556 RF_BAND_MAX
1557 };
1558
1559 #define RF_GAIN_NUM 11
1560 #define RF_HW_OFFSET_NUM 10
1561
1562 struct rtw_gapk_info {
1563 u32 rf3f_bp[RF_BAND_MAX][RF_GAIN_NUM][RTW_RF_PATH_MAX];
1564 u32 rf3f_fs[RTW_RF_PATH_MAX][RF_GAIN_NUM];
1565 bool txgapk_bp_done;
1566 s8 offset[RF_GAIN_NUM][RTW_RF_PATH_MAX];
1567 s8 fianl_offset[RF_GAIN_NUM][RTW_RF_PATH_MAX];
1568 u8 read_txgain;
1569 u8 channel;
1570 };
1571
1572 #define EDCCA_TH_L2H_IDX 0
1573 #define EDCCA_TH_H2L_IDX 1
1574 #define EDCCA_TH_L2H_LB 48
1575 #define EDCCA_ADC_BACKOFF 12
1576 #define EDCCA_IGI_BASE 50
1577 #define EDCCA_IGI_L2H_DIFF 8
1578 #define EDCCA_L2H_H2L_DIFF 7
1579 #define EDCCA_L2H_H2L_DIFF_NORMAL 8
1580
1581 enum rtw_edcca_mode {
1582 RTW_EDCCA_NORMAL = 0,
1583 RTW_EDCCA_ADAPTIVITY = 1,
1584 };
1585
1586 struct rtw_cfo_track {
1587 bool is_adjust;
1588 u8 crystal_cap;
1589 s32 cfo_tail[RTW_RF_PATH_MAX];
1590 s32 cfo_cnt[RTW_RF_PATH_MAX];
1591 u32 packet_count;
1592 u32 packet_count_pre;
1593 };
1594
1595 #define RRSR_INIT_2G 0x15f
1596 #define RRSR_INIT_5G 0x150
1597
1598 enum rtw_dm_cap {
1599 RTW_DM_CAP_NA,
1600 RTW_DM_CAP_TXGAPK,
1601 RTW_DM_CAP_NUM
1602 };
1603
1604 struct rtw_dm_info {
1605 u32 cck_fa_cnt;
1606 u32 ofdm_fa_cnt;
1607 u32 total_fa_cnt;
1608 u32 cck_cca_cnt;
1609 u32 ofdm_cca_cnt;
1610 u32 total_cca_cnt;
1611
1612 u32 cck_ok_cnt;
1613 u32 cck_err_cnt;
1614 u32 ofdm_ok_cnt;
1615 u32 ofdm_err_cnt;
1616 u32 ht_ok_cnt;
1617 u32 ht_err_cnt;
1618 u32 vht_ok_cnt;
1619 u32 vht_err_cnt;
1620
1621 u8 min_rssi;
1622 u8 pre_min_rssi;
1623 u16 fa_history[4];
1624 u8 igi_history[4];
1625 u8 igi_bitmap;
1626 bool damping;
1627 u8 damping_cnt;
1628 u8 damping_rssi;
1629
1630 u8 cck_gi_u_bnd;
1631 u8 cck_gi_l_bnd;
1632
1633 u8 tx_rate;
1634 u32 rrsr_val_init;
1635 u32 rrsr_mask_min;
1636 u8 thermal_avg[RTW_RF_PATH_MAX];
1637 u8 thermal_meter_k;
1638 u8 thermal_meter_lck;
1639 s8 delta_power_index[RTW_RF_PATH_MAX];
1640 s8 delta_power_index_last[RTW_RF_PATH_MAX];
1641 u8 default_ofdm_index;
1642 bool pwr_trk_triggered;
1643 bool pwr_trk_init_trigger;
1644 struct ewma_thermal avg_thermal[RTW_RF_PATH_MAX];
1645 s8 txagc_remnant_cck;
1646 s8 txagc_remnant_ofdm;
1647
1648 /* backup dack results for each path and I/Q */
1649 u32 dack_adck[RTW_RF_PATH_MAX];
1650 u16 dack_msbk[RTW_RF_PATH_MAX][2][DACK_MSBK_BACKUP_NUM];
1651 u8 dack_dck[RTW_RF_PATH_MAX][2][DACK_DCK_BACKUP_NUM];
1652
1653 struct rtw_dpk_info dpk_info;
1654 struct rtw_cfo_track cfo_track;
1655
1656 /* [bandwidth 0:20M/1:40M][number of path] */
1657 u8 cck_pd_lv[2][RTW_RF_PATH_MAX];
1658 u32 cck_fa_avg;
1659 u8 cck_pd_default;
1660
1661 /* save the last rx phy status for debug */
1662 s8 rx_snr[RTW_RF_PATH_MAX];
1663 u8 rx_evm_dbm[RTW_RF_PATH_MAX];
1664 s16 cfo_tail[RTW_RF_PATH_MAX];
1665 u8 rssi[RTW_RF_PATH_MAX];
1666 u8 curr_rx_rate;
1667 struct rtw_pkt_count cur_pkt_count;
1668 struct rtw_pkt_count last_pkt_count;
1669 struct ewma_evm ewma_evm[RTW_EVM_NUM];
1670 struct ewma_snr ewma_snr[RTW_SNR_NUM];
1671
1672 u32 dm_flags; /* enum rtw_dm_cap */
1673 struct rtw_iqk_info iqk;
1674 struct rtw_gapk_info gapk;
1675 bool is_bt_iqk_timeout;
1676
1677 s8 l2h_th_ini;
1678 enum rtw_edcca_mode edcca_mode;
1679 u8 scan_density;
1680 };
1681
1682 struct rtw_efuse {
1683 u32 size;
1684 u32 physical_size;
1685 u32 logical_size;
1686 u32 protect_size;
1687
1688 u8 addr[ETH_ALEN];
1689 u8 channel_plan;
1690 u8 country_code[2];
1691 u8 rf_board_option;
1692 u8 rfe_option;
1693 u8 power_track_type;
1694 u8 thermal_meter[RTW_RF_PATH_MAX];
1695 u8 thermal_meter_k;
1696 u8 crystal_cap;
1697 u8 ant_div_cfg;
1698 u8 ant_div_type;
1699 u8 regd;
1700 u8 afe;
1701
1702 u8 lna_type_2g;
1703 u8 lna_type_5g;
1704 u8 glna_type;
1705 u8 alna_type;
1706 bool ext_lna_2g;
1707 bool ext_lna_5g;
1708 u8 pa_type_2g;
1709 u8 pa_type_5g;
1710 u8 gpa_type;
1711 u8 apa_type;
1712 bool ext_pa_2g;
1713 bool ext_pa_5g;
1714 u8 tx_bb_swing_setting_2g;
1715 u8 tx_bb_swing_setting_5g;
1716
1717 bool btcoex;
1718 /* bt share antenna with wifi */
1719 bool share_ant;
1720 u8 bt_setting;
1721
1722 struct {
1723 u8 hci;
1724 u8 bw;
1725 u8 ptcl;
1726 u8 nss;
1727 u8 ant_num;
1728 } hw_cap;
1729
1730 struct rtw_txpwr_idx txpwr_idx_table[4];
1731 };
1732
1733 struct rtw_phy_cond {
1734 #ifdef __LITTLE_ENDIAN
1735 u32 rfe:8;
1736 u32 intf:4;
1737 u32 pkg:4;
1738 u32 plat:4;
1739 u32 intf_rsvd:4;
1740 u32 cut:4;
1741 u32 branch:2;
1742 u32 neg:1;
1743 u32 pos:1;
1744 #else
1745 u32 pos:1;
1746 u32 neg:1;
1747 u32 branch:2;
1748 u32 cut:4;
1749 u32 intf_rsvd:4;
1750 u32 plat:4;
1751 u32 pkg:4;
1752 u32 intf:4;
1753 u32 rfe:8;
1754 #endif
1755 /* for intf:4 */
1756 #define INTF_PCIE BIT(0)
1757 #define INTF_USB BIT(1)
1758 #define INTF_SDIO BIT(2)
1759 /* for branch:2 */
1760 #define BRANCH_IF 0
1761 #define BRANCH_ELIF 1
1762 #define BRANCH_ELSE 2
1763 #define BRANCH_ENDIF 3
1764 };
1765
1766 struct rtw_fifo_conf {
1767 /* tx fifo information */
1768 u16 rsvd_boundary;
1769 u16 rsvd_pg_num;
1770 u16 rsvd_drv_pg_num;
1771 u16 txff_pg_num;
1772 u16 acq_pg_num;
1773 u16 rsvd_drv_addr;
1774 u16 rsvd_h2c_info_addr;
1775 u16 rsvd_h2c_sta_info_addr;
1776 u16 rsvd_h2cq_addr;
1777 u16 rsvd_cpu_instr_addr;
1778 u16 rsvd_fw_txbuf_addr;
1779 u16 rsvd_csibuf_addr;
1780 const struct rtw_rqpn *rqpn;
1781 };
1782
1783 struct rtw_fwcd_desc {
1784 u32 size;
1785 u8 *next;
1786 u8 *data;
1787 };
1788
1789 struct rtw_fwcd_segs {
1790 const u32 *segs;
1791 u8 num;
1792 };
1793
1794 #define FW_CD_TYPE 0xffff
1795 #define FW_CD_LEN 4
1796 #define FW_CD_VAL 0xaabbccdd
1797 struct rtw_fw_state {
1798 const struct firmware *firmware;
1799 struct rtw_dev *rtwdev;
1800 struct completion completion;
1801 struct rtw_fwcd_desc fwcd_desc;
1802 u16 version;
1803 u8 sub_version;
1804 u8 sub_index;
1805 u16 h2c_version;
1806 u32 feature;
1807 };
1808
1809 struct rtw_hal {
1810 u32 rcr;
1811
1812 u32 chip_version;
1813 u8 cut_version;
1814 u8 mp_chip;
1815 u8 oem_id;
1816 struct rtw_phy_cond phy_cond;
1817
1818 u8 ps_mode;
1819 u8 current_channel;
1820 u8 current_band_width;
1821 u8 current_band_type;
1822
1823 /* center channel for different available bandwidth,
1824 * val of (bw > current_band_width) is invalid
1825 */
1826 u8 cch_by_bw[RTW_MAX_CHANNEL_WIDTH + 1];
1827
1828 u8 sec_ch_offset;
1829 u8 rf_type;
1830 u8 rf_path_num;
1831 u8 rf_phy_num;
1832 u32 antenna_tx;
1833 u32 antenna_rx;
1834 u8 bfee_sts_cap;
1835
1836 /* protect tx power section */
1837 struct mutex tx_power_mutex;
1838 s8 tx_pwr_by_rate_offset_2g[RTW_RF_PATH_MAX]
1839 [DESC_RATE_MAX];
1840 s8 tx_pwr_by_rate_offset_5g[RTW_RF_PATH_MAX]
1841 [DESC_RATE_MAX];
1842 s8 tx_pwr_by_rate_base_2g[RTW_RF_PATH_MAX]
1843 [RTW_RATE_SECTION_MAX];
1844 s8 tx_pwr_by_rate_base_5g[RTW_RF_PATH_MAX]
1845 [RTW_RATE_SECTION_MAX];
1846 s8 tx_pwr_limit_2g[RTW_REGD_MAX]
1847 [RTW_CHANNEL_WIDTH_MAX]
1848 [RTW_RATE_SECTION_MAX]
1849 [RTW_MAX_CHANNEL_NUM_2G];
1850 s8 tx_pwr_limit_5g[RTW_REGD_MAX]
1851 [RTW_CHANNEL_WIDTH_MAX]
1852 [RTW_RATE_SECTION_MAX]
1853 [RTW_MAX_CHANNEL_NUM_5G];
1854 s8 tx_pwr_tbl[RTW_RF_PATH_MAX]
1855 [DESC_RATE_MAX];
1856 };
1857
1858 struct rtw_path_div {
1859 enum rtw_bb_path current_tx_path;
1860 u32 path_a_sum;
1861 u32 path_b_sum;
1862 u16 path_a_cnt;
1863 u16 path_b_cnt;
1864 };
1865
1866 struct rtw_dev {
1867 struct ieee80211_hw *hw;
1868 struct device *dev;
1869
1870 struct rtw_hci hci;
1871
1872 struct rtw_chip_info *chip;
1873 struct rtw_hal hal;
1874 struct rtw_fifo_conf fifo;
1875 struct rtw_fw_state fw;
1876 struct rtw_efuse efuse;
1877 struct rtw_sec_desc sec;
1878 struct rtw_traffic_stats stats;
1879 struct rtw_regd regd;
1880 struct rtw_bf_info bf_info;
1881
1882 struct rtw_dm_info dm_info;
1883 struct rtw_coex coex;
1884
1885 /* ensures exclusive access from mac80211 callbacks */
1886 struct mutex mutex;
1887
1888 /* read/write rf register */
1889 spinlock_t rf_lock;
1890
1891 /* watch dog every 2 sec */
1892 struct delayed_work watch_dog_work;
1893 u32 watch_dog_cnt;
1894
1895 struct list_head rsvd_page_list;
1896
1897 /* c2h cmd queue & handler work */
1898 struct sk_buff_head c2h_queue;
1899 struct work_struct c2h_work;
1900 struct work_struct fw_recovery_work;
1901
1902 /* used to protect txqs list */
1903 spinlock_t txq_lock;
1904 struct list_head txqs;
1905 struct workqueue_struct *tx_wq;
1906 struct work_struct tx_work;
1907 struct work_struct ba_work;
1908
1909 struct rtw_tx_report tx_report;
1910
1911 struct {
1912 /* incicate the mail box to use with fw */
1913 u8 last_box_num;
1914 /* protect to send h2c to fw */
1915 spinlock_t lock;
1916 u32 seq;
1917 } h2c;
1918
1919 /* lps power state & handler work */
1920 struct rtw_lps_conf lps_conf;
1921 bool ps_enabled;
1922 bool beacon_loss;
1923 struct completion lps_leave_check;
1924
1925 struct dentry *debugfs;
1926
1927 u8 sta_cnt;
1928 u32 rts_threshold;
1929
1930 DECLARE_BITMAP(mac_id_map, RTW_MAX_MAC_ID_NUM);
1931 DECLARE_BITMAP(flags, NUM_OF_RTW_FLAGS);
1932
1933 u8 mp_mode;
1934 struct rtw_path_div dm_path_div;
1935
1936 struct rtw_fw_state wow_fw;
1937 struct rtw_wow_param wow;
1938
1939 bool need_rfk;
1940 struct completion fw_scan_density;
1941
1942 /* hci related data, must be last */
1943 u8 priv[] __aligned(sizeof(void *));
1944 };
1945
1946 #include "hci.h"
1947
rtw_is_assoc(struct rtw_dev * rtwdev)1948 static inline bool rtw_is_assoc(struct rtw_dev *rtwdev)
1949 {
1950 return !!rtwdev->sta_cnt;
1951 }
1952
rtwtxq_to_txq(struct rtw_txq * rtwtxq)1953 static inline struct ieee80211_txq *rtwtxq_to_txq(struct rtw_txq *rtwtxq)
1954 {
1955 void *p = rtwtxq;
1956
1957 return container_of(p, struct ieee80211_txq, drv_priv);
1958 }
1959
rtwvif_to_vif(struct rtw_vif * rtwvif)1960 static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw_vif *rtwvif)
1961 {
1962 void *p = rtwvif;
1963
1964 return container_of(p, struct ieee80211_vif, drv_priv);
1965 }
1966
rtw_ssid_equal(struct cfg80211_ssid * a,struct cfg80211_ssid * b)1967 static inline bool rtw_ssid_equal(struct cfg80211_ssid *a,
1968 struct cfg80211_ssid *b)
1969 {
1970 if (!a || !b || a->ssid_len != b->ssid_len)
1971 return false;
1972
1973 if (memcmp(a->ssid, b->ssid, a->ssid_len))
1974 return false;
1975
1976 return true;
1977 }
1978
rtw_chip_efuse_grant_on(struct rtw_dev * rtwdev)1979 static inline void rtw_chip_efuse_grant_on(struct rtw_dev *rtwdev)
1980 {
1981 if (rtwdev->chip->ops->efuse_grant)
1982 rtwdev->chip->ops->efuse_grant(rtwdev, true);
1983 }
1984
rtw_chip_efuse_grant_off(struct rtw_dev * rtwdev)1985 static inline void rtw_chip_efuse_grant_off(struct rtw_dev *rtwdev)
1986 {
1987 if (rtwdev->chip->ops->efuse_grant)
1988 rtwdev->chip->ops->efuse_grant(rtwdev, false);
1989 }
1990
rtw_chip_wcpu_11n(struct rtw_dev * rtwdev)1991 static inline bool rtw_chip_wcpu_11n(struct rtw_dev *rtwdev)
1992 {
1993 return rtwdev->chip->wlan_cpu == RTW_WCPU_11N;
1994 }
1995
rtw_chip_wcpu_11ac(struct rtw_dev * rtwdev)1996 static inline bool rtw_chip_wcpu_11ac(struct rtw_dev *rtwdev)
1997 {
1998 return rtwdev->chip->wlan_cpu == RTW_WCPU_11AC;
1999 }
2000
rtw_chip_has_rx_ldpc(struct rtw_dev * rtwdev)2001 static inline bool rtw_chip_has_rx_ldpc(struct rtw_dev *rtwdev)
2002 {
2003 return rtwdev->chip->rx_ldpc;
2004 }
2005
rtw_chip_has_tx_stbc(struct rtw_dev * rtwdev)2006 static inline bool rtw_chip_has_tx_stbc(struct rtw_dev *rtwdev)
2007 {
2008 return rtwdev->chip->tx_stbc;
2009 }
2010
rtw_release_macid(struct rtw_dev * rtwdev,u8 mac_id)2011 static inline void rtw_release_macid(struct rtw_dev *rtwdev, u8 mac_id)
2012 {
2013 clear_bit(mac_id, rtwdev->mac_id_map);
2014 }
2015
rtw_chip_dump_fw_crash(struct rtw_dev * rtwdev)2016 static inline int rtw_chip_dump_fw_crash(struct rtw_dev *rtwdev)
2017 {
2018 if (rtwdev->chip->ops->dump_fw_crash)
2019 return rtwdev->chip->ops->dump_fw_crash(rtwdev);
2020
2021 return 0;
2022 }
2023
2024 void rtw_get_channel_params(struct cfg80211_chan_def *chandef,
2025 struct rtw_channel_params *ch_param);
2026 bool check_hw_ready(struct rtw_dev *rtwdev, u32 addr, u32 mask, u32 target);
2027 bool ltecoex_read_reg(struct rtw_dev *rtwdev, u16 offset, u32 *val);
2028 bool ltecoex_reg_write(struct rtw_dev *rtwdev, u16 offset, u32 value);
2029 void rtw_restore_reg(struct rtw_dev *rtwdev,
2030 struct rtw_backup_info *bckp, u32 num);
2031 void rtw_desc_to_mcsrate(u16 rate, u8 *mcs, u8 *nss);
2032 void rtw_set_channel(struct rtw_dev *rtwdev);
2033 void rtw_chip_prepare_tx(struct rtw_dev *rtwdev);
2034 void rtw_vif_port_config(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif,
2035 u32 config);
2036 void rtw_tx_report_purge_timer(struct timer_list *t);
2037 void rtw_update_sta_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si);
2038 int rtw_core_start(struct rtw_dev *rtwdev);
2039 void rtw_core_stop(struct rtw_dev *rtwdev);
2040 int rtw_chip_info_setup(struct rtw_dev *rtwdev);
2041 int rtw_core_init(struct rtw_dev *rtwdev);
2042 void rtw_core_deinit(struct rtw_dev *rtwdev);
2043 int rtw_register_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw);
2044 void rtw_unregister_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw);
2045 u16 rtw_desc_to_bitrate(u8 desc_rate);
2046 void rtw_vif_assoc_changed(struct rtw_vif *rtwvif,
2047 struct ieee80211_bss_conf *conf);
2048 int rtw_sta_add(struct rtw_dev *rtwdev, struct ieee80211_sta *sta,
2049 struct ieee80211_vif *vif);
2050 void rtw_sta_remove(struct rtw_dev *rtwdev, struct ieee80211_sta *sta,
2051 bool fw_exist);
2052 void rtw_fw_recovery(struct rtw_dev *rtwdev);
2053 void rtw_core_fw_scan_notify(struct rtw_dev *rtwdev, bool start);
2054 int rtw_dump_fw(struct rtw_dev *rtwdev, const u32 ocp_src, u32 size,
2055 u32 fwcd_item);
2056 int rtw_dump_reg(struct rtw_dev *rtwdev, const u32 addr, const u32 size);
2057
2058 #endif
2059