1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * APM X-Gene PCIe Driver
4 *
5 * Copyright (c) 2014 Applied Micro Circuits Corporation.
6 *
7 * Author: Tanmay Inamdar <tinamdar@apm.com>.
8 */
9 #include <linux/clk.h>
10 #include <linux/delay.h>
11 #include <linux/io.h>
12 #include <linux/jiffies.h>
13 #include <linux/memblock.h>
14 #include <linux/init.h>
15 #include <linux/of.h>
16 #include <linux/of_address.h>
17 #include <linux/of_irq.h>
18 #include <linux/of_pci.h>
19 #include <linux/pci.h>
20 #include <linux/pci-acpi.h>
21 #include <linux/pci-ecam.h>
22 #include <linux/platform_device.h>
23 #include <linux/slab.h>
24
25 #include "../pci.h"
26
27 #define PCIECORE_CTLANDSTATUS 0x50
28 #define PIM1_1L 0x80
29 #define IBAR2 0x98
30 #define IR2MSK 0x9c
31 #define PIM2_1L 0xa0
32 #define IBAR3L 0xb4
33 #define IR3MSKL 0xbc
34 #define PIM3_1L 0xc4
35 #define OMR1BARL 0x100
36 #define OMR2BARL 0x118
37 #define OMR3BARL 0x130
38 #define CFGBARL 0x154
39 #define CFGBARH 0x158
40 #define CFGCTL 0x15c
41 #define RTDID 0x160
42 #define BRIDGE_CFG_0 0x2000
43 #define BRIDGE_CFG_4 0x2010
44 #define BRIDGE_STATUS_0 0x2600
45
46 #define LINK_UP_MASK 0x00000100
47 #define AXI_EP_CFG_ACCESS 0x10000
48 #define EN_COHERENCY 0xF0000000
49 #define EN_REG 0x00000001
50 #define OB_LO_IO 0x00000002
51 #define XGENE_PCIE_DEVICEID 0xE004
52 #define SZ_1T (SZ_1G*1024ULL)
53 #define PIPE_PHY_RATE_RD(src) ((0xc000 & (u32)(src)) >> 0xe)
54
55 #define XGENE_V1_PCI_EXP_CAP 0x40
56
57 /* PCIe IP version */
58 #define XGENE_PCIE_IP_VER_UNKN 0
59 #define XGENE_PCIE_IP_VER_1 1
60 #define XGENE_PCIE_IP_VER_2 2
61
62 #if defined(CONFIG_PCI_XGENE) || (defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS))
63 struct xgene_pcie_port {
64 struct device_node *node;
65 struct device *dev;
66 struct clk *clk;
67 void __iomem *csr_base;
68 void __iomem *cfg_base;
69 unsigned long cfg_addr;
70 bool link_up;
71 u32 version;
72 };
73
xgene_pcie_readl(struct xgene_pcie_port * port,u32 reg)74 static u32 xgene_pcie_readl(struct xgene_pcie_port *port, u32 reg)
75 {
76 return readl(port->csr_base + reg);
77 }
78
xgene_pcie_writel(struct xgene_pcie_port * port,u32 reg,u32 val)79 static void xgene_pcie_writel(struct xgene_pcie_port *port, u32 reg, u32 val)
80 {
81 writel(val, port->csr_base + reg);
82 }
83
pcie_bar_low_val(u32 addr,u32 flags)84 static inline u32 pcie_bar_low_val(u32 addr, u32 flags)
85 {
86 return (addr & PCI_BASE_ADDRESS_MEM_MASK) | flags;
87 }
88
pcie_bus_to_port(struct pci_bus * bus)89 static inline struct xgene_pcie_port *pcie_bus_to_port(struct pci_bus *bus)
90 {
91 struct pci_config_window *cfg;
92
93 if (acpi_disabled)
94 return (struct xgene_pcie_port *)(bus->sysdata);
95
96 cfg = bus->sysdata;
97 return (struct xgene_pcie_port *)(cfg->priv);
98 }
99
100 /*
101 * When the address bit [17:16] is 2'b01, the Configuration access will be
102 * treated as Type 1 and it will be forwarded to external PCIe device.
103 */
xgene_pcie_get_cfg_base(struct pci_bus * bus)104 static void __iomem *xgene_pcie_get_cfg_base(struct pci_bus *bus)
105 {
106 struct xgene_pcie_port *port = pcie_bus_to_port(bus);
107
108 if (bus->number >= (bus->primary + 1))
109 return port->cfg_base + AXI_EP_CFG_ACCESS;
110
111 return port->cfg_base;
112 }
113
114 /*
115 * For Configuration request, RTDID register is used as Bus Number,
116 * Device Number and Function number of the header fields.
117 */
xgene_pcie_set_rtdid_reg(struct pci_bus * bus,uint devfn)118 static void xgene_pcie_set_rtdid_reg(struct pci_bus *bus, uint devfn)
119 {
120 struct xgene_pcie_port *port = pcie_bus_to_port(bus);
121 unsigned int b, d, f;
122 u32 rtdid_val = 0;
123
124 b = bus->number;
125 d = PCI_SLOT(devfn);
126 f = PCI_FUNC(devfn);
127
128 if (!pci_is_root_bus(bus))
129 rtdid_val = (b << 8) | (d << 3) | f;
130
131 xgene_pcie_writel(port, RTDID, rtdid_val);
132 /* read the register back to ensure flush */
133 xgene_pcie_readl(port, RTDID);
134 }
135
136 /*
137 * X-Gene PCIe port uses BAR0-BAR1 of RC's configuration space as
138 * the translation from PCI bus to native BUS. Entire DDR region
139 * is mapped into PCIe space using these registers, so it can be
140 * reached by DMA from EP devices. The BAR0/1 of bridge should be
141 * hidden during enumeration to avoid the sizing and resource allocation
142 * by PCIe core.
143 */
xgene_pcie_hide_rc_bars(struct pci_bus * bus,int offset)144 static bool xgene_pcie_hide_rc_bars(struct pci_bus *bus, int offset)
145 {
146 if (pci_is_root_bus(bus) && ((offset == PCI_BASE_ADDRESS_0) ||
147 (offset == PCI_BASE_ADDRESS_1)))
148 return true;
149
150 return false;
151 }
152
xgene_pcie_map_bus(struct pci_bus * bus,unsigned int devfn,int offset)153 static void __iomem *xgene_pcie_map_bus(struct pci_bus *bus, unsigned int devfn,
154 int offset)
155 {
156 if ((pci_is_root_bus(bus) && devfn != 0) ||
157 xgene_pcie_hide_rc_bars(bus, offset))
158 return NULL;
159
160 xgene_pcie_set_rtdid_reg(bus, devfn);
161 return xgene_pcie_get_cfg_base(bus) + offset;
162 }
163
xgene_pcie_config_read32(struct pci_bus * bus,unsigned int devfn,int where,int size,u32 * val)164 static int xgene_pcie_config_read32(struct pci_bus *bus, unsigned int devfn,
165 int where, int size, u32 *val)
166 {
167 struct xgene_pcie_port *port = pcie_bus_to_port(bus);
168
169 if (pci_generic_config_read32(bus, devfn, where & ~0x3, 4, val) !=
170 PCIBIOS_SUCCESSFUL)
171 return PCIBIOS_DEVICE_NOT_FOUND;
172
173 /*
174 * The v1 controller has a bug in its Configuration Request
175 * Retry Status (CRS) logic: when CRS Software Visibility is
176 * enabled and we read the Vendor and Device ID of a non-existent
177 * device, the controller fabricates return data of 0xFFFF0001
178 * ("device exists but is not ready") instead of 0xFFFFFFFF
179 * ("device does not exist"). This causes the PCI core to retry
180 * the read until it times out. Avoid this by not claiming to
181 * support CRS SV.
182 */
183 if (pci_is_root_bus(bus) && (port->version == XGENE_PCIE_IP_VER_1) &&
184 ((where & ~0x3) == XGENE_V1_PCI_EXP_CAP + PCI_EXP_RTCTL))
185 *val &= ~(PCI_EXP_RTCAP_CRSVIS << 16);
186
187 if (size <= 2)
188 *val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1);
189
190 return PCIBIOS_SUCCESSFUL;
191 }
192 #endif
193
194 #if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)
xgene_get_csr_resource(struct acpi_device * adev,struct resource * res)195 static int xgene_get_csr_resource(struct acpi_device *adev,
196 struct resource *res)
197 {
198 struct device *dev = &adev->dev;
199 struct resource_entry *entry;
200 struct list_head list;
201 unsigned long flags;
202 int ret;
203
204 INIT_LIST_HEAD(&list);
205 flags = IORESOURCE_MEM;
206 ret = acpi_dev_get_resources(adev, &list,
207 acpi_dev_filter_resource_type_cb,
208 (void *) flags);
209 if (ret < 0) {
210 dev_err(dev, "failed to parse _CRS method, error code %d\n",
211 ret);
212 return ret;
213 }
214
215 if (ret == 0) {
216 dev_err(dev, "no IO and memory resources present in _CRS\n");
217 return -EINVAL;
218 }
219
220 entry = list_first_entry(&list, struct resource_entry, node);
221 *res = *entry->res;
222 acpi_dev_free_resource_list(&list);
223 return 0;
224 }
225
xgene_pcie_ecam_init(struct pci_config_window * cfg,u32 ipversion)226 static int xgene_pcie_ecam_init(struct pci_config_window *cfg, u32 ipversion)
227 {
228 struct device *dev = cfg->parent;
229 struct acpi_device *adev = to_acpi_device(dev);
230 struct xgene_pcie_port *port;
231 struct resource csr;
232 int ret;
233
234 port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
235 if (!port)
236 return -ENOMEM;
237
238 ret = xgene_get_csr_resource(adev, &csr);
239 if (ret) {
240 dev_err(dev, "can't get CSR resource\n");
241 return ret;
242 }
243 port->csr_base = devm_pci_remap_cfg_resource(dev, &csr);
244 if (IS_ERR(port->csr_base))
245 return PTR_ERR(port->csr_base);
246
247 port->cfg_base = cfg->win;
248 port->version = ipversion;
249
250 cfg->priv = port;
251 return 0;
252 }
253
xgene_v1_pcie_ecam_init(struct pci_config_window * cfg)254 static int xgene_v1_pcie_ecam_init(struct pci_config_window *cfg)
255 {
256 return xgene_pcie_ecam_init(cfg, XGENE_PCIE_IP_VER_1);
257 }
258
259 const struct pci_ecam_ops xgene_v1_pcie_ecam_ops = {
260 .init = xgene_v1_pcie_ecam_init,
261 .pci_ops = {
262 .map_bus = xgene_pcie_map_bus,
263 .read = xgene_pcie_config_read32,
264 .write = pci_generic_config_write,
265 }
266 };
267
xgene_v2_pcie_ecam_init(struct pci_config_window * cfg)268 static int xgene_v2_pcie_ecam_init(struct pci_config_window *cfg)
269 {
270 return xgene_pcie_ecam_init(cfg, XGENE_PCIE_IP_VER_2);
271 }
272
273 const struct pci_ecam_ops xgene_v2_pcie_ecam_ops = {
274 .init = xgene_v2_pcie_ecam_init,
275 .pci_ops = {
276 .map_bus = xgene_pcie_map_bus,
277 .read = xgene_pcie_config_read32,
278 .write = pci_generic_config_write,
279 }
280 };
281 #endif
282
283 #if defined(CONFIG_PCI_XGENE)
xgene_pcie_set_ib_mask(struct xgene_pcie_port * port,u32 addr,u32 flags,u64 size)284 static u64 xgene_pcie_set_ib_mask(struct xgene_pcie_port *port, u32 addr,
285 u32 flags, u64 size)
286 {
287 u64 mask = (~(size - 1) & PCI_BASE_ADDRESS_MEM_MASK) | flags;
288 u32 val32 = 0;
289 u32 val;
290
291 val32 = xgene_pcie_readl(port, addr);
292 val = (val32 & 0x0000ffff) | (lower_32_bits(mask) << 16);
293 xgene_pcie_writel(port, addr, val);
294
295 val32 = xgene_pcie_readl(port, addr + 0x04);
296 val = (val32 & 0xffff0000) | (lower_32_bits(mask) >> 16);
297 xgene_pcie_writel(port, addr + 0x04, val);
298
299 val32 = xgene_pcie_readl(port, addr + 0x04);
300 val = (val32 & 0x0000ffff) | (upper_32_bits(mask) << 16);
301 xgene_pcie_writel(port, addr + 0x04, val);
302
303 val32 = xgene_pcie_readl(port, addr + 0x08);
304 val = (val32 & 0xffff0000) | (upper_32_bits(mask) >> 16);
305 xgene_pcie_writel(port, addr + 0x08, val);
306
307 return mask;
308 }
309
xgene_pcie_linkup(struct xgene_pcie_port * port,u32 * lanes,u32 * speed)310 static void xgene_pcie_linkup(struct xgene_pcie_port *port,
311 u32 *lanes, u32 *speed)
312 {
313 u32 val32;
314
315 port->link_up = false;
316 val32 = xgene_pcie_readl(port, PCIECORE_CTLANDSTATUS);
317 if (val32 & LINK_UP_MASK) {
318 port->link_up = true;
319 *speed = PIPE_PHY_RATE_RD(val32);
320 val32 = xgene_pcie_readl(port, BRIDGE_STATUS_0);
321 *lanes = val32 >> 26;
322 }
323 }
324
xgene_pcie_init_port(struct xgene_pcie_port * port)325 static int xgene_pcie_init_port(struct xgene_pcie_port *port)
326 {
327 struct device *dev = port->dev;
328 int rc;
329
330 port->clk = clk_get(dev, NULL);
331 if (IS_ERR(port->clk)) {
332 dev_err(dev, "clock not available\n");
333 return -ENODEV;
334 }
335
336 rc = clk_prepare_enable(port->clk);
337 if (rc) {
338 dev_err(dev, "clock enable failed\n");
339 return rc;
340 }
341
342 return 0;
343 }
344
xgene_pcie_map_reg(struct xgene_pcie_port * port,struct platform_device * pdev)345 static int xgene_pcie_map_reg(struct xgene_pcie_port *port,
346 struct platform_device *pdev)
347 {
348 struct device *dev = port->dev;
349 struct resource *res;
350
351 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csr");
352 port->csr_base = devm_pci_remap_cfg_resource(dev, res);
353 if (IS_ERR(port->csr_base))
354 return PTR_ERR(port->csr_base);
355
356 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");
357 port->cfg_base = devm_ioremap_resource(dev, res);
358 if (IS_ERR(port->cfg_base))
359 return PTR_ERR(port->cfg_base);
360 port->cfg_addr = res->start;
361
362 return 0;
363 }
364
xgene_pcie_setup_ob_reg(struct xgene_pcie_port * port,struct resource * res,u32 offset,u64 cpu_addr,u64 pci_addr)365 static void xgene_pcie_setup_ob_reg(struct xgene_pcie_port *port,
366 struct resource *res, u32 offset,
367 u64 cpu_addr, u64 pci_addr)
368 {
369 struct device *dev = port->dev;
370 resource_size_t size = resource_size(res);
371 u64 restype = resource_type(res);
372 u64 mask = 0;
373 u32 min_size;
374 u32 flag = EN_REG;
375
376 if (restype == IORESOURCE_MEM) {
377 min_size = SZ_128M;
378 } else {
379 min_size = 128;
380 flag |= OB_LO_IO;
381 }
382
383 if (size >= min_size)
384 mask = ~(size - 1) | flag;
385 else
386 dev_warn(dev, "res size 0x%llx less than minimum 0x%x\n",
387 (u64)size, min_size);
388
389 xgene_pcie_writel(port, offset, lower_32_bits(cpu_addr));
390 xgene_pcie_writel(port, offset + 0x04, upper_32_bits(cpu_addr));
391 xgene_pcie_writel(port, offset + 0x08, lower_32_bits(mask));
392 xgene_pcie_writel(port, offset + 0x0c, upper_32_bits(mask));
393 xgene_pcie_writel(port, offset + 0x10, lower_32_bits(pci_addr));
394 xgene_pcie_writel(port, offset + 0x14, upper_32_bits(pci_addr));
395 }
396
xgene_pcie_setup_cfg_reg(struct xgene_pcie_port * port)397 static void xgene_pcie_setup_cfg_reg(struct xgene_pcie_port *port)
398 {
399 u64 addr = port->cfg_addr;
400
401 xgene_pcie_writel(port, CFGBARL, lower_32_bits(addr));
402 xgene_pcie_writel(port, CFGBARH, upper_32_bits(addr));
403 xgene_pcie_writel(port, CFGCTL, EN_REG);
404 }
405
xgene_pcie_map_ranges(struct xgene_pcie_port * port)406 static int xgene_pcie_map_ranges(struct xgene_pcie_port *port)
407 {
408 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(port);
409 struct resource_entry *window;
410 struct device *dev = port->dev;
411
412 resource_list_for_each_entry(window, &bridge->windows) {
413 struct resource *res = window->res;
414 u64 restype = resource_type(res);
415
416 dev_dbg(dev, "%pR\n", res);
417
418 switch (restype) {
419 case IORESOURCE_IO:
420 xgene_pcie_setup_ob_reg(port, res, OMR3BARL,
421 pci_pio_to_address(res->start),
422 res->start - window->offset);
423 break;
424 case IORESOURCE_MEM:
425 if (res->flags & IORESOURCE_PREFETCH)
426 xgene_pcie_setup_ob_reg(port, res, OMR2BARL,
427 res->start,
428 res->start -
429 window->offset);
430 else
431 xgene_pcie_setup_ob_reg(port, res, OMR1BARL,
432 res->start,
433 res->start -
434 window->offset);
435 break;
436 case IORESOURCE_BUS:
437 break;
438 default:
439 dev_err(dev, "invalid resource %pR\n", res);
440 return -EINVAL;
441 }
442 }
443 xgene_pcie_setup_cfg_reg(port);
444 return 0;
445 }
446
xgene_pcie_setup_pims(struct xgene_pcie_port * port,u32 pim_reg,u64 pim,u64 size)447 static void xgene_pcie_setup_pims(struct xgene_pcie_port *port, u32 pim_reg,
448 u64 pim, u64 size)
449 {
450 xgene_pcie_writel(port, pim_reg, lower_32_bits(pim));
451 xgene_pcie_writel(port, pim_reg + 0x04,
452 upper_32_bits(pim) | EN_COHERENCY);
453 xgene_pcie_writel(port, pim_reg + 0x10, lower_32_bits(size));
454 xgene_pcie_writel(port, pim_reg + 0x14, upper_32_bits(size));
455 }
456
457 /*
458 * X-Gene PCIe support maximum 3 inbound memory regions
459 * This function helps to select a region based on size of region
460 */
xgene_pcie_select_ib_reg(u8 * ib_reg_mask,u64 size)461 static int xgene_pcie_select_ib_reg(u8 *ib_reg_mask, u64 size)
462 {
463 if ((size > 4) && (size < SZ_16M) && !(*ib_reg_mask & (1 << 1))) {
464 *ib_reg_mask |= (1 << 1);
465 return 1;
466 }
467
468 if ((size > SZ_1K) && (size < SZ_1T) && !(*ib_reg_mask & (1 << 0))) {
469 *ib_reg_mask |= (1 << 0);
470 return 0;
471 }
472
473 if ((size > SZ_1M) && (size < SZ_1T) && !(*ib_reg_mask & (1 << 2))) {
474 *ib_reg_mask |= (1 << 2);
475 return 2;
476 }
477
478 return -EINVAL;
479 }
480
xgene_pcie_setup_ib_reg(struct xgene_pcie_port * port,struct resource_entry * entry,u8 * ib_reg_mask)481 static void xgene_pcie_setup_ib_reg(struct xgene_pcie_port *port,
482 struct resource_entry *entry,
483 u8 *ib_reg_mask)
484 {
485 void __iomem *cfg_base = port->cfg_base;
486 struct device *dev = port->dev;
487 void __iomem *bar_addr;
488 u32 pim_reg;
489 u64 cpu_addr = entry->res->start;
490 u64 pci_addr = cpu_addr - entry->offset;
491 u64 size = resource_size(entry->res);
492 u64 mask = ~(size - 1) | EN_REG;
493 u32 flags = PCI_BASE_ADDRESS_MEM_TYPE_64;
494 u32 bar_low;
495 int region;
496
497 region = xgene_pcie_select_ib_reg(ib_reg_mask, size);
498 if (region < 0) {
499 dev_warn(dev, "invalid pcie dma-range config\n");
500 return;
501 }
502
503 if (entry->res->flags & IORESOURCE_PREFETCH)
504 flags |= PCI_BASE_ADDRESS_MEM_PREFETCH;
505
506 bar_low = pcie_bar_low_val((u32)cpu_addr, flags);
507 switch (region) {
508 case 0:
509 xgene_pcie_set_ib_mask(port, BRIDGE_CFG_4, flags, size);
510 bar_addr = cfg_base + PCI_BASE_ADDRESS_0;
511 writel(bar_low, bar_addr);
512 writel(upper_32_bits(cpu_addr), bar_addr + 0x4);
513 pim_reg = PIM1_1L;
514 break;
515 case 1:
516 xgene_pcie_writel(port, IBAR2, bar_low);
517 xgene_pcie_writel(port, IR2MSK, lower_32_bits(mask));
518 pim_reg = PIM2_1L;
519 break;
520 case 2:
521 xgene_pcie_writel(port, IBAR3L, bar_low);
522 xgene_pcie_writel(port, IBAR3L + 0x4, upper_32_bits(cpu_addr));
523 xgene_pcie_writel(port, IR3MSKL, lower_32_bits(mask));
524 xgene_pcie_writel(port, IR3MSKL + 0x4, upper_32_bits(mask));
525 pim_reg = PIM3_1L;
526 break;
527 }
528
529 xgene_pcie_setup_pims(port, pim_reg, pci_addr, ~(size - 1));
530 }
531
xgene_pcie_parse_map_dma_ranges(struct xgene_pcie_port * port)532 static int xgene_pcie_parse_map_dma_ranges(struct xgene_pcie_port *port)
533 {
534 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(port);
535 struct resource_entry *entry;
536 u8 ib_reg_mask = 0;
537
538 resource_list_for_each_entry(entry, &bridge->dma_ranges)
539 xgene_pcie_setup_ib_reg(port, entry, &ib_reg_mask);
540
541 return 0;
542 }
543
544 /* clear BAR configuration which was done by firmware */
xgene_pcie_clear_config(struct xgene_pcie_port * port)545 static void xgene_pcie_clear_config(struct xgene_pcie_port *port)
546 {
547 int i;
548
549 for (i = PIM1_1L; i <= CFGCTL; i += 4)
550 xgene_pcie_writel(port, i, 0);
551 }
552
xgene_pcie_setup(struct xgene_pcie_port * port)553 static int xgene_pcie_setup(struct xgene_pcie_port *port)
554 {
555 struct device *dev = port->dev;
556 u32 val, lanes = 0, speed = 0;
557 int ret;
558
559 xgene_pcie_clear_config(port);
560
561 /* setup the vendor and device IDs correctly */
562 val = (XGENE_PCIE_DEVICEID << 16) | PCI_VENDOR_ID_AMCC;
563 xgene_pcie_writel(port, BRIDGE_CFG_0, val);
564
565 ret = xgene_pcie_map_ranges(port);
566 if (ret)
567 return ret;
568
569 ret = xgene_pcie_parse_map_dma_ranges(port);
570 if (ret)
571 return ret;
572
573 xgene_pcie_linkup(port, &lanes, &speed);
574 if (!port->link_up)
575 dev_info(dev, "(rc) link down\n");
576 else
577 dev_info(dev, "(rc) x%d gen-%d link up\n", lanes, speed + 1);
578 return 0;
579 }
580
581 static struct pci_ops xgene_pcie_ops = {
582 .map_bus = xgene_pcie_map_bus,
583 .read = xgene_pcie_config_read32,
584 .write = pci_generic_config_write32,
585 };
586
xgene_pcie_probe(struct platform_device * pdev)587 static int xgene_pcie_probe(struct platform_device *pdev)
588 {
589 struct device *dev = &pdev->dev;
590 struct device_node *dn = dev->of_node;
591 struct xgene_pcie_port *port;
592 struct pci_host_bridge *bridge;
593 int ret;
594
595 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*port));
596 if (!bridge)
597 return -ENOMEM;
598
599 port = pci_host_bridge_priv(bridge);
600
601 port->node = of_node_get(dn);
602 port->dev = dev;
603
604 port->version = XGENE_PCIE_IP_VER_UNKN;
605 if (of_device_is_compatible(port->node, "apm,xgene-pcie"))
606 port->version = XGENE_PCIE_IP_VER_1;
607
608 ret = xgene_pcie_map_reg(port, pdev);
609 if (ret)
610 return ret;
611
612 ret = xgene_pcie_init_port(port);
613 if (ret)
614 return ret;
615
616 ret = xgene_pcie_setup(port);
617 if (ret)
618 return ret;
619
620 bridge->sysdata = port;
621 bridge->ops = &xgene_pcie_ops;
622
623 return pci_host_probe(bridge);
624 }
625
626 static const struct of_device_id xgene_pcie_match_table[] = {
627 {.compatible = "apm,xgene-pcie",},
628 {},
629 };
630
631 static struct platform_driver xgene_pcie_driver = {
632 .driver = {
633 .name = "xgene-pcie",
634 .of_match_table = of_match_ptr(xgene_pcie_match_table),
635 .suppress_bind_attrs = true,
636 },
637 .probe = xgene_pcie_probe,
638 };
639 builtin_platform_driver(xgene_pcie_driver);
640 #endif
641