1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef __SOC_MEDIATEK_MT8192_PM_DOMAINS_H 4 #define __SOC_MEDIATEK_MT8192_PM_DOMAINS_H 5 6 #include "mtk-pm-domains.h" 7 #include <dt-bindings/power/mt8192-power.h> 8 9 /* 10 * MT8192 power domain support 11 */ 12 13 static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { 14 [MT8192_POWER_DOMAIN_AUDIO] = { 15 .name = "audio", 16 .sta_mask = BIT(21), 17 .ctl_offs = 0x0354, 18 .sram_pdn_bits = GENMASK(8, 8), 19 .sram_pdn_ack_bits = GENMASK(12, 12), 20 .bp_infracfg = { 21 BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_2_AUDIO, 22 MT8192_TOP_AXI_PROT_EN_2_SET, 23 MT8192_TOP_AXI_PROT_EN_2_CLR, 24 MT8192_TOP_AXI_PROT_EN_2_STA1), 25 }, 26 }, 27 [MT8192_POWER_DOMAIN_CONN] = { 28 .name = "conn", 29 .sta_mask = PWR_STATUS_CONN, 30 .ctl_offs = 0x0304, 31 .sram_pdn_bits = 0, 32 .sram_pdn_ack_bits = 0, 33 .bp_infracfg = { 34 BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_CONN, 35 MT8192_TOP_AXI_PROT_EN_SET, 36 MT8192_TOP_AXI_PROT_EN_CLR, 37 MT8192_TOP_AXI_PROT_EN_STA1), 38 BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_CONN_2ND, 39 MT8192_TOP_AXI_PROT_EN_SET, 40 MT8192_TOP_AXI_PROT_EN_CLR, 41 MT8192_TOP_AXI_PROT_EN_STA1), 42 BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_1_CONN, 43 MT8192_TOP_AXI_PROT_EN_1_SET, 44 MT8192_TOP_AXI_PROT_EN_1_CLR, 45 MT8192_TOP_AXI_PROT_EN_1_STA1), 46 }, 47 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 48 }, 49 [MT8192_POWER_DOMAIN_MFG0] = { 50 .name = "mfg0", 51 .sta_mask = BIT(2), 52 .ctl_offs = 0x0308, 53 .sram_pdn_bits = GENMASK(8, 8), 54 .sram_pdn_ack_bits = GENMASK(12, 12), 55 }, 56 [MT8192_POWER_DOMAIN_MFG1] = { 57 .name = "mfg1", 58 .sta_mask = BIT(3), 59 .ctl_offs = 0x030c, 60 .sram_pdn_bits = GENMASK(8, 8), 61 .sram_pdn_ack_bits = GENMASK(12, 12), 62 .bp_infracfg = { 63 BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_1_MFG1, 64 MT8192_TOP_AXI_PROT_EN_1_SET, 65 MT8192_TOP_AXI_PROT_EN_1_CLR, 66 MT8192_TOP_AXI_PROT_EN_1_STA1), 67 BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_2_MFG1, 68 MT8192_TOP_AXI_PROT_EN_2_SET, 69 MT8192_TOP_AXI_PROT_EN_2_CLR, 70 MT8192_TOP_AXI_PROT_EN_2_STA1), 71 BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MFG1, 72 MT8192_TOP_AXI_PROT_EN_SET, 73 MT8192_TOP_AXI_PROT_EN_CLR, 74 MT8192_TOP_AXI_PROT_EN_STA1), 75 BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_2_MFG1_2ND, 76 MT8192_TOP_AXI_PROT_EN_2_SET, 77 MT8192_TOP_AXI_PROT_EN_2_CLR, 78 MT8192_TOP_AXI_PROT_EN_2_STA1), 79 }, 80 }, 81 [MT8192_POWER_DOMAIN_MFG2] = { 82 .name = "mfg2", 83 .sta_mask = BIT(4), 84 .ctl_offs = 0x0310, 85 .sram_pdn_bits = GENMASK(8, 8), 86 .sram_pdn_ack_bits = GENMASK(12, 12), 87 }, 88 [MT8192_POWER_DOMAIN_MFG3] = { 89 .name = "mfg3", 90 .sta_mask = BIT(5), 91 .ctl_offs = 0x0314, 92 .sram_pdn_bits = GENMASK(8, 8), 93 .sram_pdn_ack_bits = GENMASK(12, 12), 94 }, 95 [MT8192_POWER_DOMAIN_MFG4] = { 96 .name = "mfg4", 97 .sta_mask = BIT(6), 98 .ctl_offs = 0x0318, 99 .sram_pdn_bits = GENMASK(8, 8), 100 .sram_pdn_ack_bits = GENMASK(12, 12), 101 }, 102 [MT8192_POWER_DOMAIN_MFG5] = { 103 .name = "mfg5", 104 .sta_mask = BIT(7), 105 .ctl_offs = 0x031c, 106 .sram_pdn_bits = GENMASK(8, 8), 107 .sram_pdn_ack_bits = GENMASK(12, 12), 108 }, 109 [MT8192_POWER_DOMAIN_MFG6] = { 110 .name = "mfg6", 111 .sta_mask = BIT(8), 112 .ctl_offs = 0x0320, 113 .sram_pdn_bits = GENMASK(8, 8), 114 .sram_pdn_ack_bits = GENMASK(12, 12), 115 }, 116 [MT8192_POWER_DOMAIN_DISP] = { 117 .name = "disp", 118 .sta_mask = BIT(20), 119 .ctl_offs = 0x0350, 120 .sram_pdn_bits = GENMASK(8, 8), 121 .sram_pdn_ack_bits = GENMASK(12, 12), 122 .bp_infracfg = { 123 BUS_PROT_WR_IGN(MT8192_TOP_AXI_PROT_EN_MM_DISP, 124 MT8192_TOP_AXI_PROT_EN_MM_SET, 125 MT8192_TOP_AXI_PROT_EN_MM_CLR, 126 MT8192_TOP_AXI_PROT_EN_MM_STA1), 127 BUS_PROT_WR_IGN(MT8192_TOP_AXI_PROT_EN_MM_2_DISP, 128 MT8192_TOP_AXI_PROT_EN_MM_2_SET, 129 MT8192_TOP_AXI_PROT_EN_MM_2_CLR, 130 MT8192_TOP_AXI_PROT_EN_MM_2_STA1), 131 BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_DISP, 132 MT8192_TOP_AXI_PROT_EN_SET, 133 MT8192_TOP_AXI_PROT_EN_CLR, 134 MT8192_TOP_AXI_PROT_EN_STA1), 135 BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_DISP_2ND, 136 MT8192_TOP_AXI_PROT_EN_MM_SET, 137 MT8192_TOP_AXI_PROT_EN_MM_CLR, 138 MT8192_TOP_AXI_PROT_EN_MM_STA1), 139 BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_2_DISP_2ND, 140 MT8192_TOP_AXI_PROT_EN_MM_2_SET, 141 MT8192_TOP_AXI_PROT_EN_MM_2_CLR, 142 MT8192_TOP_AXI_PROT_EN_MM_2_STA1), 143 }, 144 }, 145 [MT8192_POWER_DOMAIN_IPE] = { 146 .name = "ipe", 147 .sta_mask = BIT(14), 148 .ctl_offs = 0x0338, 149 .sram_pdn_bits = GENMASK(8, 8), 150 .sram_pdn_ack_bits = GENMASK(12, 12), 151 .bp_infracfg = { 152 BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_IPE, 153 MT8192_TOP_AXI_PROT_EN_MM_SET, 154 MT8192_TOP_AXI_PROT_EN_MM_CLR, 155 MT8192_TOP_AXI_PROT_EN_MM_STA1), 156 BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_IPE_2ND, 157 MT8192_TOP_AXI_PROT_EN_MM_SET, 158 MT8192_TOP_AXI_PROT_EN_MM_CLR, 159 MT8192_TOP_AXI_PROT_EN_MM_STA1), 160 }, 161 }, 162 [MT8192_POWER_DOMAIN_ISP] = { 163 .name = "isp", 164 .sta_mask = BIT(12), 165 .ctl_offs = 0x0330, 166 .sram_pdn_bits = GENMASK(8, 8), 167 .sram_pdn_ack_bits = GENMASK(12, 12), 168 .bp_infracfg = { 169 BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_2_ISP, 170 MT8192_TOP_AXI_PROT_EN_MM_2_SET, 171 MT8192_TOP_AXI_PROT_EN_MM_2_CLR, 172 MT8192_TOP_AXI_PROT_EN_MM_2_STA1), 173 BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_2_ISP_2ND, 174 MT8192_TOP_AXI_PROT_EN_MM_2_SET, 175 MT8192_TOP_AXI_PROT_EN_MM_2_CLR, 176 MT8192_TOP_AXI_PROT_EN_MM_2_STA1), 177 }, 178 }, 179 [MT8192_POWER_DOMAIN_ISP2] = { 180 .name = "isp2", 181 .sta_mask = BIT(13), 182 .ctl_offs = 0x0334, 183 .sram_pdn_bits = GENMASK(8, 8), 184 .sram_pdn_ack_bits = GENMASK(12, 12), 185 .bp_infracfg = { 186 BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_ISP2, 187 MT8192_TOP_AXI_PROT_EN_MM_SET, 188 MT8192_TOP_AXI_PROT_EN_MM_CLR, 189 MT8192_TOP_AXI_PROT_EN_MM_STA1), 190 BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_ISP2_2ND, 191 MT8192_TOP_AXI_PROT_EN_MM_SET, 192 MT8192_TOP_AXI_PROT_EN_MM_CLR, 193 MT8192_TOP_AXI_PROT_EN_MM_STA1), 194 }, 195 }, 196 [MT8192_POWER_DOMAIN_MDP] = { 197 .name = "mdp", 198 .sta_mask = BIT(19), 199 .ctl_offs = 0x034c, 200 .sram_pdn_bits = GENMASK(8, 8), 201 .sram_pdn_ack_bits = GENMASK(12, 12), 202 .bp_infracfg = { 203 BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_2_MDP, 204 MT8192_TOP_AXI_PROT_EN_MM_2_SET, 205 MT8192_TOP_AXI_PROT_EN_MM_2_CLR, 206 MT8192_TOP_AXI_PROT_EN_MM_2_STA1), 207 BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_2_MDP_2ND, 208 MT8192_TOP_AXI_PROT_EN_MM_2_SET, 209 MT8192_TOP_AXI_PROT_EN_MM_2_CLR, 210 MT8192_TOP_AXI_PROT_EN_MM_2_STA1), 211 }, 212 }, 213 [MT8192_POWER_DOMAIN_VENC] = { 214 .name = "venc", 215 .sta_mask = BIT(17), 216 .ctl_offs = 0x0344, 217 .sram_pdn_bits = GENMASK(8, 8), 218 .sram_pdn_ack_bits = GENMASK(12, 12), 219 .bp_infracfg = { 220 BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_VENC, 221 MT8192_TOP_AXI_PROT_EN_MM_SET, 222 MT8192_TOP_AXI_PROT_EN_MM_CLR, 223 MT8192_TOP_AXI_PROT_EN_MM_STA1), 224 BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_VENC_2ND, 225 MT8192_TOP_AXI_PROT_EN_MM_SET, 226 MT8192_TOP_AXI_PROT_EN_MM_CLR, 227 MT8192_TOP_AXI_PROT_EN_MM_STA1), 228 }, 229 }, 230 [MT8192_POWER_DOMAIN_VDEC] = { 231 .name = "vdec", 232 .sta_mask = BIT(15), 233 .ctl_offs = 0x033c, 234 .sram_pdn_bits = GENMASK(8, 8), 235 .sram_pdn_ack_bits = GENMASK(12, 12), 236 .bp_infracfg = { 237 BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_VDEC, 238 MT8192_TOP_AXI_PROT_EN_MM_SET, 239 MT8192_TOP_AXI_PROT_EN_MM_CLR, 240 MT8192_TOP_AXI_PROT_EN_MM_STA1), 241 BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_VDEC_2ND, 242 MT8192_TOP_AXI_PROT_EN_MM_SET, 243 MT8192_TOP_AXI_PROT_EN_MM_CLR, 244 MT8192_TOP_AXI_PROT_EN_MM_STA1), 245 }, 246 }, 247 [MT8192_POWER_DOMAIN_VDEC2] = { 248 .name = "vdec2", 249 .sta_mask = BIT(16), 250 .ctl_offs = 0x0340, 251 .sram_pdn_bits = GENMASK(8, 8), 252 .sram_pdn_ack_bits = GENMASK(12, 12), 253 }, 254 [MT8192_POWER_DOMAIN_CAM] = { 255 .name = "cam", 256 .sta_mask = BIT(23), 257 .ctl_offs = 0x035c, 258 .sram_pdn_bits = GENMASK(8, 8), 259 .sram_pdn_ack_bits = GENMASK(12, 12), 260 .bp_infracfg = { 261 BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_2_CAM, 262 MT8192_TOP_AXI_PROT_EN_2_SET, 263 MT8192_TOP_AXI_PROT_EN_2_CLR, 264 MT8192_TOP_AXI_PROT_EN_2_STA1), 265 BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_CAM, 266 MT8192_TOP_AXI_PROT_EN_MM_SET, 267 MT8192_TOP_AXI_PROT_EN_MM_CLR, 268 MT8192_TOP_AXI_PROT_EN_MM_STA1), 269 BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_1_CAM, 270 MT8192_TOP_AXI_PROT_EN_1_SET, 271 MT8192_TOP_AXI_PROT_EN_1_CLR, 272 MT8192_TOP_AXI_PROT_EN_1_STA1), 273 BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_CAM_2ND, 274 MT8192_TOP_AXI_PROT_EN_MM_SET, 275 MT8192_TOP_AXI_PROT_EN_MM_CLR, 276 MT8192_TOP_AXI_PROT_EN_MM_STA1), 277 BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_VDNR_CAM, 278 MT8192_TOP_AXI_PROT_EN_VDNR_SET, 279 MT8192_TOP_AXI_PROT_EN_VDNR_CLR, 280 MT8192_TOP_AXI_PROT_EN_VDNR_STA1), 281 }, 282 }, 283 [MT8192_POWER_DOMAIN_CAM_RAWA] = { 284 .name = "cam_rawa", 285 .sta_mask = BIT(24), 286 .ctl_offs = 0x0360, 287 .sram_pdn_bits = GENMASK(8, 8), 288 .sram_pdn_ack_bits = GENMASK(12, 12), 289 }, 290 [MT8192_POWER_DOMAIN_CAM_RAWB] = { 291 .name = "cam_rawb", 292 .sta_mask = BIT(25), 293 .ctl_offs = 0x0364, 294 .sram_pdn_bits = GENMASK(8, 8), 295 .sram_pdn_ack_bits = GENMASK(12, 12), 296 }, 297 [MT8192_POWER_DOMAIN_CAM_RAWC] = { 298 .name = "cam_rawc", 299 .sta_mask = BIT(26), 300 .ctl_offs = 0x0368, 301 .sram_pdn_bits = GENMASK(8, 8), 302 .sram_pdn_ack_bits = GENMASK(12, 12), 303 }, 304 }; 305 306 static const struct scpsys_soc_data mt8192_scpsys_data = { 307 .domains_data = scpsys_domain_data_mt8192, 308 .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8192), 309 .pwr_sta_offs = 0x016c, 310 .pwr_sta2nd_offs = 0x0170, 311 }; 312 313 #endif /* __SOC_MEDIATEK_MT8192_PM_DOMAINS_H */ 314