1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2017-2018, The Linux foundation. All rights reserved.
3
4 #include <linux/clk.h>
5 #include <linux/dmaengine.h>
6 #include <linux/dma-mapping.h>
7 #include <linux/dma/qcom-gpi-dma.h>
8 #include <linux/interrupt.h>
9 #include <linux/io.h>
10 #include <linux/log2.h>
11 #include <linux/module.h>
12 #include <linux/platform_device.h>
13 #include <linux/pm_opp.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/qcom-geni-se.h>
16 #include <linux/spi/spi.h>
17 #include <linux/spinlock.h>
18
19 /* SPI SE specific registers and respective register fields */
20 #define SE_SPI_CPHA 0x224
21 #define CPHA BIT(0)
22
23 #define SE_SPI_LOOPBACK 0x22c
24 #define LOOPBACK_ENABLE 0x1
25 #define NORMAL_MODE 0x0
26 #define LOOPBACK_MSK GENMASK(1, 0)
27
28 #define SE_SPI_CPOL 0x230
29 #define CPOL BIT(2)
30
31 #define SE_SPI_DEMUX_OUTPUT_INV 0x24c
32 #define CS_DEMUX_OUTPUT_INV_MSK GENMASK(3, 0)
33
34 #define SE_SPI_DEMUX_SEL 0x250
35 #define CS_DEMUX_OUTPUT_SEL GENMASK(3, 0)
36
37 #define SE_SPI_TRANS_CFG 0x25c
38 #define CS_TOGGLE BIT(0)
39
40 #define SE_SPI_WORD_LEN 0x268
41 #define WORD_LEN_MSK GENMASK(9, 0)
42 #define MIN_WORD_LEN 4
43
44 #define SE_SPI_TX_TRANS_LEN 0x26c
45 #define SE_SPI_RX_TRANS_LEN 0x270
46 #define TRANS_LEN_MSK GENMASK(23, 0)
47
48 #define SE_SPI_PRE_POST_CMD_DLY 0x274
49
50 #define SE_SPI_DELAY_COUNTERS 0x278
51 #define SPI_INTER_WORDS_DELAY_MSK GENMASK(9, 0)
52 #define SPI_CS_CLK_DELAY_MSK GENMASK(19, 10)
53 #define SPI_CS_CLK_DELAY_SHFT 10
54
55 /* M_CMD OP codes for SPI */
56 #define SPI_TX_ONLY 1
57 #define SPI_RX_ONLY 2
58 #define SPI_TX_RX 7
59 #define SPI_CS_ASSERT 8
60 #define SPI_CS_DEASSERT 9
61 #define SPI_SCK_ONLY 10
62 /* M_CMD params for SPI */
63 #define SPI_PRE_CMD_DELAY BIT(0)
64 #define TIMESTAMP_BEFORE BIT(1)
65 #define FRAGMENTATION BIT(2)
66 #define TIMESTAMP_AFTER BIT(3)
67 #define POST_CMD_DELAY BIT(4)
68
69 #define GSI_LOOPBACK_EN BIT(0)
70 #define GSI_CS_TOGGLE BIT(3)
71 #define GSI_CPHA BIT(4)
72 #define GSI_CPOL BIT(5)
73
74 #define MAX_TX_SG 3
75 #define NUM_SPI_XFER 8
76 #define SPI_XFER_TIMEOUT_MS 250
77
78 struct spi_geni_master {
79 struct geni_se se;
80 struct device *dev;
81 u32 tx_fifo_depth;
82 u32 fifo_width_bits;
83 u32 tx_wm;
84 u32 last_mode;
85 unsigned long cur_speed_hz;
86 unsigned long cur_sclk_hz;
87 unsigned int cur_bits_per_word;
88 unsigned int tx_rem_bytes;
89 unsigned int rx_rem_bytes;
90 const struct spi_transfer *cur_xfer;
91 struct completion cs_done;
92 struct completion cancel_done;
93 struct completion abort_done;
94 unsigned int oversampling;
95 spinlock_t lock;
96 int irq;
97 bool cs_flag;
98 bool abort_failed;
99 struct dma_chan *tx;
100 struct dma_chan *rx;
101 int cur_xfer_mode;
102 };
103
get_spi_clk_cfg(unsigned int speed_hz,struct spi_geni_master * mas,unsigned int * clk_idx,unsigned int * clk_div)104 static int get_spi_clk_cfg(unsigned int speed_hz,
105 struct spi_geni_master *mas,
106 unsigned int *clk_idx,
107 unsigned int *clk_div)
108 {
109 unsigned long sclk_freq;
110 unsigned int actual_hz;
111 int ret;
112
113 ret = geni_se_clk_freq_match(&mas->se,
114 speed_hz * mas->oversampling,
115 clk_idx, &sclk_freq, false);
116 if (ret) {
117 dev_err(mas->dev, "Failed(%d) to find src clk for %dHz\n",
118 ret, speed_hz);
119 return ret;
120 }
121
122 *clk_div = DIV_ROUND_UP(sclk_freq, mas->oversampling * speed_hz);
123 actual_hz = sclk_freq / (mas->oversampling * *clk_div);
124
125 dev_dbg(mas->dev, "req %u=>%u sclk %lu, idx %d, div %d\n", speed_hz,
126 actual_hz, sclk_freq, *clk_idx, *clk_div);
127 ret = dev_pm_opp_set_rate(mas->dev, sclk_freq);
128 if (ret)
129 dev_err(mas->dev, "dev_pm_opp_set_rate failed %d\n", ret);
130 else
131 mas->cur_sclk_hz = sclk_freq;
132
133 return ret;
134 }
135
handle_fifo_timeout(struct spi_master * spi,struct spi_message * msg)136 static void handle_fifo_timeout(struct spi_master *spi,
137 struct spi_message *msg)
138 {
139 struct spi_geni_master *mas = spi_master_get_devdata(spi);
140 unsigned long time_left;
141 struct geni_se *se = &mas->se;
142
143 spin_lock_irq(&mas->lock);
144 reinit_completion(&mas->cancel_done);
145 writel(0, se->base + SE_GENI_TX_WATERMARK_REG);
146 mas->cur_xfer = NULL;
147 geni_se_cancel_m_cmd(se);
148 spin_unlock_irq(&mas->lock);
149
150 time_left = wait_for_completion_timeout(&mas->cancel_done, HZ);
151 if (time_left)
152 return;
153
154 spin_lock_irq(&mas->lock);
155 reinit_completion(&mas->abort_done);
156 geni_se_abort_m_cmd(se);
157 spin_unlock_irq(&mas->lock);
158
159 time_left = wait_for_completion_timeout(&mas->abort_done, HZ);
160 if (!time_left) {
161 dev_err(mas->dev, "Failed to cancel/abort m_cmd\n");
162
163 /*
164 * No need for a lock since SPI core has a lock and we never
165 * access this from an interrupt.
166 */
167 mas->abort_failed = true;
168 }
169 }
170
spi_geni_is_abort_still_pending(struct spi_geni_master * mas)171 static bool spi_geni_is_abort_still_pending(struct spi_geni_master *mas)
172 {
173 struct geni_se *se = &mas->se;
174 u32 m_irq, m_irq_en;
175
176 if (!mas->abort_failed)
177 return false;
178
179 /*
180 * The only known case where a transfer times out and then a cancel
181 * times out then an abort times out is if something is blocking our
182 * interrupt handler from running. Avoid starting any new transfers
183 * until that sorts itself out.
184 */
185 spin_lock_irq(&mas->lock);
186 m_irq = readl(se->base + SE_GENI_M_IRQ_STATUS);
187 m_irq_en = readl(se->base + SE_GENI_M_IRQ_EN);
188 spin_unlock_irq(&mas->lock);
189
190 if (m_irq & m_irq_en) {
191 dev_err(mas->dev, "Interrupts pending after abort: %#010x\n",
192 m_irq & m_irq_en);
193 return true;
194 }
195
196 /*
197 * If we're here the problem resolved itself so no need to check more
198 * on future transfers.
199 */
200 mas->abort_failed = false;
201
202 return false;
203 }
204
spi_geni_set_cs(struct spi_device * slv,bool set_flag)205 static void spi_geni_set_cs(struct spi_device *slv, bool set_flag)
206 {
207 struct spi_geni_master *mas = spi_master_get_devdata(slv->master);
208 struct spi_master *spi = dev_get_drvdata(mas->dev);
209 struct geni_se *se = &mas->se;
210 unsigned long time_left;
211
212 if (!(slv->mode & SPI_CS_HIGH))
213 set_flag = !set_flag;
214
215 if (set_flag == mas->cs_flag)
216 return;
217
218 pm_runtime_get_sync(mas->dev);
219
220 if (spi_geni_is_abort_still_pending(mas)) {
221 dev_err(mas->dev, "Can't set chip select\n");
222 goto exit;
223 }
224
225 spin_lock_irq(&mas->lock);
226 if (mas->cur_xfer) {
227 dev_err(mas->dev, "Can't set CS when prev xfer running\n");
228 spin_unlock_irq(&mas->lock);
229 goto exit;
230 }
231
232 mas->cs_flag = set_flag;
233 reinit_completion(&mas->cs_done);
234 if (set_flag)
235 geni_se_setup_m_cmd(se, SPI_CS_ASSERT, 0);
236 else
237 geni_se_setup_m_cmd(se, SPI_CS_DEASSERT, 0);
238 spin_unlock_irq(&mas->lock);
239
240 time_left = wait_for_completion_timeout(&mas->cs_done, HZ);
241 if (!time_left) {
242 dev_warn(mas->dev, "Timeout setting chip select\n");
243 handle_fifo_timeout(spi, NULL);
244 }
245
246 exit:
247 pm_runtime_put(mas->dev);
248 }
249
spi_setup_word_len(struct spi_geni_master * mas,u16 mode,unsigned int bits_per_word)250 static void spi_setup_word_len(struct spi_geni_master *mas, u16 mode,
251 unsigned int bits_per_word)
252 {
253 unsigned int pack_words;
254 bool msb_first = (mode & SPI_LSB_FIRST) ? false : true;
255 struct geni_se *se = &mas->se;
256 u32 word_len;
257
258 /*
259 * If bits_per_word isn't a byte aligned value, set the packing to be
260 * 1 SPI word per FIFO word.
261 */
262 if (!(mas->fifo_width_bits % bits_per_word))
263 pack_words = mas->fifo_width_bits / bits_per_word;
264 else
265 pack_words = 1;
266 geni_se_config_packing(&mas->se, bits_per_word, pack_words, msb_first,
267 true, true);
268 word_len = (bits_per_word - MIN_WORD_LEN) & WORD_LEN_MSK;
269 writel(word_len, se->base + SE_SPI_WORD_LEN);
270 }
271
geni_spi_set_clock_and_bw(struct spi_geni_master * mas,unsigned long clk_hz)272 static int geni_spi_set_clock_and_bw(struct spi_geni_master *mas,
273 unsigned long clk_hz)
274 {
275 u32 clk_sel, m_clk_cfg, idx, div;
276 struct geni_se *se = &mas->se;
277 int ret;
278
279 if (clk_hz == mas->cur_speed_hz)
280 return 0;
281
282 ret = get_spi_clk_cfg(clk_hz, mas, &idx, &div);
283 if (ret) {
284 dev_err(mas->dev, "Err setting clk to %lu: %d\n", clk_hz, ret);
285 return ret;
286 }
287
288 /*
289 * SPI core clock gets configured with the requested frequency
290 * or the frequency closer to the requested frequency.
291 * For that reason requested frequency is stored in the
292 * cur_speed_hz and referred in the consecutive transfer instead
293 * of calling clk_get_rate() API.
294 */
295 mas->cur_speed_hz = clk_hz;
296
297 clk_sel = idx & CLK_SEL_MSK;
298 m_clk_cfg = (div << CLK_DIV_SHFT) | SER_CLK_EN;
299 writel(clk_sel, se->base + SE_GENI_CLK_SEL);
300 writel(m_clk_cfg, se->base + GENI_SER_M_CLK_CFG);
301
302 /* Set BW quota for CPU as driver supports FIFO mode only. */
303 se->icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(mas->cur_speed_hz);
304 ret = geni_icc_set_bw(se);
305 if (ret)
306 return ret;
307
308 return 0;
309 }
310
setup_fifo_params(struct spi_device * spi_slv,struct spi_master * spi)311 static int setup_fifo_params(struct spi_device *spi_slv,
312 struct spi_master *spi)
313 {
314 struct spi_geni_master *mas = spi_master_get_devdata(spi);
315 struct geni_se *se = &mas->se;
316 u32 loopback_cfg = 0, cpol = 0, cpha = 0, demux_output_inv = 0;
317 u32 demux_sel;
318
319 if (mas->last_mode != spi_slv->mode) {
320 if (spi_slv->mode & SPI_LOOP)
321 loopback_cfg = LOOPBACK_ENABLE;
322
323 if (spi_slv->mode & SPI_CPOL)
324 cpol = CPOL;
325
326 if (spi_slv->mode & SPI_CPHA)
327 cpha = CPHA;
328
329 if (spi_slv->mode & SPI_CS_HIGH)
330 demux_output_inv = BIT(spi_slv->chip_select);
331
332 demux_sel = spi_slv->chip_select;
333 mas->cur_bits_per_word = spi_slv->bits_per_word;
334
335 spi_setup_word_len(mas, spi_slv->mode, spi_slv->bits_per_word);
336 writel(loopback_cfg, se->base + SE_SPI_LOOPBACK);
337 writel(demux_sel, se->base + SE_SPI_DEMUX_SEL);
338 writel(cpha, se->base + SE_SPI_CPHA);
339 writel(cpol, se->base + SE_SPI_CPOL);
340 writel(demux_output_inv, se->base + SE_SPI_DEMUX_OUTPUT_INV);
341
342 mas->last_mode = spi_slv->mode;
343 }
344
345 return geni_spi_set_clock_and_bw(mas, spi_slv->max_speed_hz);
346 }
347
348 static void
spi_gsi_callback_result(void * cb,const struct dmaengine_result * result)349 spi_gsi_callback_result(void *cb, const struct dmaengine_result *result)
350 {
351 struct spi_master *spi = cb;
352
353 if (result->result != DMA_TRANS_NOERROR) {
354 dev_err(&spi->dev, "DMA txn failed: %d\n", result->result);
355 return;
356 }
357
358 if (!result->residue) {
359 dev_dbg(&spi->dev, "DMA txn completed\n");
360 spi_finalize_current_transfer(spi);
361 } else {
362 dev_err(&spi->dev, "DMA xfer has pending: %d\n", result->residue);
363 }
364 }
365
setup_gsi_xfer(struct spi_transfer * xfer,struct spi_geni_master * mas,struct spi_device * spi_slv,struct spi_master * spi)366 static int setup_gsi_xfer(struct spi_transfer *xfer, struct spi_geni_master *mas,
367 struct spi_device *spi_slv, struct spi_master *spi)
368 {
369 unsigned long flags = DMA_PREP_INTERRUPT | DMA_CTRL_ACK;
370 struct dma_slave_config config = {};
371 struct gpi_spi_config peripheral = {};
372 struct dma_async_tx_descriptor *tx_desc, *rx_desc;
373 int ret;
374
375 config.peripheral_config = &peripheral;
376 config.peripheral_size = sizeof(peripheral);
377 peripheral.set_config = true;
378
379 if (xfer->bits_per_word != mas->cur_bits_per_word ||
380 xfer->speed_hz != mas->cur_speed_hz) {
381 mas->cur_bits_per_word = xfer->bits_per_word;
382 mas->cur_speed_hz = xfer->speed_hz;
383 }
384
385 if (xfer->tx_buf && xfer->rx_buf) {
386 peripheral.cmd = SPI_DUPLEX;
387 } else if (xfer->tx_buf) {
388 peripheral.cmd = SPI_TX;
389 peripheral.rx_len = 0;
390 } else if (xfer->rx_buf) {
391 peripheral.cmd = SPI_RX;
392 if (!(mas->cur_bits_per_word % MIN_WORD_LEN)) {
393 peripheral.rx_len = ((xfer->len << 3) / mas->cur_bits_per_word);
394 } else {
395 int bytes_per_word = (mas->cur_bits_per_word / BITS_PER_BYTE) + 1;
396
397 peripheral.rx_len = (xfer->len / bytes_per_word);
398 }
399 }
400
401 peripheral.loopback_en = !!(spi_slv->mode & SPI_LOOP);
402 peripheral.clock_pol_high = !!(spi_slv->mode & SPI_CPOL);
403 peripheral.data_pol_high = !!(spi_slv->mode & SPI_CPHA);
404 peripheral.cs = spi_slv->chip_select;
405 peripheral.pack_en = true;
406 peripheral.word_len = xfer->bits_per_word - MIN_WORD_LEN;
407
408 ret = get_spi_clk_cfg(mas->cur_speed_hz, mas,
409 &peripheral.clk_src, &peripheral.clk_div);
410 if (ret) {
411 dev_err(mas->dev, "Err in get_spi_clk_cfg() :%d\n", ret);
412 return ret;
413 }
414
415 if (!xfer->cs_change) {
416 if (!list_is_last(&xfer->transfer_list, &spi->cur_msg->transfers))
417 peripheral.fragmentation = FRAGMENTATION;
418 }
419
420 if (peripheral.cmd & SPI_RX) {
421 dmaengine_slave_config(mas->rx, &config);
422 rx_desc = dmaengine_prep_slave_sg(mas->rx, xfer->rx_sg.sgl, xfer->rx_sg.nents,
423 DMA_DEV_TO_MEM, flags);
424 if (!rx_desc) {
425 dev_err(mas->dev, "Err setting up rx desc\n");
426 return -EIO;
427 }
428 }
429
430 /*
431 * Prepare the TX always, even for RX or tx_buf being null, we would
432 * need TX to be prepared per GSI spec
433 */
434 dmaengine_slave_config(mas->tx, &config);
435 tx_desc = dmaengine_prep_slave_sg(mas->tx, xfer->tx_sg.sgl, xfer->tx_sg.nents,
436 DMA_MEM_TO_DEV, flags);
437 if (!tx_desc) {
438 dev_err(mas->dev, "Err setting up tx desc\n");
439 return -EIO;
440 }
441
442 tx_desc->callback_result = spi_gsi_callback_result;
443 tx_desc->callback_param = spi;
444
445 if (peripheral.cmd & SPI_RX)
446 dmaengine_submit(rx_desc);
447 dmaengine_submit(tx_desc);
448
449 if (peripheral.cmd & SPI_RX)
450 dma_async_issue_pending(mas->rx);
451
452 dma_async_issue_pending(mas->tx);
453 return 1;
454 }
455
geni_can_dma(struct spi_controller * ctlr,struct spi_device * slv,struct spi_transfer * xfer)456 static bool geni_can_dma(struct spi_controller *ctlr,
457 struct spi_device *slv, struct spi_transfer *xfer)
458 {
459 struct spi_geni_master *mas = spi_master_get_devdata(slv->master);
460
461 /* check if dma is supported */
462 return mas->cur_xfer_mode != GENI_SE_FIFO;
463 }
464
spi_geni_prepare_message(struct spi_master * spi,struct spi_message * spi_msg)465 static int spi_geni_prepare_message(struct spi_master *spi,
466 struct spi_message *spi_msg)
467 {
468 struct spi_geni_master *mas = spi_master_get_devdata(spi);
469 int ret;
470
471 switch (mas->cur_xfer_mode) {
472 case GENI_SE_FIFO:
473 if (spi_geni_is_abort_still_pending(mas))
474 return -EBUSY;
475 ret = setup_fifo_params(spi_msg->spi, spi);
476 if (ret)
477 dev_err(mas->dev, "Couldn't select mode %d\n", ret);
478 return ret;
479
480 case GENI_GPI_DMA:
481 /* nothing to do for GPI DMA */
482 return 0;
483 }
484
485 dev_err(mas->dev, "Mode not supported %d", mas->cur_xfer_mode);
486 return -EINVAL;
487 }
488
spi_geni_grab_gpi_chan(struct spi_geni_master * mas)489 static int spi_geni_grab_gpi_chan(struct spi_geni_master *mas)
490 {
491 int ret;
492
493 mas->tx = dma_request_chan(mas->dev, "tx");
494 if (IS_ERR(mas->tx)) {
495 ret = dev_err_probe(mas->dev, PTR_ERR(mas->tx),
496 "Failed to get tx DMA ch\n");
497 goto err_tx;
498 }
499
500 mas->rx = dma_request_chan(mas->dev, "rx");
501 if (IS_ERR(mas->rx)) {
502 ret = dev_err_probe(mas->dev, PTR_ERR(mas->rx),
503 "Failed to get rx DMA ch\n");
504 goto err_rx;
505 }
506
507 return 0;
508
509 err_rx:
510 mas->rx = NULL;
511 dma_release_channel(mas->tx);
512 err_tx:
513 mas->tx = NULL;
514 return ret;
515 }
516
spi_geni_release_dma_chan(struct spi_geni_master * mas)517 static void spi_geni_release_dma_chan(struct spi_geni_master *mas)
518 {
519 if (mas->rx) {
520 dma_release_channel(mas->rx);
521 mas->rx = NULL;
522 }
523
524 if (mas->tx) {
525 dma_release_channel(mas->tx);
526 mas->tx = NULL;
527 }
528 }
529
spi_geni_init(struct spi_geni_master * mas)530 static int spi_geni_init(struct spi_geni_master *mas)
531 {
532 struct geni_se *se = &mas->se;
533 unsigned int proto, major, minor, ver;
534 u32 spi_tx_cfg, fifo_disable;
535 int ret = -ENXIO;
536
537 pm_runtime_get_sync(mas->dev);
538
539 proto = geni_se_read_proto(se);
540 if (proto != GENI_SE_SPI) {
541 dev_err(mas->dev, "Invalid proto %d\n", proto);
542 goto out_pm;
543 }
544 mas->tx_fifo_depth = geni_se_get_tx_fifo_depth(se);
545
546 /* Width of Tx and Rx FIFO is same */
547 mas->fifo_width_bits = geni_se_get_tx_fifo_width(se);
548
549 /*
550 * Hardware programming guide suggests to configure
551 * RX FIFO RFR level to fifo_depth-2.
552 */
553 geni_se_init(se, mas->tx_fifo_depth - 3, mas->tx_fifo_depth - 2);
554 /* Transmit an entire FIFO worth of data per IRQ */
555 mas->tx_wm = 1;
556 ver = geni_se_get_qup_hw_version(se);
557 major = GENI_SE_VERSION_MAJOR(ver);
558 minor = GENI_SE_VERSION_MINOR(ver);
559
560 if (major == 1 && minor == 0)
561 mas->oversampling = 2;
562 else
563 mas->oversampling = 1;
564
565 fifo_disable = readl(se->base + GENI_IF_DISABLE_RO) & FIFO_IF_DISABLE;
566 switch (fifo_disable) {
567 case 1:
568 ret = spi_geni_grab_gpi_chan(mas);
569 if (!ret) { /* success case */
570 mas->cur_xfer_mode = GENI_GPI_DMA;
571 geni_se_select_mode(se, GENI_GPI_DMA);
572 dev_dbg(mas->dev, "Using GPI DMA mode for SPI\n");
573 break;
574 }
575 /*
576 * in case of failure to get dma channel, we can still do the
577 * FIFO mode, so fallthrough
578 */
579 dev_warn(mas->dev, "FIFO mode disabled, but couldn't get DMA, fall back to FIFO mode\n");
580 fallthrough;
581
582 case 0:
583 mas->cur_xfer_mode = GENI_SE_FIFO;
584 geni_se_select_mode(se, GENI_SE_FIFO);
585 ret = 0;
586 break;
587 }
588
589 /* We always control CS manually */
590 spi_tx_cfg = readl(se->base + SE_SPI_TRANS_CFG);
591 spi_tx_cfg &= ~CS_TOGGLE;
592 writel(spi_tx_cfg, se->base + SE_SPI_TRANS_CFG);
593
594 out_pm:
595 pm_runtime_put(mas->dev);
596 return ret;
597 }
598
geni_byte_per_fifo_word(struct spi_geni_master * mas)599 static unsigned int geni_byte_per_fifo_word(struct spi_geni_master *mas)
600 {
601 /*
602 * Calculate how many bytes we'll put in each FIFO word. If the
603 * transfer words don't pack cleanly into a FIFO word we'll just put
604 * one transfer word in each FIFO word. If they do pack we'll pack 'em.
605 */
606 if (mas->fifo_width_bits % mas->cur_bits_per_word)
607 return roundup_pow_of_two(DIV_ROUND_UP(mas->cur_bits_per_word,
608 BITS_PER_BYTE));
609
610 return mas->fifo_width_bits / BITS_PER_BYTE;
611 }
612
geni_spi_handle_tx(struct spi_geni_master * mas)613 static bool geni_spi_handle_tx(struct spi_geni_master *mas)
614 {
615 struct geni_se *se = &mas->se;
616 unsigned int max_bytes;
617 const u8 *tx_buf;
618 unsigned int bytes_per_fifo_word = geni_byte_per_fifo_word(mas);
619 unsigned int i = 0;
620
621 /* Stop the watermark IRQ if nothing to send */
622 if (!mas->cur_xfer) {
623 writel(0, se->base + SE_GENI_TX_WATERMARK_REG);
624 return false;
625 }
626
627 max_bytes = (mas->tx_fifo_depth - mas->tx_wm) * bytes_per_fifo_word;
628 if (mas->tx_rem_bytes < max_bytes)
629 max_bytes = mas->tx_rem_bytes;
630
631 tx_buf = mas->cur_xfer->tx_buf + mas->cur_xfer->len - mas->tx_rem_bytes;
632 while (i < max_bytes) {
633 unsigned int j;
634 unsigned int bytes_to_write;
635 u32 fifo_word = 0;
636 u8 *fifo_byte = (u8 *)&fifo_word;
637
638 bytes_to_write = min(bytes_per_fifo_word, max_bytes - i);
639 for (j = 0; j < bytes_to_write; j++)
640 fifo_byte[j] = tx_buf[i++];
641 iowrite32_rep(se->base + SE_GENI_TX_FIFOn, &fifo_word, 1);
642 }
643 mas->tx_rem_bytes -= max_bytes;
644 if (!mas->tx_rem_bytes) {
645 writel(0, se->base + SE_GENI_TX_WATERMARK_REG);
646 return false;
647 }
648 return true;
649 }
650
geni_spi_handle_rx(struct spi_geni_master * mas)651 static void geni_spi_handle_rx(struct spi_geni_master *mas)
652 {
653 struct geni_se *se = &mas->se;
654 u32 rx_fifo_status;
655 unsigned int rx_bytes;
656 unsigned int rx_last_byte_valid;
657 u8 *rx_buf;
658 unsigned int bytes_per_fifo_word = geni_byte_per_fifo_word(mas);
659 unsigned int i = 0;
660
661 rx_fifo_status = readl(se->base + SE_GENI_RX_FIFO_STATUS);
662 rx_bytes = (rx_fifo_status & RX_FIFO_WC_MSK) * bytes_per_fifo_word;
663 if (rx_fifo_status & RX_LAST) {
664 rx_last_byte_valid = rx_fifo_status & RX_LAST_BYTE_VALID_MSK;
665 rx_last_byte_valid >>= RX_LAST_BYTE_VALID_SHFT;
666 if (rx_last_byte_valid && rx_last_byte_valid < 4)
667 rx_bytes -= bytes_per_fifo_word - rx_last_byte_valid;
668 }
669
670 /* Clear out the FIFO and bail if nowhere to put it */
671 if (!mas->cur_xfer) {
672 for (i = 0; i < DIV_ROUND_UP(rx_bytes, bytes_per_fifo_word); i++)
673 readl(se->base + SE_GENI_RX_FIFOn);
674 return;
675 }
676
677 if (mas->rx_rem_bytes < rx_bytes)
678 rx_bytes = mas->rx_rem_bytes;
679
680 rx_buf = mas->cur_xfer->rx_buf + mas->cur_xfer->len - mas->rx_rem_bytes;
681 while (i < rx_bytes) {
682 u32 fifo_word = 0;
683 u8 *fifo_byte = (u8 *)&fifo_word;
684 unsigned int bytes_to_read;
685 unsigned int j;
686
687 bytes_to_read = min(bytes_per_fifo_word, rx_bytes - i);
688 ioread32_rep(se->base + SE_GENI_RX_FIFOn, &fifo_word, 1);
689 for (j = 0; j < bytes_to_read; j++)
690 rx_buf[i++] = fifo_byte[j];
691 }
692 mas->rx_rem_bytes -= rx_bytes;
693 }
694
setup_fifo_xfer(struct spi_transfer * xfer,struct spi_geni_master * mas,u16 mode,struct spi_master * spi)695 static void setup_fifo_xfer(struct spi_transfer *xfer,
696 struct spi_geni_master *mas,
697 u16 mode, struct spi_master *spi)
698 {
699 u32 m_cmd = 0;
700 u32 len;
701 struct geni_se *se = &mas->se;
702 int ret;
703
704 /*
705 * Ensure that our interrupt handler isn't still running from some
706 * prior command before we start messing with the hardware behind
707 * its back. We don't need to _keep_ the lock here since we're only
708 * worried about racing with out interrupt handler. The SPI core
709 * already handles making sure that we're not trying to do two
710 * transfers at once or setting a chip select and doing a transfer
711 * concurrently.
712 *
713 * NOTE: we actually _can't_ hold the lock here because possibly we
714 * might call clk_set_rate() which needs to be able to sleep.
715 */
716 spin_lock_irq(&mas->lock);
717 spin_unlock_irq(&mas->lock);
718
719 if (xfer->bits_per_word != mas->cur_bits_per_word) {
720 spi_setup_word_len(mas, mode, xfer->bits_per_word);
721 mas->cur_bits_per_word = xfer->bits_per_word;
722 }
723
724 /* Speed and bits per word can be overridden per transfer */
725 ret = geni_spi_set_clock_and_bw(mas, xfer->speed_hz);
726 if (ret)
727 return;
728
729 mas->tx_rem_bytes = 0;
730 mas->rx_rem_bytes = 0;
731
732 if (!(mas->cur_bits_per_word % MIN_WORD_LEN))
733 len = xfer->len * BITS_PER_BYTE / mas->cur_bits_per_word;
734 else
735 len = xfer->len / (mas->cur_bits_per_word / BITS_PER_BYTE + 1);
736 len &= TRANS_LEN_MSK;
737
738 mas->cur_xfer = xfer;
739 if (xfer->tx_buf) {
740 m_cmd |= SPI_TX_ONLY;
741 mas->tx_rem_bytes = xfer->len;
742 writel(len, se->base + SE_SPI_TX_TRANS_LEN);
743 }
744
745 if (xfer->rx_buf) {
746 m_cmd |= SPI_RX_ONLY;
747 writel(len, se->base + SE_SPI_RX_TRANS_LEN);
748 mas->rx_rem_bytes = xfer->len;
749 }
750
751 /*
752 * Lock around right before we start the transfer since our
753 * interrupt could come in at any time now.
754 */
755 spin_lock_irq(&mas->lock);
756 geni_se_setup_m_cmd(se, m_cmd, FRAGMENTATION);
757 if (m_cmd & SPI_TX_ONLY) {
758 if (geni_spi_handle_tx(mas))
759 writel(mas->tx_wm, se->base + SE_GENI_TX_WATERMARK_REG);
760 }
761 spin_unlock_irq(&mas->lock);
762 }
763
spi_geni_transfer_one(struct spi_master * spi,struct spi_device * slv,struct spi_transfer * xfer)764 static int spi_geni_transfer_one(struct spi_master *spi,
765 struct spi_device *slv,
766 struct spi_transfer *xfer)
767 {
768 struct spi_geni_master *mas = spi_master_get_devdata(spi);
769
770 if (spi_geni_is_abort_still_pending(mas))
771 return -EBUSY;
772
773 /* Terminate and return success for 0 byte length transfer */
774 if (!xfer->len)
775 return 0;
776
777 if (mas->cur_xfer_mode == GENI_SE_FIFO) {
778 setup_fifo_xfer(xfer, mas, slv->mode, spi);
779 return 1;
780 }
781 return setup_gsi_xfer(xfer, mas, slv, spi);
782 }
783
geni_spi_isr(int irq,void * data)784 static irqreturn_t geni_spi_isr(int irq, void *data)
785 {
786 struct spi_master *spi = data;
787 struct spi_geni_master *mas = spi_master_get_devdata(spi);
788 struct geni_se *se = &mas->se;
789 u32 m_irq;
790
791 m_irq = readl(se->base + SE_GENI_M_IRQ_STATUS);
792 if (!m_irq)
793 return IRQ_NONE;
794
795 if (m_irq & (M_CMD_OVERRUN_EN | M_ILLEGAL_CMD_EN | M_CMD_FAILURE_EN |
796 M_RX_FIFO_RD_ERR_EN | M_RX_FIFO_WR_ERR_EN |
797 M_TX_FIFO_RD_ERR_EN | M_TX_FIFO_WR_ERR_EN))
798 dev_warn(mas->dev, "Unexpected IRQ err status %#010x\n", m_irq);
799
800 spin_lock(&mas->lock);
801
802 if ((m_irq & M_RX_FIFO_WATERMARK_EN) || (m_irq & M_RX_FIFO_LAST_EN))
803 geni_spi_handle_rx(mas);
804
805 if (m_irq & M_TX_FIFO_WATERMARK_EN)
806 geni_spi_handle_tx(mas);
807
808 if (m_irq & M_CMD_DONE_EN) {
809 if (mas->cur_xfer) {
810 spi_finalize_current_transfer(spi);
811 mas->cur_xfer = NULL;
812 /*
813 * If this happens, then a CMD_DONE came before all the
814 * Tx buffer bytes were sent out. This is unusual, log
815 * this condition and disable the WM interrupt to
816 * prevent the system from stalling due an interrupt
817 * storm.
818 *
819 * If this happens when all Rx bytes haven't been
820 * received, log the condition. The only known time
821 * this can happen is if bits_per_word != 8 and some
822 * registers that expect xfer lengths in num spi_words
823 * weren't written correctly.
824 */
825 if (mas->tx_rem_bytes) {
826 writel(0, se->base + SE_GENI_TX_WATERMARK_REG);
827 dev_err(mas->dev, "Premature done. tx_rem = %d bpw%d\n",
828 mas->tx_rem_bytes, mas->cur_bits_per_word);
829 }
830 if (mas->rx_rem_bytes)
831 dev_err(mas->dev, "Premature done. rx_rem = %d bpw%d\n",
832 mas->rx_rem_bytes, mas->cur_bits_per_word);
833 } else {
834 complete(&mas->cs_done);
835 }
836 }
837
838 if (m_irq & M_CMD_CANCEL_EN)
839 complete(&mas->cancel_done);
840 if (m_irq & M_CMD_ABORT_EN)
841 complete(&mas->abort_done);
842
843 /*
844 * It's safe or a good idea to Ack all of our interrupts at the end
845 * of the function. Specifically:
846 * - M_CMD_DONE_EN / M_RX_FIFO_LAST_EN: Edge triggered interrupts and
847 * clearing Acks. Clearing at the end relies on nobody else having
848 * started a new transfer yet or else we could be clearing _their_
849 * done bit, but everyone grabs the spinlock before starting a new
850 * transfer.
851 * - M_RX_FIFO_WATERMARK_EN / M_TX_FIFO_WATERMARK_EN: These appear
852 * to be "latched level" interrupts so it's important to clear them
853 * _after_ you've handled the condition and always safe to do so
854 * since they'll re-assert if they're still happening.
855 */
856 writel(m_irq, se->base + SE_GENI_M_IRQ_CLEAR);
857
858 spin_unlock(&mas->lock);
859
860 return IRQ_HANDLED;
861 }
862
spi_geni_probe(struct platform_device * pdev)863 static int spi_geni_probe(struct platform_device *pdev)
864 {
865 int ret, irq;
866 struct spi_master *spi;
867 struct spi_geni_master *mas;
868 void __iomem *base;
869 struct clk *clk;
870 struct device *dev = &pdev->dev;
871
872 irq = platform_get_irq(pdev, 0);
873 if (irq < 0)
874 return irq;
875
876 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
877 if (ret) {
878 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
879 if (ret)
880 return dev_err_probe(dev, ret, "could not set DMA mask\n");
881 }
882
883 base = devm_platform_ioremap_resource(pdev, 0);
884 if (IS_ERR(base))
885 return PTR_ERR(base);
886
887 clk = devm_clk_get(dev, "se");
888 if (IS_ERR(clk))
889 return PTR_ERR(clk);
890
891 spi = devm_spi_alloc_master(dev, sizeof(*mas));
892 if (!spi)
893 return -ENOMEM;
894
895 platform_set_drvdata(pdev, spi);
896 mas = spi_master_get_devdata(spi);
897 mas->irq = irq;
898 mas->dev = dev;
899 mas->se.dev = dev;
900 mas->se.wrapper = dev_get_drvdata(dev->parent);
901 mas->se.base = base;
902 mas->se.clk = clk;
903
904 ret = devm_pm_opp_set_clkname(&pdev->dev, "se");
905 if (ret)
906 return ret;
907 /* OPP table is optional */
908 ret = devm_pm_opp_of_add_table(&pdev->dev);
909 if (ret && ret != -ENODEV) {
910 dev_err(&pdev->dev, "invalid OPP table in device tree\n");
911 return ret;
912 }
913
914 spi->bus_num = -1;
915 spi->dev.of_node = dev->of_node;
916 spi->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP | SPI_CS_HIGH;
917 spi->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
918 spi->num_chipselect = 4;
919 spi->max_speed_hz = 50000000;
920 spi->prepare_message = spi_geni_prepare_message;
921 spi->transfer_one = spi_geni_transfer_one;
922 spi->can_dma = geni_can_dma;
923 spi->dma_map_dev = dev->parent;
924 spi->auto_runtime_pm = true;
925 spi->handle_err = handle_fifo_timeout;
926 spi->use_gpio_descriptors = true;
927
928 init_completion(&mas->cs_done);
929 init_completion(&mas->cancel_done);
930 init_completion(&mas->abort_done);
931 spin_lock_init(&mas->lock);
932 pm_runtime_use_autosuspend(&pdev->dev);
933 pm_runtime_set_autosuspend_delay(&pdev->dev, 250);
934 pm_runtime_enable(dev);
935
936 ret = geni_icc_get(&mas->se, NULL);
937 if (ret)
938 goto spi_geni_probe_runtime_disable;
939 /* Set the bus quota to a reasonable value for register access */
940 mas->se.icc_paths[GENI_TO_CORE].avg_bw = Bps_to_icc(CORE_2X_50_MHZ);
941 mas->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW;
942
943 ret = geni_icc_set_bw(&mas->se);
944 if (ret)
945 goto spi_geni_probe_runtime_disable;
946
947 ret = spi_geni_init(mas);
948 if (ret)
949 goto spi_geni_probe_runtime_disable;
950
951 /*
952 * check the mode supported and set_cs for fifo mode only
953 * for dma (gsi) mode, the gsi will set cs based on params passed in
954 * TRE
955 */
956 if (mas->cur_xfer_mode == GENI_SE_FIFO)
957 spi->set_cs = spi_geni_set_cs;
958
959 ret = request_irq(mas->irq, geni_spi_isr, 0, dev_name(dev), spi);
960 if (ret)
961 goto spi_geni_release_dma;
962
963 ret = spi_register_master(spi);
964 if (ret)
965 goto spi_geni_probe_free_irq;
966
967 return 0;
968 spi_geni_probe_free_irq:
969 free_irq(mas->irq, spi);
970 spi_geni_release_dma:
971 spi_geni_release_dma_chan(mas);
972 spi_geni_probe_runtime_disable:
973 pm_runtime_disable(dev);
974 return ret;
975 }
976
spi_geni_remove(struct platform_device * pdev)977 static int spi_geni_remove(struct platform_device *pdev)
978 {
979 struct spi_master *spi = platform_get_drvdata(pdev);
980 struct spi_geni_master *mas = spi_master_get_devdata(spi);
981
982 /* Unregister _before_ disabling pm_runtime() so we stop transfers */
983 spi_unregister_master(spi);
984
985 spi_geni_release_dma_chan(mas);
986
987 free_irq(mas->irq, spi);
988 pm_runtime_disable(&pdev->dev);
989 return 0;
990 }
991
spi_geni_runtime_suspend(struct device * dev)992 static int __maybe_unused spi_geni_runtime_suspend(struct device *dev)
993 {
994 struct spi_master *spi = dev_get_drvdata(dev);
995 struct spi_geni_master *mas = spi_master_get_devdata(spi);
996 int ret;
997
998 /* Drop the performance state vote */
999 dev_pm_opp_set_rate(dev, 0);
1000
1001 ret = geni_se_resources_off(&mas->se);
1002 if (ret)
1003 return ret;
1004
1005 return geni_icc_disable(&mas->se);
1006 }
1007
spi_geni_runtime_resume(struct device * dev)1008 static int __maybe_unused spi_geni_runtime_resume(struct device *dev)
1009 {
1010 struct spi_master *spi = dev_get_drvdata(dev);
1011 struct spi_geni_master *mas = spi_master_get_devdata(spi);
1012 int ret;
1013
1014 ret = geni_icc_enable(&mas->se);
1015 if (ret)
1016 return ret;
1017
1018 ret = geni_se_resources_on(&mas->se);
1019 if (ret)
1020 return ret;
1021
1022 return dev_pm_opp_set_rate(mas->dev, mas->cur_sclk_hz);
1023 }
1024
spi_geni_suspend(struct device * dev)1025 static int __maybe_unused spi_geni_suspend(struct device *dev)
1026 {
1027 struct spi_master *spi = dev_get_drvdata(dev);
1028 int ret;
1029
1030 ret = spi_master_suspend(spi);
1031 if (ret)
1032 return ret;
1033
1034 ret = pm_runtime_force_suspend(dev);
1035 if (ret)
1036 spi_master_resume(spi);
1037
1038 return ret;
1039 }
1040
spi_geni_resume(struct device * dev)1041 static int __maybe_unused spi_geni_resume(struct device *dev)
1042 {
1043 struct spi_master *spi = dev_get_drvdata(dev);
1044 int ret;
1045
1046 ret = pm_runtime_force_resume(dev);
1047 if (ret)
1048 return ret;
1049
1050 ret = spi_master_resume(spi);
1051 if (ret)
1052 pm_runtime_force_suspend(dev);
1053
1054 return ret;
1055 }
1056
1057 static const struct dev_pm_ops spi_geni_pm_ops = {
1058 SET_RUNTIME_PM_OPS(spi_geni_runtime_suspend,
1059 spi_geni_runtime_resume, NULL)
1060 SET_SYSTEM_SLEEP_PM_OPS(spi_geni_suspend, spi_geni_resume)
1061 };
1062
1063 static const struct of_device_id spi_geni_dt_match[] = {
1064 { .compatible = "qcom,geni-spi" },
1065 {}
1066 };
1067 MODULE_DEVICE_TABLE(of, spi_geni_dt_match);
1068
1069 static struct platform_driver spi_geni_driver = {
1070 .probe = spi_geni_probe,
1071 .remove = spi_geni_remove,
1072 .driver = {
1073 .name = "geni_spi",
1074 .pm = &spi_geni_pm_ops,
1075 .of_match_table = spi_geni_dt_match,
1076 },
1077 };
1078 module_platform_driver(spi_geni_driver);
1079
1080 MODULE_DESCRIPTION("SPI driver for GENI based QUP cores");
1081 MODULE_LICENSE("GPL v2");
1082