1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2007 - 2011 Realtek Corporation. */ 3 4 #ifndef __HALPWRSEQCMD_H__ 5 #define __HALPWRSEQCMD_H__ 6 7 #include "drv_types.h" 8 9 /*---------------------------------------------*/ 10 /* 3 The value of cmd: 4 bits */ 11 /*---------------------------------------------*/ 12 #define PWR_CMD_READ 0x00 13 /* offset: the read register offset */ 14 /* msk: the mask of the read value */ 15 /* value: N/A, left by 0 */ 16 /* note: dirver shall implement this function by read & msk */ 17 18 #define PWR_CMD_WRITE 0x01 19 /* offset: the read register offset */ 20 /* msk: the mask of the write bits */ 21 /* value: write value */ 22 /* note: driver shall implement this cmd by read & msk after write */ 23 24 #define PWR_CMD_POLLING 0x02 25 /* offset: the read register offset */ 26 /* msk: the mask of the polled value */ 27 /* value: the value to be polled, masked by the msd field. */ 28 /* note: driver shall implement this cmd by */ 29 /* do{ */ 30 /* if ( (Read(offset) & msk) == (value & msk) ) */ 31 /* break; */ 32 /* } while (not timeout); */ 33 34 #define PWR_CMD_DELAY 0x03 35 /* offset: the value to delay */ 36 /* msk: N/A */ 37 /* value: the unit of delay, 0: us, 1: ms */ 38 39 #define PWR_CMD_END 0x04 40 /* offset: N/A */ 41 /* msk: N/A */ 42 /* value: N/A */ 43 44 /*---------------------------------------------*/ 45 /* 3 The value of base: 4 bits */ 46 /*---------------------------------------------*/ 47 /* define the base address of each block */ 48 #define PWR_BASEADDR_MAC 0x00 49 #define PWR_BASEADDR_USB 0x01 50 #define PWR_BASEADDR_PCIE 0x02 51 #define PWR_BASEADDR_SDIO 0x03 52 53 /*---------------------------------------------*/ 54 /* 3 The value of interface_msk: 4 bits */ 55 /*---------------------------------------------*/ 56 #define PWR_INTF_SDIO_MSK BIT(0) 57 #define PWR_INTF_USB_MSK BIT(1) 58 #define PWR_INTF_PCI_MSK BIT(2) 59 #define PWR_INTF_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3)) 60 61 /*---------------------------------------------*/ 62 /* 3 The value of fab_msk: 4 bits */ 63 /*---------------------------------------------*/ 64 #define PWR_FAB_TSMC_MSK BIT(0) 65 #define PWR_FAB_UMC_MSK BIT(1) 66 #define PWR_FAB_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3)) 67 68 /*---------------------------------------------*/ 69 /* 3 The value of cut_msk: 8 bits */ 70 /*---------------------------------------------*/ 71 #define PWR_CUT_TESTCHIP_MSK BIT(0) 72 #define PWR_CUT_A_MSK BIT(1) 73 #define PWR_CUT_B_MSK BIT(2) 74 #define PWR_CUT_C_MSK BIT(3) 75 #define PWR_CUT_D_MSK BIT(4) 76 #define PWR_CUT_E_MSK BIT(5) 77 #define PWR_CUT_F_MSK BIT(6) 78 #define PWR_CUT_G_MSK BIT(7) 79 #define PWR_CUT_ALL_MSK 0xFF 80 81 enum pwrseq_cmd_delat_unit { 82 PWRSEQ_DELAY_US, 83 PWRSEQ_DELAY_MS, 84 }; 85 86 struct wl_pwr_cfg { 87 u16 offset; 88 u8 cut_msk; 89 u8 fab_msk:4; 90 u8 interface_msk:4; 91 u8 base:4; 92 u8 cmd:4; 93 u8 msk; 94 u8 value; 95 }; 96 97 #define GET_PWR_CFG_OFFSET(__PWR_CMD) __PWR_CMD.offset 98 #define GET_PWR_CFG_CUT_MASK(__PWR_CMD) __PWR_CMD.cut_msk 99 #define GET_PWR_CFG_FAB_MASK(__PWR_CMD) __PWR_CMD.fab_msk 100 #define GET_PWR_CFG_INTF_MASK(__PWR_CMD) __PWR_CMD.interface_msk 101 #define GET_PWR_CFG_BASE(__PWR_CMD) __PWR_CMD.base 102 #define GET_PWR_CFG_CMD(__PWR_CMD) __PWR_CMD.cmd 103 #define GET_PWR_CFG_MASK(__PWR_CMD) __PWR_CMD.msk 104 #define GET_PWR_CFG_VALUE(__PWR_CMD) __PWR_CMD.value 105 106 /* Prototype of protected function. */ 107 u8 HalPwrSeqCmdParsing(struct adapter *padapter, u8 CutVersion, u8 FabVersion, 108 u8 InterfaceType, struct wl_pwr_cfg PwrCfgCmd[]); 109 110 #endif 111