1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 *
4 * Implementation of primary ALSA driver code base for NVIDIA Tegra HDA.
5 */
6
7 #include <linux/clk.h>
8 #include <linux/clocksource.h>
9 #include <linux/completion.h>
10 #include <linux/delay.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/init.h>
13 #include <linux/interrupt.h>
14 #include <linux/io.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/moduleparam.h>
18 #include <linux/mutex.h>
19 #include <linux/of_device.h>
20 #include <linux/reset.h>
21 #include <linux/slab.h>
22 #include <linux/time.h>
23 #include <linux/string.h>
24 #include <linux/pm_runtime.h>
25
26 #include <sound/core.h>
27 #include <sound/initval.h>
28
29 #include <sound/hda_codec.h>
30 #include "hda_controller.h"
31
32 /* Defines for Nvidia Tegra HDA support */
33 #define HDA_BAR0 0x8000
34
35 #define HDA_CFG_CMD 0x1004
36 #define HDA_CFG_BAR0 0x1010
37
38 #define HDA_ENABLE_IO_SPACE (1 << 0)
39 #define HDA_ENABLE_MEM_SPACE (1 << 1)
40 #define HDA_ENABLE_BUS_MASTER (1 << 2)
41 #define HDA_ENABLE_SERR (1 << 8)
42 #define HDA_DISABLE_INTR (1 << 10)
43 #define HDA_BAR0_INIT_PROGRAM 0xFFFFFFFF
44 #define HDA_BAR0_FINAL_PROGRAM (1 << 14)
45
46 /* IPFS */
47 #define HDA_IPFS_CONFIG 0x180
48 #define HDA_IPFS_EN_FPCI 0x1
49
50 #define HDA_IPFS_FPCI_BAR0 0x80
51 #define HDA_FPCI_BAR0_START 0x40
52
53 #define HDA_IPFS_INTR_MASK 0x188
54 #define HDA_IPFS_EN_INTR (1 << 16)
55
56 /* FPCI */
57 #define FPCI_DBG_CFG_2 0x10F4
58 #define FPCI_GCAP_NSDO_SHIFT 18
59 #define FPCI_GCAP_NSDO_MASK (0x3 << FPCI_GCAP_NSDO_SHIFT)
60
61 /* max number of SDs */
62 #define NUM_CAPTURE_SD 1
63 #define NUM_PLAYBACK_SD 1
64
65 /*
66 * Tegra194 does not reflect correct number of SDO lines. Below macro
67 * is used to update the GCAP register to workaround the issue.
68 */
69 #define TEGRA194_NUM_SDO_LINES 4
70
71 struct hda_tegra {
72 struct azx chip;
73 struct device *dev;
74 struct reset_control *reset;
75 struct clk_bulk_data clocks[3];
76 unsigned int nclocks;
77 void __iomem *regs;
78 struct work_struct probe_work;
79 };
80
81 #ifdef CONFIG_PM
82 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
83 module_param(power_save, bint, 0644);
84 MODULE_PARM_DESC(power_save,
85 "Automatic power-saving timeout (in seconds, 0 = disable).");
86 #else
87 #define power_save 0
88 #endif
89
90 static const struct hda_controller_ops hda_tegra_ops; /* nothing special */
91
hda_tegra_init(struct hda_tegra * hda)92 static void hda_tegra_init(struct hda_tegra *hda)
93 {
94 u32 v;
95
96 /* Enable PCI access */
97 v = readl(hda->regs + HDA_IPFS_CONFIG);
98 v |= HDA_IPFS_EN_FPCI;
99 writel(v, hda->regs + HDA_IPFS_CONFIG);
100
101 /* Enable MEM/IO space and bus master */
102 v = readl(hda->regs + HDA_CFG_CMD);
103 v &= ~HDA_DISABLE_INTR;
104 v |= HDA_ENABLE_MEM_SPACE | HDA_ENABLE_IO_SPACE |
105 HDA_ENABLE_BUS_MASTER | HDA_ENABLE_SERR;
106 writel(v, hda->regs + HDA_CFG_CMD);
107
108 writel(HDA_BAR0_INIT_PROGRAM, hda->regs + HDA_CFG_BAR0);
109 writel(HDA_BAR0_FINAL_PROGRAM, hda->regs + HDA_CFG_BAR0);
110 writel(HDA_FPCI_BAR0_START, hda->regs + HDA_IPFS_FPCI_BAR0);
111
112 v = readl(hda->regs + HDA_IPFS_INTR_MASK);
113 v |= HDA_IPFS_EN_INTR;
114 writel(v, hda->regs + HDA_IPFS_INTR_MASK);
115 }
116
117 /*
118 * power management
119 */
hda_tegra_suspend(struct device * dev)120 static int __maybe_unused hda_tegra_suspend(struct device *dev)
121 {
122 struct snd_card *card = dev_get_drvdata(dev);
123 int rc;
124
125 rc = pm_runtime_force_suspend(dev);
126 if (rc < 0)
127 return rc;
128 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
129
130 return 0;
131 }
132
hda_tegra_resume(struct device * dev)133 static int __maybe_unused hda_tegra_resume(struct device *dev)
134 {
135 struct snd_card *card = dev_get_drvdata(dev);
136 int rc;
137
138 rc = pm_runtime_force_resume(dev);
139 if (rc < 0)
140 return rc;
141 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
142
143 return 0;
144 }
145
hda_tegra_runtime_suspend(struct device * dev)146 static int __maybe_unused hda_tegra_runtime_suspend(struct device *dev)
147 {
148 struct snd_card *card = dev_get_drvdata(dev);
149 struct azx *chip = card->private_data;
150 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
151
152 if (chip && chip->running) {
153 /* enable controller wake up event */
154 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
155 STATESTS_INT_MASK);
156
157 azx_stop_chip(chip);
158 azx_enter_link_reset(chip);
159 }
160 clk_bulk_disable_unprepare(hda->nclocks, hda->clocks);
161
162 return 0;
163 }
164
hda_tegra_runtime_resume(struct device * dev)165 static int __maybe_unused hda_tegra_runtime_resume(struct device *dev)
166 {
167 struct snd_card *card = dev_get_drvdata(dev);
168 struct azx *chip = card->private_data;
169 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
170 int rc;
171
172 if (!chip->running) {
173 rc = reset_control_assert(hda->reset);
174 if (rc)
175 return rc;
176 }
177
178 rc = clk_bulk_prepare_enable(hda->nclocks, hda->clocks);
179 if (rc != 0)
180 return rc;
181 if (chip->running) {
182 hda_tegra_init(hda);
183 azx_init_chip(chip, 1);
184 /* disable controller wake up event*/
185 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
186 ~STATESTS_INT_MASK);
187 } else {
188 usleep_range(10, 100);
189
190 rc = reset_control_deassert(hda->reset);
191 if (rc)
192 return rc;
193 }
194
195 return 0;
196 }
197
198 static const struct dev_pm_ops hda_tegra_pm = {
199 SET_SYSTEM_SLEEP_PM_OPS(hda_tegra_suspend, hda_tegra_resume)
200 SET_RUNTIME_PM_OPS(hda_tegra_runtime_suspend,
201 hda_tegra_runtime_resume,
202 NULL)
203 };
204
hda_tegra_dev_disconnect(struct snd_device * device)205 static int hda_tegra_dev_disconnect(struct snd_device *device)
206 {
207 struct azx *chip = device->device_data;
208
209 chip->bus.shutdown = 1;
210 return 0;
211 }
212
213 /*
214 * destructor
215 */
hda_tegra_dev_free(struct snd_device * device)216 static int hda_tegra_dev_free(struct snd_device *device)
217 {
218 struct azx *chip = device->device_data;
219 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
220
221 cancel_work_sync(&hda->probe_work);
222 if (azx_bus(chip)->chip_init) {
223 azx_stop_all_streams(chip);
224 azx_stop_chip(chip);
225 }
226
227 azx_free_stream_pages(chip);
228 azx_free_streams(chip);
229 snd_hdac_bus_exit(azx_bus(chip));
230
231 return 0;
232 }
233
hda_tegra_init_chip(struct azx * chip,struct platform_device * pdev)234 static int hda_tegra_init_chip(struct azx *chip, struct platform_device *pdev)
235 {
236 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
237 struct hdac_bus *bus = azx_bus(chip);
238 struct resource *res;
239
240 hda->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
241 if (IS_ERR(hda->regs))
242 return PTR_ERR(hda->regs);
243
244 bus->remap_addr = hda->regs + HDA_BAR0;
245 bus->addr = res->start + HDA_BAR0;
246
247 hda_tegra_init(hda);
248
249 return 0;
250 }
251
hda_tegra_first_init(struct azx * chip,struct platform_device * pdev)252 static int hda_tegra_first_init(struct azx *chip, struct platform_device *pdev)
253 {
254 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
255 struct hdac_bus *bus = azx_bus(chip);
256 struct snd_card *card = chip->card;
257 int err;
258 unsigned short gcap;
259 int irq_id = platform_get_irq(pdev, 0);
260 const char *sname, *drv_name = "tegra-hda";
261 struct device_node *np = pdev->dev.of_node;
262
263 if (irq_id < 0)
264 return irq_id;
265
266 err = hda_tegra_init_chip(chip, pdev);
267 if (err)
268 return err;
269
270 err = devm_request_irq(chip->card->dev, irq_id, azx_interrupt,
271 IRQF_SHARED, KBUILD_MODNAME, chip);
272 if (err) {
273 dev_err(chip->card->dev,
274 "unable to request IRQ %d, disabling device\n",
275 irq_id);
276 return err;
277 }
278 bus->irq = irq_id;
279 bus->dma_stop_delay = 100;
280 card->sync_irq = bus->irq;
281
282 /*
283 * Tegra194 has 4 SDO lines and the STRIPE can be used to
284 * indicate how many of the SDO lines the stream should be
285 * striped. But GCAP register does not reflect the true
286 * capability of HW. Below workaround helps to fix this.
287 *
288 * GCAP_NSDO is bits 19:18 in T_AZA_DBG_CFG_2,
289 * 0 for 1 SDO, 1 for 2 SDO, 2 for 4 SDO lines.
290 */
291 if (of_device_is_compatible(np, "nvidia,tegra194-hda")) {
292 u32 val;
293
294 dev_info(card->dev, "Override SDO lines to %u\n",
295 TEGRA194_NUM_SDO_LINES);
296
297 val = readl(hda->regs + FPCI_DBG_CFG_2) & ~FPCI_GCAP_NSDO_MASK;
298 val |= (TEGRA194_NUM_SDO_LINES >> 1) << FPCI_GCAP_NSDO_SHIFT;
299 writel(val, hda->regs + FPCI_DBG_CFG_2);
300 }
301
302 gcap = azx_readw(chip, GCAP);
303 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
304
305 chip->align_buffer_size = 1;
306
307 /* read number of streams from GCAP register instead of using
308 * hardcoded value
309 */
310 chip->capture_streams = (gcap >> 8) & 0x0f;
311 chip->playback_streams = (gcap >> 12) & 0x0f;
312 if (!chip->playback_streams && !chip->capture_streams) {
313 /* gcap didn't give any info, switching to old method */
314 chip->playback_streams = NUM_PLAYBACK_SD;
315 chip->capture_streams = NUM_CAPTURE_SD;
316 }
317 chip->capture_index_offset = 0;
318 chip->playback_index_offset = chip->capture_streams;
319 chip->num_streams = chip->playback_streams + chip->capture_streams;
320
321 /* initialize streams */
322 err = azx_init_streams(chip);
323 if (err < 0) {
324 dev_err(card->dev, "failed to initialize streams: %d\n", err);
325 return err;
326 }
327
328 err = azx_alloc_stream_pages(chip);
329 if (err < 0) {
330 dev_err(card->dev, "failed to allocate stream pages: %d\n",
331 err);
332 return err;
333 }
334
335 /* initialize chip */
336 azx_init_chip(chip, 1);
337
338 /*
339 * Playback (for 44.1K/48K, 2-channel, 16-bps) fails with
340 * 4 SDO lines due to legacy design limitation. Following
341 * is, from HD Audio Specification (Revision 1.0a), used to
342 * control striping of the stream across multiple SDO lines
343 * for sample rates <= 48K.
344 *
345 * { ((num_channels * bits_per_sample) / number of SDOs) >= 8 }
346 *
347 * Due to legacy design issue it is recommended that above
348 * ratio must be greater than 8. Since number of SDO lines is
349 * in powers of 2, next available ratio is 16 which can be
350 * used as a limiting factor here.
351 */
352 if (of_device_is_compatible(np, "nvidia,tegra30-hda"))
353 chip->bus.core.sdo_limit = 16;
354
355 /* codec detection */
356 if (!bus->codec_mask) {
357 dev_err(card->dev, "no codecs found!\n");
358 return -ENODEV;
359 }
360
361 /* driver name */
362 strncpy(card->driver, drv_name, sizeof(card->driver));
363 /* shortname for card */
364 sname = of_get_property(np, "nvidia,model", NULL);
365 if (!sname)
366 sname = drv_name;
367 if (strlen(sname) > sizeof(card->shortname))
368 dev_info(card->dev, "truncating shortname for card\n");
369 strncpy(card->shortname, sname, sizeof(card->shortname));
370
371 /* longname for card */
372 snprintf(card->longname, sizeof(card->longname),
373 "%s at 0x%lx irq %i",
374 card->shortname, bus->addr, bus->irq);
375
376 return 0;
377 }
378
379 /*
380 * constructor
381 */
382
383 static void hda_tegra_probe_work(struct work_struct *work);
384
hda_tegra_create(struct snd_card * card,unsigned int driver_caps,struct hda_tegra * hda)385 static int hda_tegra_create(struct snd_card *card,
386 unsigned int driver_caps,
387 struct hda_tegra *hda)
388 {
389 static const struct snd_device_ops ops = {
390 .dev_disconnect = hda_tegra_dev_disconnect,
391 .dev_free = hda_tegra_dev_free,
392 };
393 struct azx *chip;
394 int err;
395
396 chip = &hda->chip;
397
398 mutex_init(&chip->open_mutex);
399 chip->card = card;
400 chip->ops = &hda_tegra_ops;
401 chip->driver_caps = driver_caps;
402 chip->driver_type = driver_caps & 0xff;
403 chip->dev_index = 0;
404 INIT_LIST_HEAD(&chip->pcm_list);
405
406 chip->codec_probe_mask = -1;
407
408 chip->single_cmd = false;
409 chip->snoop = true;
410
411 INIT_WORK(&hda->probe_work, hda_tegra_probe_work);
412
413 err = azx_bus_init(chip, NULL);
414 if (err < 0)
415 return err;
416
417 chip->bus.core.sync_write = 0;
418 chip->bus.core.needs_damn_long_delay = 1;
419 chip->bus.core.aligned_mmio = 1;
420
421 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
422 if (err < 0) {
423 dev_err(card->dev, "Error creating device\n");
424 return err;
425 }
426
427 return 0;
428 }
429
430 static const struct of_device_id hda_tegra_match[] = {
431 { .compatible = "nvidia,tegra30-hda" },
432 { .compatible = "nvidia,tegra194-hda" },
433 {},
434 };
435 MODULE_DEVICE_TABLE(of, hda_tegra_match);
436
hda_tegra_probe(struct platform_device * pdev)437 static int hda_tegra_probe(struct platform_device *pdev)
438 {
439 const unsigned int driver_flags = AZX_DCAPS_CORBRP_SELF_CLEAR |
440 AZX_DCAPS_PM_RUNTIME;
441 struct snd_card *card;
442 struct azx *chip;
443 struct hda_tegra *hda;
444 int err;
445
446 hda = devm_kzalloc(&pdev->dev, sizeof(*hda), GFP_KERNEL);
447 if (!hda)
448 return -ENOMEM;
449 hda->dev = &pdev->dev;
450 chip = &hda->chip;
451
452 err = snd_card_new(&pdev->dev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1,
453 THIS_MODULE, 0, &card);
454 if (err < 0) {
455 dev_err(&pdev->dev, "Error creating card!\n");
456 return err;
457 }
458
459 hda->reset = devm_reset_control_array_get_exclusive(&pdev->dev);
460 if (IS_ERR(hda->reset)) {
461 err = PTR_ERR(hda->reset);
462 goto out_free;
463 }
464
465 hda->clocks[hda->nclocks++].id = "hda";
466 hda->clocks[hda->nclocks++].id = "hda2hdmi";
467 hda->clocks[hda->nclocks++].id = "hda2codec_2x";
468
469 err = devm_clk_bulk_get(&pdev->dev, hda->nclocks, hda->clocks);
470 if (err < 0)
471 goto out_free;
472
473 err = hda_tegra_create(card, driver_flags, hda);
474 if (err < 0)
475 goto out_free;
476 card->private_data = chip;
477
478 dev_set_drvdata(&pdev->dev, card);
479
480 pm_runtime_enable(hda->dev);
481 if (!azx_has_pm_runtime(chip))
482 pm_runtime_forbid(hda->dev);
483
484 schedule_work(&hda->probe_work);
485
486 return 0;
487
488 out_free:
489 snd_card_free(card);
490 return err;
491 }
492
hda_tegra_probe_work(struct work_struct * work)493 static void hda_tegra_probe_work(struct work_struct *work)
494 {
495 struct hda_tegra *hda = container_of(work, struct hda_tegra, probe_work);
496 struct azx *chip = &hda->chip;
497 struct platform_device *pdev = to_platform_device(hda->dev);
498 int err;
499
500 pm_runtime_get_sync(hda->dev);
501 err = hda_tegra_first_init(chip, pdev);
502 if (err < 0)
503 goto out_free;
504
505 /* create codec instances */
506 err = azx_probe_codecs(chip, 8);
507 if (err < 0)
508 goto out_free;
509
510 err = azx_codec_configure(chip);
511 if (err < 0)
512 goto out_free;
513
514 err = snd_card_register(chip->card);
515 if (err < 0)
516 goto out_free;
517
518 chip->running = 1;
519 snd_hda_set_power_save(&chip->bus, power_save * 1000);
520
521 out_free:
522 pm_runtime_put(hda->dev);
523 return; /* no error return from async probe */
524 }
525
hda_tegra_remove(struct platform_device * pdev)526 static int hda_tegra_remove(struct platform_device *pdev)
527 {
528 int ret;
529
530 ret = snd_card_free(dev_get_drvdata(&pdev->dev));
531 pm_runtime_disable(&pdev->dev);
532
533 return ret;
534 }
535
hda_tegra_shutdown(struct platform_device * pdev)536 static void hda_tegra_shutdown(struct platform_device *pdev)
537 {
538 struct snd_card *card = dev_get_drvdata(&pdev->dev);
539 struct azx *chip;
540
541 if (!card)
542 return;
543 chip = card->private_data;
544 if (chip && chip->running)
545 azx_stop_chip(chip);
546 }
547
548 static struct platform_driver tegra_platform_hda = {
549 .driver = {
550 .name = "tegra-hda",
551 .pm = &hda_tegra_pm,
552 .of_match_table = hda_tegra_match,
553 },
554 .probe = hda_tegra_probe,
555 .remove = hda_tegra_remove,
556 .shutdown = hda_tegra_shutdown,
557 };
558 module_platform_driver(tegra_platform_hda);
559
560 MODULE_DESCRIPTION("Tegra HDA bus driver");
561 MODULE_LICENSE("GPL v2");
562