1 // SPDX-License-Identifier: BSD-2-Clause
2 /*
3 * Copyright (c) 2021, Aspeed Technology Inc.
4 */
5
6 #include <console.h>
7 #include <drivers/gic.h>
8 #include <drivers/serial8250_uart.h>
9 #include <mm/core_memprot.h>
10 #include <platform_config.h>
11 #include <stdint.h>
12 #include <io.h>
13 #include <kernel/boot.h>
14 #include <kernel/panic.h>
15
16 enum TZM_PERM {
17 TZM_PERM_VGA_CURSOR_RD,
18 TZM_PERM_VGA_CRT_RD,
19 TZM_PERM_SOC_DISPLAY_RD,
20 TZM_PERM_PCIE_BUS1_RW,
21 TZM_PERM_VIDEO_HIGH_WR,
22 TZM_PERM_CPU_RW,
23 TZM_PERM_SLI_RW,
24 TZM_PERM_PCIE_BUS2_RW,
25 TZM_PERM_USB20_HUB_EHCI1_DMA_RW,
26 TZM_PERM_USB20_DEV_EHCI2_DMA_RW,
27 TZM_PERM_USB11_UCHI_HOST_RW,
28 TZM_PERM_AHB_RW,
29 TZM_PERM_CM3_DATA_RW,
30 TZM_PERM_CM3_INSN_RW,
31 TZM_PERM_MAC0_DMA_RW,
32 TZM_PERM_MAC1_DMA_RW,
33 TZM_PERM_SDIO_DMA_RW,
34 TZM_PERM_PILOT_RW,
35 TZM_PERM_XDMA1_RW,
36 TZM_PERM_MCTP1_RW,
37 TZM_PERM_VIDEO_FLAG_RW,
38 TZM_PERM_VIDEO_LOW_WR,
39 TZM_PERM_2D_DATA_RW,
40 TZM_PERM_ENCRYPT_RW,
41 TZM_PERM_MCTP2_RW,
42 TZM_PERM_XDMA2_RW,
43 TZM_PERM_ECC_RSA_RW,
44 };
45
46 register_phys_mem(MEM_AREA_IO_NSEC,
47 CONSOLE_UART_BASE,
48 SMALL_PAGE_SIZE);
49
50 register_phys_mem(MEM_AREA_IO_SEC,
51 GIC_BASE + GICD_OFFSET,
52 SMALL_PAGE_SIZE);
53
54 register_phys_mem(MEM_AREA_IO_SEC,
55 GIC_BASE + GICC_OFFSET,
56 SMALL_PAGE_SIZE);
57
58 register_phys_mem(MEM_AREA_IO_SEC,
59 AHBC_BASE,
60 SMALL_PAGE_SIZE);
61
62 #define AHBC_REG_WR_PROT 0x204
63 #define AHBC_TZM_ST(i) (0x300 + ((i) * 0x10))
64 #define AHBC_TZM_ED(i) (0x304 + ((i) * 0x10))
65 #define AHBC_TZM_PERM(i) (0x308 + ((i) * 0x10))
66
67 register_ddr(CFG_DRAM_BASE, CFG_DRAM_SIZE);
68
69 static struct serial8250_uart_data console_data;
70 static struct gic_data gic_data;
71
main_init_gic(void)72 void main_init_gic(void)
73 {
74 vaddr_t gicc_base = 0;
75 vaddr_t gicd_base = 0;
76
77 gicc_base = core_mmu_get_va(GIC_BASE + GICC_OFFSET,
78 MEM_AREA_IO_SEC, SMALL_PAGE_SIZE);
79 gicd_base = core_mmu_get_va(GIC_BASE + GICD_OFFSET,
80 MEM_AREA_IO_SEC, SMALL_PAGE_SIZE);
81 if (!gicc_base || !gicd_base)
82 panic();
83
84 gic_init(&gic_data, gicc_base, gicd_base);
85 itr_init(&gic_data.chip);
86 }
87
main_secondary_init_gic(void)88 void main_secondary_init_gic(void)
89 {
90 gic_cpu_init(&gic_data);
91 }
92
itr_core_handler(void)93 void itr_core_handler(void)
94 {
95 gic_it_handle(&gic_data);
96 }
97
console_init(void)98 void console_init(void)
99 {
100 serial8250_uart_init(&console_data, CONSOLE_UART_BASE,
101 CONSOLE_UART_CLK_IN_HZ, CONSOLE_BAUDRATE);
102 register_serial_console(&console_data.chip);
103 }
104
plat_primary_init_early(void)105 void plat_primary_init_early(void)
106 {
107 vaddr_t ahbc_virt = 0;
108
109 ahbc_virt = core_mmu_get_va(AHBC_BASE,
110 MEM_AREA_IO_SEC, SMALL_PAGE_SIZE);
111 if (!ahbc_virt)
112 panic();
113
114 io_write32(ahbc_virt + AHBC_TZM_PERM(0),
115 BIT(TZM_PERM_CPU_RW));
116 io_write32(ahbc_virt + AHBC_TZM_ED(0),
117 CFG_TZDRAM_START + CFG_TZDRAM_SIZE - 1);
118 io_write32(ahbc_virt + AHBC_TZM_ST(0),
119 CFG_TZDRAM_START | BIT(0));
120 io_write32(ahbc_virt + AHBC_REG_WR_PROT, BIT(16));
121 }
122