1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright (c) 2014, Allwinner Technology Co., Ltd. 4 * Copyright (c) 2018, Linaro Limited 5 * Copyright (c) 2018, Amit Singh Tomar <amittomer25@gmail.com 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright notice, 12 * this list of conditions and the following disclaimer. 13 * 14 * 2. Redistributions in binary form must reproduce the above copyright notice, 15 * this list of conditions and the following disclaimer in the documentation 16 * and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef PLATFORM_CONFIG_H 32 #define PLATFORM_CONFIG_H 33 34 #include <mm/generic_ram_layout.h> 35 36 /* Make stacks aligned to data cache line length */ 37 #define STACK_ALIGNMENT 64 38 39 /* 16550 UART */ 40 #define CONSOLE_UART_BASE 0x01c28000 /* UART0 */ 41 #define CONSOLE_UART_CLK_IN_HZ 24000000 42 #define CONSOLE_BAUDRATE 115200 43 #define SUNXI_UART_REG_SIZE 0x400 44 45 #if defined(PLATFORM_FLAVOR_bpi_zero) 46 #define GIC_BASE 0x01c80000 47 #define GICC_OFFSET 0x2000 48 #define GICD_OFFSET 0x1000 49 #define SUNXI_TZPC_BASE 0x01c23400 50 #define SUNXI_TZPC_REG_SIZE 0x400 51 #define SUNXI_CPUCFG_BASE 0x01f01c00 52 #define SUNXI_CPUCFG_REG_SIZE 0x400 53 #define SUNXI_PRCM_BASE 0x01f01400 54 #define SUNXI_PRCM_REG_SIZE 0x400 55 #define PRCM_CPU_SOFT_ENTRY_REG 0x164 56 #endif 57 58 #if defined(PLATFORM_FLAVOR_sun50i_a64) 59 #define SUNXI_SMC_BASE 0x01c1e000 60 #endif 61 62 #endif /* PLATFORM_CONFIG_H */ 63