1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
2 /*
3 * Copyright (c) 2017-2019, STMicroelectronics
4 *
5 * The driver API is defined in header file stm32_i2c.h.
6 *
7 * I2C bus driver does not register to the PM framework. It is the
8 * responsibility of the bus owner to call the related STM32 I2C driver
9 * API functions when bus suspends or resumes.
10 */
11
12 #include <arm.h>
13 #include <drivers/clk.h>
14 #include <drivers/clk_dt.h>
15 #include <drivers/stm32_i2c.h>
16 #include <io.h>
17 #include <kernel/delay.h>
18 #include <kernel/dt.h>
19 #include <kernel/boot.h>
20 #include <kernel/panic.h>
21 #include <libfdt.h>
22 #include <stdbool.h>
23 #include <stdlib.h>
24 #include <stm32_util.h>
25 #include <trace.h>
26
27 /* STM32 I2C registers offsets */
28 #define I2C_CR1 0x00U
29 #define I2C_CR2 0x04U
30 #define I2C_OAR1 0x08U
31 #define I2C_OAR2 0x0CU
32 #define I2C_TIMINGR 0x10U
33 #define I2C_TIMEOUTR 0x14U
34 #define I2C_ISR 0x18U
35 #define I2C_ICR 0x1CU
36 #define I2C_PECR 0x20U
37 #define I2C_RXDR 0x24U
38 #define I2C_TXDR 0x28U
39 #define I2C_SIZE 0x2CU
40
41 /* Bit definition for I2C_CR1 register */
42 #define I2C_CR1_PE BIT(0)
43 #define I2C_CR1_TXIE BIT(1)
44 #define I2C_CR1_RXIE BIT(2)
45 #define I2C_CR1_ADDRIE BIT(3)
46 #define I2C_CR1_NACKIE BIT(4)
47 #define I2C_CR1_STOPIE BIT(5)
48 #define I2C_CR1_TCIE BIT(6)
49 #define I2C_CR1_ERRIE BIT(7)
50 #define I2C_CR1_DNF GENMASK_32(11, 8)
51 #define I2C_CR1_ANFOFF BIT(12)
52 #define I2C_CR1_SWRST BIT(13)
53 #define I2C_CR1_TXDMAEN BIT(14)
54 #define I2C_CR1_RXDMAEN BIT(15)
55 #define I2C_CR1_SBC BIT(16)
56 #define I2C_CR1_NOSTRETCH BIT(17)
57 #define I2C_CR1_WUPEN BIT(18)
58 #define I2C_CR1_GCEN BIT(19)
59 #define I2C_CR1_SMBHEN BIT(22)
60 #define I2C_CR1_SMBDEN BIT(21)
61 #define I2C_CR1_ALERTEN BIT(22)
62 #define I2C_CR1_PECEN BIT(23)
63
64 /* Bit definition for I2C_CR2 register */
65 #define I2C_CR2_SADD GENMASK_32(9, 0)
66 #define I2C_CR2_RD_WRN BIT(10)
67 #define I2C_CR2_RD_WRN_OFFSET 10U
68 #define I2C_CR2_ADD10 BIT(11)
69 #define I2C_CR2_HEAD10R BIT(12)
70 #define I2C_CR2_START BIT(13)
71 #define I2C_CR2_STOP BIT(14)
72 #define I2C_CR2_NACK BIT(15)
73 #define I2C_CR2_NBYTES GENMASK_32(23, 16)
74 #define I2C_CR2_NBYTES_OFFSET 16U
75 #define I2C_CR2_RELOAD BIT(24)
76 #define I2C_CR2_AUTOEND BIT(25)
77 #define I2C_CR2_PECBYTE BIT(26)
78
79 /* Bit definition for I2C_OAR1 register */
80 #define I2C_OAR1_OA1 GENMASK_32(9, 0)
81 #define I2C_OAR1_OA1MODE BIT(10)
82 #define I2C_OAR1_OA1EN BIT(15)
83
84 /* Bit definition for I2C_OAR2 register */
85 #define I2C_OAR2_OA2 GENMASK_32(7, 1)
86 #define I2C_OAR2_OA2MSK GENMASK_32(10, 8)
87 #define I2C_OAR2_OA2NOMASK 0
88 #define I2C_OAR2_OA2MASK01 BIT(8)
89 #define I2C_OAR2_OA2MASK02 BIT(9)
90 #define I2C_OAR2_OA2MASK03 GENMASK_32(9, 8)
91 #define I2C_OAR2_OA2MASK04 BIT(10)
92 #define I2C_OAR2_OA2MASK05 (BIT(8) | BIT(10))
93 #define I2C_OAR2_OA2MASK06 (BIT(9) | BIT(10))
94 #define I2C_OAR2_OA2MASK07 GENMASK_32(10, 8)
95 #define I2C_OAR2_OA2EN BIT(15)
96
97 /* Bit definition for I2C_TIMINGR register */
98 #define I2C_TIMINGR_SCLL GENMASK_32(7, 0)
99 #define I2C_TIMINGR_SCLH GENMASK_32(15, 8)
100 #define I2C_TIMINGR_SDADEL GENMASK_32(19, 16)
101 #define I2C_TIMINGR_SCLDEL GENMASK_32(23, 20)
102 #define I2C_TIMINGR_PRESC GENMASK_32(31, 28)
103 #define I2C_TIMINGR_SCLL_MAX (I2C_TIMINGR_SCLL + 1)
104 #define I2C_TIMINGR_SCLH_MAX ((I2C_TIMINGR_SCLH >> 8) + 1)
105 #define I2C_TIMINGR_SDADEL_MAX ((I2C_TIMINGR_SDADEL >> 16) + 1)
106 #define I2C_TIMINGR_SCLDEL_MAX ((I2C_TIMINGR_SCLDEL >> 20) + 1)
107 #define I2C_TIMINGR_PRESC_MAX ((I2C_TIMINGR_PRESC >> 28) + 1)
108 #define I2C_SET_TIMINGR_SCLL(n) ((n) & \
109 (I2C_TIMINGR_SCLL_MAX - 1))
110 #define I2C_SET_TIMINGR_SCLH(n) (((n) & \
111 (I2C_TIMINGR_SCLH_MAX - 1)) << 8)
112 #define I2C_SET_TIMINGR_SDADEL(n) (((n) & \
113 (I2C_TIMINGR_SDADEL_MAX - 1)) << 16)
114 #define I2C_SET_TIMINGR_SCLDEL(n) (((n) & \
115 (I2C_TIMINGR_SCLDEL_MAX - 1)) << 20)
116 #define I2C_SET_TIMINGR_PRESC(n) (((n) & \
117 (I2C_TIMINGR_PRESC_MAX - 1)) << 28)
118
119 /* Bit definition for I2C_TIMEOUTR register */
120 #define I2C_TIMEOUTR_TIMEOUTA GENMASK_32(11, 0)
121 #define I2C_TIMEOUTR_TIDLE BIT(12)
122 #define I2C_TIMEOUTR_TIMOUTEN BIT(15)
123 #define I2C_TIMEOUTR_TIMEOUTB GENMASK_32(27, 16)
124 #define I2C_TIMEOUTR_TEXTEN BIT(31)
125
126 /* Bit definition for I2C_ISR register */
127 #define I2C_ISR_TXE BIT(0)
128 #define I2C_ISR_TXIS BIT(1)
129 #define I2C_ISR_RXNE BIT(2)
130 #define I2C_ISR_ADDR BIT(3)
131 #define I2C_ISR_NACKF BIT(4)
132 #define I2C_ISR_STOPF BIT(5)
133 #define I2C_ISR_TC BIT(6)
134 #define I2C_ISR_TCR BIT(7)
135 #define I2C_ISR_BERR BIT(8)
136 #define I2C_ISR_ARLO BIT(9)
137 #define I2C_ISR_OVR BIT(10)
138 #define I2C_ISR_PECERR BIT(11)
139 #define I2C_ISR_TIMEOUT BIT(12)
140 #define I2C_ISR_ALERT BIT(13)
141 #define I2C_ISR_BUSY BIT(15)
142 #define I2C_ISR_DIR BIT(16)
143 #define I2C_ISR_ADDCODE GENMASK_32(23, 17)
144
145 /* Bit definition for I2C_ICR register */
146 #define I2C_ICR_ADDRCF BIT(3)
147 #define I2C_ICR_NACKCF BIT(4)
148 #define I2C_ICR_STOPCF BIT(5)
149 #define I2C_ICR_BERRCF BIT(8)
150 #define I2C_ICR_ARLOCF BIT(9)
151 #define I2C_ICR_OVRCF BIT(10)
152 #define I2C_ICR_PECCF BIT(11)
153 #define I2C_ICR_TIMOUTCF BIT(12)
154 #define I2C_ICR_ALERTCF BIT(13)
155
156 /* Max data size for a single I2C transfer */
157 #define MAX_NBYTE_SIZE 255U
158
159 #define I2C_NSEC_PER_SEC 1000000000UL
160 #define I2C_TIMEOUT_BUSY_MS 25
161 #define I2C_TIMEOUT_BUSY_US (I2C_TIMEOUT_BUSY_MS * 1000)
162
163 #define CR2_RESET_MASK (I2C_CR2_SADD | I2C_CR2_HEAD10R | \
164 I2C_CR2_NBYTES | I2C_CR2_RELOAD | \
165 I2C_CR2_RD_WRN)
166
167 #define TIMINGR_CLEAR_MASK (I2C_TIMINGR_SCLL | I2C_TIMINGR_SCLH | \
168 I2C_TIMINGR_SDADEL | \
169 I2C_TIMINGR_SCLDEL | I2C_TIMINGR_PRESC)
170
171 /*
172 * I2C transfer modes
173 * I2C_RELOAD: Enable Reload mode
174 * I2C_AUTOEND_MODE: Enable automatic end mode
175 * I2C_SOFTEND_MODE: Enable software end mode
176 */
177 #define I2C_RELOAD_MODE I2C_CR2_RELOAD
178 #define I2C_AUTOEND_MODE I2C_CR2_AUTOEND
179 #define I2C_SOFTEND_MODE 0x0
180
181 /*
182 * Start/restart/stop I2C transfer requests.
183 *
184 * I2C_NO_STARTSTOP: Don't Generate stop and start condition
185 * I2C_GENERATE_STOP: Generate stop condition (size should be set to 0)
186 * I2C_GENERATE_START_READ: Generate Restart for read request.
187 * I2C_GENERATE_START_WRITE: Generate Restart for write request
188 */
189 #define I2C_NO_STARTSTOP 0x0
190 #define I2C_GENERATE_STOP (BIT(31) | I2C_CR2_STOP)
191 #define I2C_GENERATE_START_READ (BIT(31) | I2C_CR2_START | \
192 I2C_CR2_RD_WRN)
193 #define I2C_GENERATE_START_WRITE (BIT(31) | I2C_CR2_START)
194
195 /* Memory address byte sizes */
196 #define I2C_MEMADD_SIZE_8BIT 1
197 #define I2C_MEMADD_SIZE_16BIT 2
198
199 /* Effective rate cannot be lower than 80% target rate */
200 #define RATE_MIN(rate) (((rate) * 80U) / 100U)
201
202 /*
203 * struct i2c_spec_s - Private I2C timing specifications.
204 * @rate: I2C bus speed (Hz)
205 * @fall_max: Max fall time of both SDA and SCL signals (ns)
206 * @rise_max: Max rise time of both SDA and SCL signals (ns)
207 * @hddat_min: Min data hold time (ns)
208 * @vddat_max: Max data valid time (ns)
209 * @sudat_min: Min data setup time (ns)
210 * @l_min: Min low period of the SCL clock (ns)
211 * @h_min: Min high period of the SCL clock (ns)
212 */
213 struct i2c_spec_s {
214 uint32_t rate;
215 uint32_t fall_max;
216 uint32_t rise_max;
217 uint32_t hddat_min;
218 uint32_t vddat_max;
219 uint32_t sudat_min;
220 uint32_t l_min;
221 uint32_t h_min;
222 };
223
224 /*
225 * struct i2c_timing_s - Private I2C output parameters.
226 * @scldel: Data setup time
227 * @sdadel: Data hold time
228 * @sclh: SCL high period (master mode)
229 * @sclh: SCL low period (master mode)
230 * @is_saved: True if relating to a configuration candidate
231 */
232 struct i2c_timing_s {
233 uint8_t scldel;
234 uint8_t sdadel;
235 uint8_t sclh;
236 uint8_t scll;
237 bool is_saved;
238 };
239
240 /* This table must be sorted in increasing value for field @rate */
241 static const struct i2c_spec_s i2c_specs[] = {
242 /* Standard - 100KHz */
243 {
244 .rate = I2C_STANDARD_RATE,
245 .fall_max = 300,
246 .rise_max = 1000,
247 .hddat_min = 0,
248 .vddat_max = 3450,
249 .sudat_min = 250,
250 .l_min = 4700,
251 .h_min = 4000,
252 },
253 /* Fast - 400KHz */
254 {
255 .rate = I2C_FAST_RATE,
256 .fall_max = 300,
257 .rise_max = 300,
258 .hddat_min = 0,
259 .vddat_max = 900,
260 .sudat_min = 100,
261 .l_min = 1300,
262 .h_min = 600,
263 },
264 /* FastPlus - 1MHz */
265 {
266 .rate = I2C_FAST_PLUS_RATE,
267 .fall_max = 100,
268 .rise_max = 120,
269 .hddat_min = 0,
270 .vddat_max = 450,
271 .sudat_min = 50,
272 .l_min = 500,
273 .h_min = 260,
274 },
275 };
276
277 /*
278 * I2C request parameters
279 * @dev_addr: I2C address of the target device
280 * @mode: Communication mode, one of I2C_MODE_(MASTER|MEM)
281 * @mem_addr: Target memory cell accessed in device (memory mode)
282 * @mem_addr_size: Byte size of the memory cell address (memory mode)
283 * @timeout_ms: Timeout in millisenconds for the request
284 */
285 struct i2c_request {
286 uint32_t dev_addr;
287 enum i2c_mode_e mode;
288 uint32_t mem_addr;
289 uint32_t mem_addr_size;
290 unsigned int timeout_ms;
291 };
292
get_base(struct i2c_handle_s * hi2c)293 static vaddr_t get_base(struct i2c_handle_s *hi2c)
294 {
295 return io_pa_or_va_secure(&hi2c->base, hi2c->reg_size);
296 }
297
notif_i2c_timeout(struct i2c_handle_s * hi2c)298 static void notif_i2c_timeout(struct i2c_handle_s *hi2c)
299 {
300 hi2c->i2c_err |= I2C_ERROR_TIMEOUT;
301 hi2c->i2c_state = I2C_STATE_READY;
302 }
303
get_specs(uint32_t rate)304 static const struct i2c_spec_s *get_specs(uint32_t rate)
305 {
306 size_t i = 0;
307
308 for (i = 0; i < ARRAY_SIZE(i2c_specs); i++)
309 if (rate <= i2c_specs[i].rate)
310 return i2c_specs + i;
311
312 return NULL;
313 }
314
save_cfg(struct i2c_handle_s * hi2c,struct i2c_cfg * cfg)315 static void save_cfg(struct i2c_handle_s *hi2c, struct i2c_cfg *cfg)
316 {
317 vaddr_t base = get_base(hi2c);
318
319 clk_enable(hi2c->clock);
320
321 cfg->cr1 = io_read32(base + I2C_CR1);
322 cfg->cr2 = io_read32(base + I2C_CR2);
323 cfg->oar1 = io_read32(base + I2C_OAR1);
324 cfg->oar2 = io_read32(base + I2C_OAR2);
325 cfg->timingr = io_read32(base + I2C_TIMINGR);
326
327 clk_disable(hi2c->clock);
328 }
329
restore_cfg(struct i2c_handle_s * hi2c,struct i2c_cfg * cfg)330 static void restore_cfg(struct i2c_handle_s *hi2c, struct i2c_cfg *cfg)
331 {
332 vaddr_t base = get_base(hi2c);
333
334 clk_enable(hi2c->clock);
335
336 io_clrbits32(base + I2C_CR1, I2C_CR1_PE);
337 io_write32(base + I2C_TIMINGR, cfg->timingr & TIMINGR_CLEAR_MASK);
338 io_write32(base + I2C_OAR1, cfg->oar1);
339 io_write32(base + I2C_CR2, cfg->cr2);
340 io_write32(base + I2C_OAR2, cfg->oar2);
341 io_write32(base + I2C_CR1, cfg->cr1 & ~I2C_CR1_PE);
342 io_setbits32(base + I2C_CR1, cfg->cr1 & I2C_CR1_PE);
343
344 clk_disable(hi2c->clock);
345 }
346
dump_cfg(struct i2c_cfg * cfg __maybe_unused)347 static void __maybe_unused dump_cfg(struct i2c_cfg *cfg __maybe_unused)
348 {
349 DMSG("CR1: %#"PRIx32, cfg->cr1);
350 DMSG("CR2: %#"PRIx32, cfg->cr2);
351 DMSG("OAR1: %#"PRIx32, cfg->oar1);
352 DMSG("OAR2: %#"PRIx32, cfg->oar2);
353 DMSG("TIM: %#"PRIx32, cfg->timingr);
354 }
355
dump_i2c(struct i2c_handle_s * hi2c)356 static void __maybe_unused dump_i2c(struct i2c_handle_s *hi2c)
357 {
358 vaddr_t __maybe_unused base = get_base(hi2c);
359
360 clk_enable(hi2c->clock);
361
362 DMSG("CR1: %#"PRIx32, io_read32(base + I2C_CR1));
363 DMSG("CR2: %#"PRIx32, io_read32(base + I2C_CR2));
364 DMSG("OAR1: %#"PRIx32, io_read32(base + I2C_OAR1));
365 DMSG("OAR2: %#"PRIx32, io_read32(base + I2C_OAR2));
366 DMSG("TIM: %#"PRIx32, io_read32(base + I2C_TIMINGR));
367
368 clk_disable(hi2c->clock);
369 }
370
371 /*
372 * Compute the I2C device timings
373 *
374 * @init: Ref to the initialization configuration structure
375 * @clock_src: I2C clock source frequency (Hz)
376 * @timing: Pointer to the final computed timing result
377 * Return 0 on success or a negative value
378 */
i2c_compute_timing(struct stm32_i2c_init_s * init,unsigned long clock_src,uint32_t * timing)379 static int i2c_compute_timing(struct stm32_i2c_init_s *init,
380 unsigned long clock_src, uint32_t *timing)
381 {
382 const struct i2c_spec_s *specs = NULL;
383 uint32_t speed_freq = 0;
384 uint32_t i2cbus = UDIV_ROUND_NEAREST(I2C_NSEC_PER_SEC, speed_freq);
385 uint32_t i2cclk = UDIV_ROUND_NEAREST(I2C_NSEC_PER_SEC, clock_src);
386 uint32_t p_prev = I2C_TIMINGR_PRESC_MAX;
387 uint32_t af_delay_min = 0;
388 uint32_t af_delay_max = 0;
389 uint32_t dnf_delay = 0;
390 uint32_t tsync = 0;
391 uint32_t clk_min = 0;
392 uint32_t clk_max = 0;
393 int clk_error_prev = 0;
394 uint16_t p = 0;
395 uint16_t l = 0;
396 uint16_t a = 0;
397 uint16_t h = 0;
398 unsigned int sdadel_min = 0;
399 unsigned int sdadel_max = 0;
400 unsigned int scldel_min = 0;
401 unsigned int delay = 0;
402 int s = -1;
403 struct i2c_timing_s solutions[I2C_TIMINGR_PRESC_MAX] = { 0 };
404
405 specs = get_specs(init->bus_rate);
406 if (!specs) {
407 DMSG("I2C speed out of bound: %"PRId32"Hz", init->bus_rate);
408 return -1;
409 }
410
411 speed_freq = specs->rate;
412 i2cbus = UDIV_ROUND_NEAREST(I2C_NSEC_PER_SEC, speed_freq);
413 clk_error_prev = INT_MAX;
414
415 if (init->rise_time > specs->rise_max ||
416 init->fall_time > specs->fall_max) {
417 DMSG("I2C rise{%"PRId32">%"PRId32"}/fall{%"PRId32">%"PRId32"}",
418 init->rise_time, specs->rise_max,
419 init->fall_time, specs->fall_max);
420 return -1;
421 }
422
423 if (init->digital_filter_coef > STM32_I2C_DIGITAL_FILTER_MAX) {
424 DMSG("DNF out of bound %"PRId8"/%d",
425 init->digital_filter_coef, STM32_I2C_DIGITAL_FILTER_MAX);
426 return -1;
427 }
428
429 /* Analog and Digital Filters */
430 if (init->analog_filter) {
431 af_delay_min = STM32_I2C_ANALOG_FILTER_DELAY_MIN;
432 af_delay_max = STM32_I2C_ANALOG_FILTER_DELAY_MAX;
433 }
434 dnf_delay = init->digital_filter_coef * i2cclk;
435
436 sdadel_min = specs->hddat_min + init->fall_time;
437 delay = af_delay_min - ((init->digital_filter_coef + 3) * i2cclk);
438 if (SUB_OVERFLOW(sdadel_min, delay, &sdadel_min))
439 sdadel_min = 0;
440
441 sdadel_max = specs->vddat_max - init->rise_time;
442 delay = af_delay_max - ((init->digital_filter_coef + 4) * i2cclk);
443 if (SUB_OVERFLOW(sdadel_max, delay, &sdadel_max))
444 sdadel_max = 0;
445
446 scldel_min = init->rise_time + specs->sudat_min;
447
448 DMSG("I2C SDADEL(min/max): %u/%u, SCLDEL(Min): %u",
449 sdadel_min, sdadel_max, scldel_min);
450
451 /* Compute possible values for PRESC, SCLDEL and SDADEL */
452 for (p = 0; p < I2C_TIMINGR_PRESC_MAX; p++) {
453 for (l = 0; l < I2C_TIMINGR_SCLDEL_MAX; l++) {
454 uint32_t scldel = (l + 1) * (p + 1) * i2cclk;
455
456 if (scldel < scldel_min)
457 continue;
458
459 for (a = 0; a < I2C_TIMINGR_SDADEL_MAX; a++) {
460 uint32_t sdadel = (a * (p + 1) + 1) * i2cclk;
461
462 if ((sdadel >= sdadel_min) &&
463 (sdadel <= sdadel_max) &&
464 (p != p_prev)) {
465 solutions[p].scldel = l;
466 solutions[p].sdadel = a;
467 solutions[p].is_saved = true;
468 p_prev = p;
469 break;
470 }
471 }
472
473 if (p_prev == p)
474 break;
475 }
476 }
477
478 if (p_prev == I2C_TIMINGR_PRESC_MAX) {
479 DMSG("I2C no Prescaler solution");
480 return -1;
481 }
482
483 tsync = af_delay_min + dnf_delay + (2 * i2cclk);
484 clk_max = I2C_NSEC_PER_SEC / RATE_MIN(specs->rate);
485 clk_min = I2C_NSEC_PER_SEC / specs->rate;
486
487 /*
488 * Among prescaler possibilities discovered above figures out SCL Low
489 * and High Period. Provided:
490 * - SCL Low Period has to be higher than Low Period of the SCL Clock
491 * defined by I2C Specification. I2C Clock has to be lower than
492 * (SCL Low Period - Analog/Digital filters) / 4.
493 * - SCL High Period has to be lower than High Period of the SCL Clock
494 * defined by I2C Specification.
495 * - I2C Clock has to be lower than SCL High Period.
496 */
497 for (p = 0; p < I2C_TIMINGR_PRESC_MAX; p++) {
498 uint32_t prescaler = (p + 1) * i2cclk;
499
500 if (!solutions[p].is_saved)
501 continue;
502
503 for (l = 0; l < I2C_TIMINGR_SCLL_MAX; l++) {
504 uint32_t tscl_l = ((l + 1) * prescaler) + tsync;
505
506 if (tscl_l < specs->l_min ||
507 i2cclk >= ((tscl_l - af_delay_min - dnf_delay) / 4))
508 continue;
509
510 for (h = 0; h < I2C_TIMINGR_SCLH_MAX; h++) {
511 uint32_t tscl_h = ((h + 1) * prescaler) + tsync;
512 uint32_t tscl = tscl_l + tscl_h +
513 init->rise_time +
514 init->fall_time;
515
516 if (tscl >= clk_min && tscl <= clk_max &&
517 tscl_h >= specs->h_min && i2cclk < tscl_h) {
518 int clk_error = tscl - i2cbus;
519
520 if (clk_error < 0)
521 clk_error = -clk_error;
522
523 if (clk_error < clk_error_prev) {
524 clk_error_prev = clk_error;
525 solutions[p].scll = l;
526 solutions[p].sclh = h;
527 s = p;
528 }
529 }
530 }
531 }
532 }
533
534 if (s < 0) {
535 DMSG("I2C no solution at all");
536 return -1;
537 }
538
539 /* Finalize timing settings */
540 *timing = I2C_SET_TIMINGR_PRESC(s) |
541 I2C_SET_TIMINGR_SCLDEL(solutions[s].scldel) |
542 I2C_SET_TIMINGR_SDADEL(solutions[s].sdadel) |
543 I2C_SET_TIMINGR_SCLH(solutions[s].sclh) |
544 I2C_SET_TIMINGR_SCLL(solutions[s].scll);
545
546 DMSG("I2C TIMINGR (PRESC/SCLDEL/SDADEL): %i/%"PRIu8"/%"PRIu8,
547 s, solutions[s].scldel, solutions[s].sdadel);
548 DMSG("I2C TIMINGR (SCLH/SCLL): %"PRIu8"/%"PRIu8,
549 solutions[s].sclh, solutions[s].scll);
550 DMSG("I2C TIMINGR: 0x%"PRIx32, *timing);
551
552 return 0;
553 }
554
555 /* i2c_specs[] must be sorted by increasing rate */
i2c_specs_is_consistent(void)556 static bool __maybe_unused i2c_specs_is_consistent(void)
557 {
558 size_t i = 0;
559
560 COMPILE_TIME_ASSERT(ARRAY_SIZE(i2c_specs));
561
562 for (i = 1; i < ARRAY_SIZE(i2c_specs); i++)
563 if (i2c_specs[i - 1].rate >= i2c_specs[i].rate)
564 return false;
565
566 return true;
567 }
568
569 /*
570 * @brief From requested rate, get the closest I2C rate without exceeding it,
571 * within I2C specification values defined in @i2c_specs.
572 * @param rate: The requested rate.
573 * @retval Found rate, else the lowest value supported by platform.
574 */
get_lower_rate(uint32_t rate)575 static uint32_t get_lower_rate(uint32_t rate)
576 {
577 size_t i = 0;
578
579 for (i = ARRAY_SIZE(i2c_specs); i > 0; i--)
580 if (rate > i2c_specs[i - 1].rate)
581 return i2c_specs[i - 1].rate;
582
583 return i2c_specs[0].rate;
584 }
585
586 /*
587 * Setup the I2C device timings
588 *
589 * @hi2c: I2C handle structure
590 * @init: Ref to the initialization configuration structure
591 * @timing: Output TIMINGR register configuration value
592 * @retval 0 if OK, negative value else
593 */
i2c_setup_timing(struct i2c_handle_s * hi2c,struct stm32_i2c_init_s * init,uint32_t * timing)594 static int i2c_setup_timing(struct i2c_handle_s *hi2c,
595 struct stm32_i2c_init_s *init,
596 uint32_t *timing)
597 {
598 int rc = 0;
599 unsigned long clock_src = 0;
600
601 assert(i2c_specs_is_consistent());
602
603 clock_src = clk_get_rate(hi2c->clock);
604 if (!clock_src) {
605 DMSG("Null I2C clock rate");
606 return -1;
607 }
608
609 /*
610 * If the timing has already been computed, and the frequency is the
611 * same as when it was computed, then use the saved timing.
612 */
613 if (clock_src == hi2c->saved_frequency) {
614 *timing = hi2c->saved_timing;
615 return 0;
616 }
617
618 do {
619 rc = i2c_compute_timing(init, clock_src, timing);
620 if (rc) {
621 DMSG("Failed to compute I2C timings");
622 if (init->bus_rate > I2C_STANDARD_RATE) {
623 init->bus_rate = get_lower_rate(init->bus_rate);
624 IMSG("Downgrade I2C speed to %"PRIu32"Hz)",
625 init->bus_rate);
626 } else {
627 break;
628 }
629 }
630 } while (rc);
631
632 if (rc) {
633 DMSG("Impossible to compute I2C timings");
634 return rc;
635 }
636
637 DMSG("I2C Freq(%"PRIu32"Hz), Clk Source(%lu)",
638 init->bus_rate, clock_src);
639 DMSG("I2C Rise(%"PRId32") and Fall(%"PRId32") Time",
640 init->rise_time, init->fall_time);
641 DMSG("I2C Analog Filter(%s), DNF(%"PRIu8")",
642 init->analog_filter ? "On" : "Off", init->digital_filter_coef);
643
644 hi2c->saved_timing = *timing;
645 hi2c->saved_frequency = clock_src;
646
647 return 0;
648 }
649
650 /*
651 * Configure I2C Analog noise filter.
652 * @hi2c: I2C handle structure
653 * @analog_filter_on: True if enabling analog filter, false otherwise
654 * Return 0 on success or a negative value
655 */
i2c_config_analog_filter(struct i2c_handle_s * hi2c,bool analog_filter_on)656 static int i2c_config_analog_filter(struct i2c_handle_s *hi2c,
657 bool analog_filter_on)
658 {
659 vaddr_t base = get_base(hi2c);
660
661 if (hi2c->i2c_state != I2C_STATE_READY)
662 return -1;
663
664 hi2c->i2c_state = I2C_STATE_BUSY;
665
666 /* Disable the selected I2C peripheral */
667 io_clrbits32(base + I2C_CR1, I2C_CR1_PE);
668
669 /* Reset I2Cx ANOFF bit */
670 io_clrbits32(base + I2C_CR1, I2C_CR1_ANFOFF);
671
672 /* Set analog filter bit if filter is disabled */
673 if (!analog_filter_on)
674 io_setbits32(base + I2C_CR1, I2C_CR1_ANFOFF);
675
676 /* Enable the selected I2C peripheral */
677 io_setbits32(base + I2C_CR1, I2C_CR1_PE);
678
679 hi2c->i2c_state = I2C_STATE_READY;
680
681 return 0;
682 }
683
stm32_i2c_get_setup_from_fdt(void * fdt,int node,struct stm32_i2c_init_s * init,struct stm32_pinctrl ** pinctrl,size_t * pinctrl_count)684 TEE_Result stm32_i2c_get_setup_from_fdt(void *fdt, int node,
685 struct stm32_i2c_init_s *init,
686 struct stm32_pinctrl **pinctrl,
687 size_t *pinctrl_count)
688 {
689 TEE_Result res = TEE_ERROR_GENERIC;
690 const fdt32_t *cuint = NULL;
691 struct dt_node_info info = { .status = 0 };
692 int count = 0;
693
694 /* Default STM32 specific configs caller may need to overwrite */
695 memset(init, 0, sizeof(*init));
696
697 _fdt_fill_device_info(fdt, &info, node);
698 assert(info.reg != DT_INFO_INVALID_REG &&
699 info.reg_size != DT_INFO_INVALID_REG_SIZE);
700
701 init->dt_status = info.status;
702 init->pbase = info.reg;
703 init->reg_size = info.reg_size;
704
705 res = clk_dt_get_by_index(fdt, node, 0, &init->clock);
706 if (res)
707 return res;
708
709 cuint = fdt_getprop(fdt, node, "i2c-scl-rising-time-ns", NULL);
710 if (cuint)
711 init->rise_time = fdt32_to_cpu(*cuint);
712 else
713 init->rise_time = STM32_I2C_RISE_TIME_DEFAULT;
714
715 cuint = fdt_getprop(fdt, node, "i2c-scl-falling-time-ns", NULL);
716 if (cuint)
717 init->fall_time = fdt32_to_cpu(*cuint);
718 else
719 init->fall_time = STM32_I2C_FALL_TIME_DEFAULT;
720
721 cuint = fdt_getprop(fdt, node, "clock-frequency", NULL);
722 if (cuint) {
723 init->bus_rate = fdt32_to_cpu(*cuint);
724
725 if (init->bus_rate > I2C_FAST_PLUS_RATE) {
726 DMSG("Invalid bus speed (%"PRIu32" > %i)",
727 init->bus_rate, I2C_FAST_PLUS_RATE);
728 return TEE_ERROR_GENERIC;
729 }
730 } else {
731 init->bus_rate = I2C_STANDARD_RATE;
732 }
733
734 count = stm32_pinctrl_fdt_get_pinctrl(fdt, node, NULL, 0);
735 if (count <= 0) {
736 *pinctrl = NULL;
737 *pinctrl_count = count;
738 DMSG("Failed to get pinctrl: FDT errno %d", count);
739 return TEE_ERROR_GENERIC;
740 }
741
742 if (count > 2) {
743 DMSG("Too many PINCTRLs found: %zd", count);
744 return TEE_ERROR_GENERIC;
745 }
746
747 *pinctrl = calloc(count, sizeof(**pinctrl));
748 if (!*pinctrl)
749 return TEE_ERROR_OUT_OF_MEMORY;
750
751 *pinctrl_count = stm32_pinctrl_fdt_get_pinctrl(fdt, node,
752 *pinctrl, count);
753 assert(*pinctrl_count == (unsigned int)count);
754
755 return TEE_SUCCESS;
756 }
757
stm32_i2c_init(struct i2c_handle_s * hi2c,struct stm32_i2c_init_s * init_data)758 int stm32_i2c_init(struct i2c_handle_s *hi2c,
759 struct stm32_i2c_init_s *init_data)
760 {
761 int rc = 0;
762 uint32_t timing = 0;
763 vaddr_t base = 0;
764 uint32_t val = 0;
765
766 hi2c->dt_status = init_data->dt_status;
767 hi2c->base.pa = init_data->pbase;
768 hi2c->reg_size = init_data->reg_size;
769 hi2c->clock = init_data->clock;
770
771 rc = i2c_setup_timing(hi2c, init_data, &timing);
772 if (rc)
773 return rc;
774
775 clk_enable(hi2c->clock);
776
777 base = get_base(hi2c);
778 hi2c->i2c_state = I2C_STATE_BUSY;
779
780 /* Disable the selected I2C peripheral */
781 io_clrbits32(base + I2C_CR1, I2C_CR1_PE);
782
783 /* Configure I2Cx: Frequency range */
784 io_write32(base + I2C_TIMINGR, timing & TIMINGR_CLEAR_MASK);
785
786 /* Disable Own Address1 before set the Own Address1 configuration */
787 io_write32(base + I2C_OAR1, 0);
788
789 /* Configure I2Cx: Own Address1 and ack own address1 mode */
790 if (init_data->addr_mode_10b_not_7b)
791 io_write32(base + I2C_OAR1,
792 I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE |
793 init_data->own_address1);
794 else
795 io_write32(base + I2C_OAR1,
796 I2C_OAR1_OA1EN | init_data->own_address1);
797
798 /* Configure I2Cx: Addressing Master mode */
799 io_write32(base + I2C_CR2, 0);
800 if (init_data->addr_mode_10b_not_7b)
801 io_setbits32(base + I2C_CR2, I2C_CR2_ADD10);
802
803 /*
804 * Enable the AUTOEND by default, and enable NACK
805 * (should be disabled only during Slave process).
806 */
807 io_setbits32(base + I2C_CR2, I2C_CR2_AUTOEND | I2C_CR2_NACK);
808
809 /* Disable Own Address2 before set the Own Address2 configuration */
810 io_write32(base + I2C_OAR2, 0);
811
812 /* Configure I2Cx: Dual mode and Own Address2 */
813 if (init_data->dual_address_mode)
814 io_write32(base + I2C_OAR2,
815 I2C_OAR2_OA2EN | init_data->own_address2 |
816 (init_data->own_address2_masks << 8));
817
818 /* Configure I2Cx: Generalcall and NoStretch mode */
819 val = 0;
820 if (init_data->general_call_mode)
821 val |= I2C_CR1_GCEN;
822 if (init_data->no_stretch_mode)
823 val |= I2C_CR1_NOSTRETCH;
824 io_write32(base + I2C_CR1, val);
825
826 /* Enable the selected I2C peripheral */
827 io_setbits32(base + I2C_CR1, I2C_CR1_PE);
828
829 hi2c->i2c_err = I2C_ERROR_NONE;
830 hi2c->i2c_state = I2C_STATE_READY;
831
832 rc = i2c_config_analog_filter(hi2c, init_data->analog_filter);
833 if (rc)
834 DMSG("I2C analog filter error %d", rc);
835
836 clk_disable(hi2c->clock);
837
838 return rc;
839 }
840
841 /* I2C transmit (TX) data register flush sequence */
i2c_flush_txdr(struct i2c_handle_s * hi2c)842 static void i2c_flush_txdr(struct i2c_handle_s *hi2c)
843 {
844 vaddr_t base = get_base(hi2c);
845
846 /*
847 * If a pending TXIS flag is set,
848 * write a dummy data in TXDR to clear it.
849 */
850 if (io_read32(base + I2C_ISR) & I2C_ISR_TXIS)
851 io_write32(base + I2C_TXDR, 0);
852
853 /* Flush TX register if not empty */
854 if ((io_read32(base + I2C_ISR) & I2C_ISR_TXE) == 0)
855 io_setbits32(base + I2C_ISR, I2C_ISR_TXE);
856 }
857
858 /*
859 * Wait for a single target I2C_ISR bit to reach an awaited value (0 or 1)
860 *
861 * @hi2c: I2C handle structure
862 * @bit_mask: Bit mask for the target single bit position to consider
863 * @awaited_value: Awaited value of the target bit in I2C_ISR, 0 or 1
864 * @timeout_ref: Expriation timeout reference
865 * Return 0 on success and a non-zero value on timeout
866 */
wait_isr_event(struct i2c_handle_s * hi2c,uint32_t bit_mask,unsigned int awaited_value,uint64_t timeout_ref)867 static int wait_isr_event(struct i2c_handle_s *hi2c, uint32_t bit_mask,
868 unsigned int awaited_value, uint64_t timeout_ref)
869 {
870 vaddr_t isr = get_base(hi2c) + I2C_ISR;
871
872 assert(IS_POWER_OF_TWO(bit_mask) && !(awaited_value & ~1U));
873
874 /* May timeout while TEE thread is suspended */
875 while (!timeout_elapsed(timeout_ref))
876 if (!!(io_read32(isr) & bit_mask) == awaited_value)
877 break;
878
879 if (!!(io_read32(isr) & bit_mask) == awaited_value)
880 return 0;
881
882 notif_i2c_timeout(hi2c);
883 return -1;
884 }
885
886 /* Handle Acknowledge-Failed sequence detection during an I2C Communication */
i2c_ack_failed(struct i2c_handle_s * hi2c,uint64_t timeout_ref)887 static int i2c_ack_failed(struct i2c_handle_s *hi2c, uint64_t timeout_ref)
888 {
889 vaddr_t base = get_base(hi2c);
890
891 if ((io_read32(base + I2C_ISR) & I2C_ISR_NACKF) == 0U)
892 return 0;
893
894 /*
895 * Wait until STOP Flag is reset. Use polling method.
896 * AutoEnd should be initiate after AF.
897 * Timeout may elpased while TEE thread is suspended.
898 */
899 while (!timeout_elapsed(timeout_ref))
900 if (io_read32(base + I2C_ISR) & I2C_ISR_STOPF)
901 break;
902
903 if ((io_read32(base + I2C_ISR) & I2C_ISR_STOPF) == 0) {
904 notif_i2c_timeout(hi2c);
905 return -1;
906 }
907
908 io_write32(base + I2C_ICR, I2C_ISR_NACKF);
909
910 io_write32(base + I2C_ICR, I2C_ISR_STOPF);
911
912 i2c_flush_txdr(hi2c);
913
914 io_clrbits32(base + I2C_CR2, CR2_RESET_MASK);
915
916 hi2c->i2c_err |= I2C_ERROR_ACKF;
917 hi2c->i2c_state = I2C_STATE_READY;
918
919 return -1;
920 }
921
922 /* Wait TXIS bit is 1 in I2C_ISR register */
i2c_wait_txis(struct i2c_handle_s * hi2c,uint64_t timeout_ref)923 static int i2c_wait_txis(struct i2c_handle_s *hi2c, uint64_t timeout_ref)
924 {
925 while (!timeout_elapsed(timeout_ref)) {
926 if (io_read32(get_base(hi2c) + I2C_ISR) & I2C_ISR_TXIS)
927 break;
928 if (i2c_ack_failed(hi2c, timeout_ref))
929 return -1;
930 }
931
932 if (io_read32(get_base(hi2c) + I2C_ISR) & I2C_ISR_TXIS)
933 return 0;
934
935 if (i2c_ack_failed(hi2c, timeout_ref))
936 return -1;
937
938 notif_i2c_timeout(hi2c);
939 return -1;
940 }
941
942 /* Wait STOPF bit is 1 in I2C_ISR register */
i2c_wait_stop(struct i2c_handle_s * hi2c,uint64_t timeout_ref)943 static int i2c_wait_stop(struct i2c_handle_s *hi2c, uint64_t timeout_ref)
944 {
945 while (!timeout_elapsed(timeout_ref)) {
946 if (io_read32(get_base(hi2c) + I2C_ISR) & I2C_ISR_STOPF)
947 break;
948
949 if (i2c_ack_failed(hi2c, timeout_ref))
950 return -1;
951 }
952
953 if (io_read32(get_base(hi2c) + I2C_ISR) & I2C_ISR_STOPF)
954 return 0;
955
956 if (i2c_ack_failed(hi2c, timeout_ref))
957 return -1;
958
959 notif_i2c_timeout(hi2c);
960 return -1;
961 }
962
963 /*
964 * Load I2C_CR2 register for a I2C transfer
965 *
966 * @hi2c: I2C handle structure
967 * @dev_addr: Slave address to be transferred
968 * @size: Number of bytes to be transferred
969 * @i2c_mode: One of I2C_{RELOAD|AUTOEND|SOFTEND}_MODE: Enable Reload mode.
970 * @startstop: One of I2C_NO_STARTSTOP, I2C_GENERATE_STOP,
971 * I2C_GENERATE_START_{READ|WRITE}
972 */
i2c_transfer_config(struct i2c_handle_s * hi2c,uint32_t dev_addr,uint32_t size,uint32_t i2c_mode,uint32_t startstop)973 static void i2c_transfer_config(struct i2c_handle_s *hi2c, uint32_t dev_addr,
974 uint32_t size, uint32_t i2c_mode,
975 uint32_t startstop)
976 {
977 uint32_t clr_value = I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD |
978 I2C_CR2_AUTOEND | I2C_CR2_START | I2C_CR2_STOP |
979 (I2C_CR2_RD_WRN &
980 (startstop >> (31U - I2C_CR2_RD_WRN_OFFSET)));
981 uint32_t set_value = (dev_addr & I2C_CR2_SADD) |
982 ((size << I2C_CR2_NBYTES_OFFSET) &
983 I2C_CR2_NBYTES) |
984 i2c_mode | startstop;
985
986 io_clrsetbits32(get_base(hi2c) + I2C_CR2, clr_value, set_value);
987 }
988
989 /*
990 * Master sends target device address followed by internal memory
991 * address for a memory write request.
992 * Function returns 0 on success or a negative value.
993 */
i2c_request_mem_write(struct i2c_handle_s * hi2c,struct i2c_request * request,uint64_t timeout_ref)994 static int i2c_request_mem_write(struct i2c_handle_s *hi2c,
995 struct i2c_request *request,
996 uint64_t timeout_ref)
997 {
998 vaddr_t base = get_base(hi2c);
999
1000 i2c_transfer_config(hi2c, request->dev_addr, request->mem_addr_size,
1001 I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
1002
1003 if (i2c_wait_txis(hi2c, timeout_ref))
1004 return -1;
1005
1006 if (request->mem_addr_size == I2C_MEMADD_SIZE_8BIT) {
1007 /* Send memory address */
1008 io_write8(base + I2C_TXDR, request->mem_addr & 0x00FFU);
1009 } else {
1010 /* Send MSB of memory address */
1011 io_write8(base + I2C_TXDR, (request->mem_addr & 0xFF00U) >> 8);
1012
1013 if (i2c_wait_txis(hi2c, timeout_ref))
1014 return -1;
1015
1016 /* Send LSB of memory address */
1017 io_write8(base + I2C_TXDR, request->mem_addr & 0x00FFU);
1018 }
1019
1020 if (wait_isr_event(hi2c, I2C_ISR_TCR, 1, timeout_ref))
1021 return -1;
1022
1023 return 0;
1024 }
1025
1026 /*
1027 * Master sends target device address followed by internal memory
1028 * address to prepare a memory read request.
1029 * Function returns 0 on success or a negative value.
1030 */
i2c_request_mem_read(struct i2c_handle_s * hi2c,struct i2c_request * request,uint64_t timeout_ref)1031 static int i2c_request_mem_read(struct i2c_handle_s *hi2c,
1032 struct i2c_request *request,
1033 uint64_t timeout_ref)
1034 {
1035 vaddr_t base = get_base(hi2c);
1036
1037 i2c_transfer_config(hi2c, request->dev_addr, request->mem_addr_size,
1038 I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
1039
1040 if (i2c_wait_txis(hi2c, timeout_ref))
1041 return -1;
1042
1043 if (request->mem_addr_size == I2C_MEMADD_SIZE_8BIT) {
1044 /* Send memory address */
1045 io_write8(base + I2C_TXDR, request->mem_addr & 0x00FFU);
1046 } else {
1047 /* Send MSB of memory address */
1048 io_write8(base + I2C_TXDR, (request->mem_addr & 0xFF00U) >> 8);
1049
1050 if (i2c_wait_txis(hi2c, timeout_ref))
1051 return -1;
1052
1053 /* Send LSB of memory address */
1054 io_write8(base + I2C_TXDR, request->mem_addr & 0x00FFU);
1055 }
1056
1057 if (wait_isr_event(hi2c, I2C_ISR_TC, 1, timeout_ref))
1058 return -1;
1059
1060 return 0;
1061 }
1062
1063 /*
1064 * Write an amount of data in blocking mode
1065 *
1066 * @hi2c: Reference to struct i2c_handle_s
1067 * @request: I2C request parameters
1068 * @p_data: Pointer to data buffer
1069 * @size: Amount of data to be sent
1070 * Return 0 on success or a negative value
1071 */
i2c_write(struct i2c_handle_s * hi2c,struct i2c_request * request,uint8_t * p_data,uint16_t size)1072 static int i2c_write(struct i2c_handle_s *hi2c, struct i2c_request *request,
1073 uint8_t *p_data, uint16_t size)
1074 {
1075 uint64_t timeout_ref = 0;
1076 vaddr_t base = get_base(hi2c);
1077 int rc = -1;
1078 uint8_t *p_buff = p_data;
1079 size_t xfer_size = 0;
1080 size_t xfer_count = size;
1081
1082 if (request->mode != I2C_MODE_MASTER && request->mode != I2C_MODE_MEM)
1083 return -1;
1084
1085 if (hi2c->i2c_state != I2C_STATE_READY)
1086 return -1;
1087
1088 if (!p_data || !size)
1089 return -1;
1090
1091 clk_enable(hi2c->clock);
1092
1093 timeout_ref = timeout_init_us(I2C_TIMEOUT_BUSY_MS * 1000);
1094 if (wait_isr_event(hi2c, I2C_ISR_BUSY, 0, timeout_ref))
1095 goto bail;
1096
1097 hi2c->i2c_state = I2C_STATE_BUSY_TX;
1098 hi2c->i2c_err = I2C_ERROR_NONE;
1099 timeout_ref = timeout_init_us(request->timeout_ms * 1000);
1100
1101 if (request->mode == I2C_MODE_MEM) {
1102 /* In memory mode, send slave address and memory address */
1103 if (i2c_request_mem_write(hi2c, request, timeout_ref))
1104 goto bail;
1105
1106 if (xfer_count > MAX_NBYTE_SIZE) {
1107 xfer_size = MAX_NBYTE_SIZE;
1108 i2c_transfer_config(hi2c, request->dev_addr, xfer_size,
1109 I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
1110 } else {
1111 xfer_size = xfer_count;
1112 i2c_transfer_config(hi2c, request->dev_addr, xfer_size,
1113 I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
1114 }
1115 } else {
1116 /* In master mode, send slave address */
1117 if (xfer_count > MAX_NBYTE_SIZE) {
1118 xfer_size = MAX_NBYTE_SIZE;
1119 i2c_transfer_config(hi2c, request->dev_addr, xfer_size,
1120 I2C_RELOAD_MODE,
1121 I2C_GENERATE_START_WRITE);
1122 } else {
1123 xfer_size = xfer_count;
1124 i2c_transfer_config(hi2c, request->dev_addr, xfer_size,
1125 I2C_AUTOEND_MODE,
1126 I2C_GENERATE_START_WRITE);
1127 }
1128 }
1129
1130 do {
1131 if (i2c_wait_txis(hi2c, timeout_ref))
1132 goto bail;
1133
1134 io_write8(base + I2C_TXDR, *p_buff);
1135 p_buff++;
1136 xfer_count--;
1137 xfer_size--;
1138
1139 if (xfer_count && !xfer_size) {
1140 /* Wait until TCR flag is set */
1141 if (wait_isr_event(hi2c, I2C_ISR_TCR, 1, timeout_ref))
1142 goto bail;
1143
1144 if (xfer_count > MAX_NBYTE_SIZE) {
1145 xfer_size = MAX_NBYTE_SIZE;
1146 i2c_transfer_config(hi2c, request->dev_addr,
1147 xfer_size,
1148 I2C_RELOAD_MODE,
1149 I2C_NO_STARTSTOP);
1150 } else {
1151 xfer_size = xfer_count;
1152 i2c_transfer_config(hi2c, request->dev_addr,
1153 xfer_size,
1154 I2C_AUTOEND_MODE,
1155 I2C_NO_STARTSTOP);
1156 }
1157 }
1158
1159 } while (xfer_count > 0U);
1160
1161 /*
1162 * No need to Check TC flag, with AUTOEND mode the stop
1163 * is automatically generated.
1164 * Wait until STOPF flag is reset.
1165 */
1166 if (i2c_wait_stop(hi2c, timeout_ref))
1167 goto bail;
1168
1169 io_write32(base + I2C_ICR, I2C_ISR_STOPF);
1170
1171 io_clrbits32(base + I2C_CR2, CR2_RESET_MASK);
1172
1173 hi2c->i2c_state = I2C_STATE_READY;
1174
1175 rc = 0;
1176
1177 bail:
1178 clk_disable(hi2c->clock);
1179
1180 return rc;
1181 }
1182
stm32_i2c_mem_write(struct i2c_handle_s * hi2c,uint32_t dev_addr,uint32_t mem_addr,uint32_t mem_addr_size,uint8_t * p_data,size_t size,unsigned int timeout_ms)1183 int stm32_i2c_mem_write(struct i2c_handle_s *hi2c, uint32_t dev_addr,
1184 uint32_t mem_addr, uint32_t mem_addr_size,
1185 uint8_t *p_data, size_t size, unsigned int timeout_ms)
1186 {
1187 struct i2c_request request = {
1188 .dev_addr = dev_addr,
1189 .mode = I2C_MODE_MEM,
1190 .mem_addr = mem_addr,
1191 .mem_addr_size = mem_addr_size,
1192 .timeout_ms = timeout_ms,
1193 };
1194
1195 return i2c_write(hi2c, &request, p_data, size);
1196 }
1197
stm32_i2c_master_transmit(struct i2c_handle_s * hi2c,uint32_t dev_addr,uint8_t * p_data,size_t size,unsigned int timeout_ms)1198 int stm32_i2c_master_transmit(struct i2c_handle_s *hi2c, uint32_t dev_addr,
1199 uint8_t *p_data, size_t size,
1200 unsigned int timeout_ms)
1201 {
1202 struct i2c_request request = {
1203 .dev_addr = dev_addr,
1204 .mode = I2C_MODE_MASTER,
1205 .timeout_ms = timeout_ms,
1206 };
1207
1208 return i2c_write(hi2c, &request, p_data, size);
1209 }
1210
stm32_i2c_read_write_membyte(struct i2c_handle_s * hi2c,uint16_t dev_addr,unsigned int mem_addr,uint8_t * p_data,bool write)1211 int stm32_i2c_read_write_membyte(struct i2c_handle_s *hi2c, uint16_t dev_addr,
1212 unsigned int mem_addr, uint8_t *p_data,
1213 bool write)
1214 {
1215 uint64_t timeout_ref = 0;
1216 uintptr_t base = get_base(hi2c);
1217 int rc = -1;
1218 uint8_t *p_buff = p_data;
1219 uint32_t event_mask = 0;
1220
1221 if (hi2c->i2c_state != I2C_STATE_READY || !p_data)
1222 return -1;
1223
1224 clk_enable(hi2c->clock);
1225
1226 timeout_ref = timeout_init_us(I2C_TIMEOUT_BUSY_US);
1227 if (wait_isr_event(hi2c, I2C_ISR_BUSY, 0, timeout_ref))
1228 goto bail;
1229
1230 hi2c->i2c_state = write ? I2C_STATE_BUSY_TX : I2C_STATE_BUSY_RX;
1231 hi2c->i2c_err = I2C_ERROR_NONE;
1232
1233 i2c_transfer_config(hi2c, dev_addr, I2C_MEMADD_SIZE_8BIT,
1234 write ? I2C_RELOAD_MODE : I2C_SOFTEND_MODE,
1235 I2C_GENERATE_START_WRITE);
1236
1237 timeout_ref = timeout_init_us(I2C_TIMEOUT_BUSY_US);
1238 if (i2c_wait_txis(hi2c, timeout_ref))
1239 goto bail;
1240
1241 io_write8(base + I2C_TXDR, mem_addr);
1242
1243 if (write)
1244 event_mask = I2C_ISR_TCR;
1245 else
1246 event_mask = I2C_ISR_TC;
1247
1248 timeout_ref = timeout_init_us(I2C_TIMEOUT_BUSY_US);
1249 if (wait_isr_event(hi2c, event_mask, 1, timeout_ref))
1250 goto bail;
1251
1252 i2c_transfer_config(hi2c, dev_addr, I2C_MEMADD_SIZE_8BIT,
1253 I2C_AUTOEND_MODE,
1254 write ? I2C_NO_STARTSTOP : I2C_GENERATE_START_READ);
1255
1256 timeout_ref = timeout_init_us(I2C_TIMEOUT_BUSY_US);
1257 if (write) {
1258 if (i2c_wait_txis(hi2c, timeout_ref))
1259 goto bail;
1260
1261 io_write8(base + I2C_TXDR, *p_buff);
1262 } else {
1263 if (wait_isr_event(hi2c, I2C_ISR_RXNE, 1, timeout_ref))
1264 goto bail;
1265
1266 *p_buff = io_read8(base + I2C_RXDR);
1267 }
1268
1269 timeout_ref = timeout_init_us(I2C_TIMEOUT_BUSY_US);
1270 if (i2c_wait_stop(hi2c, timeout_ref))
1271 goto bail;
1272
1273 io_write32(base + I2C_ICR, I2C_ISR_STOPF);
1274 io_clrbits32(base + I2C_CR2, CR2_RESET_MASK);
1275
1276 hi2c->i2c_state = I2C_STATE_READY;
1277
1278 rc = 0;
1279
1280 bail:
1281 clk_disable(hi2c->clock);
1282
1283 return rc;
1284 }
1285
1286 /*
1287 * Read an amount of data in blocking mode
1288 *
1289 * @hi2c: Reference to struct i2c_handle_s
1290 * @request: I2C request parameters
1291 * @p_data: Pointer to data buffer
1292 * @size: Amount of data to be sent
1293 * Return 0 on success or a negative value
1294 */
i2c_read(struct i2c_handle_s * hi2c,struct i2c_request * request,uint8_t * p_data,uint32_t size)1295 static int i2c_read(struct i2c_handle_s *hi2c, struct i2c_request *request,
1296 uint8_t *p_data, uint32_t size)
1297 {
1298 vaddr_t base = get_base(hi2c);
1299 uint64_t timeout_ref = 0;
1300 int rc = -1;
1301 uint8_t *p_buff = p_data;
1302 size_t xfer_count = size;
1303 size_t xfer_size = 0;
1304
1305 if (request->mode != I2C_MODE_MASTER && request->mode != I2C_MODE_MEM)
1306 return -1;
1307
1308 if (hi2c->i2c_state != I2C_STATE_READY)
1309 return -1;
1310
1311 if (!p_data || !size)
1312 return -1;
1313
1314 clk_enable(hi2c->clock);
1315
1316 timeout_ref = timeout_init_us(I2C_TIMEOUT_BUSY_MS * 1000);
1317 if (wait_isr_event(hi2c, I2C_ISR_BUSY, 0, timeout_ref))
1318 goto bail;
1319
1320 hi2c->i2c_state = I2C_STATE_BUSY_RX;
1321 hi2c->i2c_err = I2C_ERROR_NONE;
1322 timeout_ref = timeout_init_us(request->timeout_ms * 1000);
1323
1324 if (request->mode == I2C_MODE_MEM) {
1325 /* Send memory address */
1326 if (i2c_request_mem_read(hi2c, request, timeout_ref))
1327 goto bail;
1328 }
1329
1330 /*
1331 * Send slave address.
1332 * Set NBYTES to write and reload if xfer_count > MAX_NBYTE_SIZE
1333 * and generate RESTART.
1334 */
1335 if (xfer_count > MAX_NBYTE_SIZE) {
1336 xfer_size = MAX_NBYTE_SIZE;
1337 i2c_transfer_config(hi2c, request->dev_addr, xfer_size,
1338 I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
1339 } else {
1340 xfer_size = xfer_count;
1341 i2c_transfer_config(hi2c, request->dev_addr, xfer_size,
1342 I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
1343 }
1344
1345 do {
1346 if (wait_isr_event(hi2c, I2C_ISR_RXNE, 1, timeout_ref))
1347 goto bail;
1348
1349 *p_buff = io_read8(base + I2C_RXDR);
1350 p_buff++;
1351 xfer_size--;
1352 xfer_count--;
1353
1354 if (xfer_count && !xfer_size) {
1355 if (wait_isr_event(hi2c, I2C_ISR_TCR, 1, timeout_ref))
1356 goto bail;
1357
1358 if (xfer_count > MAX_NBYTE_SIZE) {
1359 xfer_size = MAX_NBYTE_SIZE;
1360 i2c_transfer_config(hi2c, request->dev_addr,
1361 xfer_size,
1362 I2C_RELOAD_MODE,
1363 I2C_NO_STARTSTOP);
1364 } else {
1365 xfer_size = xfer_count;
1366 i2c_transfer_config(hi2c, request->dev_addr,
1367 xfer_size,
1368 I2C_AUTOEND_MODE,
1369 I2C_NO_STARTSTOP);
1370 }
1371 }
1372 } while (xfer_count > 0U);
1373
1374 /*
1375 * No need to Check TC flag, with AUTOEND mode the stop
1376 * is automatically generated.
1377 * Wait until STOPF flag is reset.
1378 */
1379 if (i2c_wait_stop(hi2c, timeout_ref))
1380 goto bail;
1381
1382 io_write32(base + I2C_ICR, I2C_ISR_STOPF);
1383
1384 io_clrbits32(base + I2C_CR2, CR2_RESET_MASK);
1385
1386 hi2c->i2c_state = I2C_STATE_READY;
1387
1388 rc = 0;
1389
1390 bail:
1391 clk_disable(hi2c->clock);
1392
1393 return rc;
1394 }
1395
stm32_i2c_mem_read(struct i2c_handle_s * hi2c,uint32_t dev_addr,uint32_t mem_addr,uint32_t mem_addr_size,uint8_t * p_data,size_t size,unsigned int timeout_ms)1396 int stm32_i2c_mem_read(struct i2c_handle_s *hi2c, uint32_t dev_addr,
1397 uint32_t mem_addr, uint32_t mem_addr_size,
1398 uint8_t *p_data, size_t size, unsigned int timeout_ms)
1399 {
1400 struct i2c_request request = {
1401 .dev_addr = dev_addr,
1402 .mode = I2C_MODE_MEM,
1403 .mem_addr = mem_addr,
1404 .mem_addr_size = mem_addr_size,
1405 .timeout_ms = timeout_ms,
1406 };
1407
1408 return i2c_read(hi2c, &request, p_data, size);
1409 }
1410
stm32_i2c_master_receive(struct i2c_handle_s * hi2c,uint32_t dev_addr,uint8_t * p_data,size_t size,unsigned int timeout_ms)1411 int stm32_i2c_master_receive(struct i2c_handle_s *hi2c, uint32_t dev_addr,
1412 uint8_t *p_data, size_t size,
1413 unsigned int timeout_ms)
1414 {
1415 struct i2c_request request = {
1416 .dev_addr = dev_addr,
1417 .mode = I2C_MODE_MASTER,
1418 .timeout_ms = timeout_ms,
1419 };
1420
1421 return i2c_read(hi2c, &request, p_data, size);
1422 }
1423
stm32_i2c_is_device_ready(struct i2c_handle_s * hi2c,uint32_t dev_addr,unsigned int trials,unsigned int timeout_ms)1424 bool stm32_i2c_is_device_ready(struct i2c_handle_s *hi2c, uint32_t dev_addr,
1425 unsigned int trials, unsigned int timeout_ms)
1426 {
1427 vaddr_t base = get_base(hi2c);
1428 unsigned int i2c_trials = 0U;
1429 bool rc = false;
1430
1431 if (hi2c->i2c_state != I2C_STATE_READY)
1432 return rc;
1433
1434 clk_enable(hi2c->clock);
1435
1436 if (io_read32(base + I2C_ISR) & I2C_ISR_BUSY)
1437 goto bail;
1438
1439 hi2c->i2c_state = I2C_STATE_BUSY;
1440 hi2c->i2c_err = I2C_ERROR_NONE;
1441
1442 do {
1443 uint64_t timeout_ref = 0;
1444 vaddr_t isr = base + I2C_ISR;
1445
1446 /* Generate Start */
1447 if ((io_read32(base + I2C_OAR1) & I2C_OAR1_OA1MODE) == 0)
1448 io_write32(base + I2C_CR2,
1449 ((dev_addr & I2C_CR2_SADD) |
1450 I2C_CR2_START | I2C_CR2_AUTOEND) &
1451 ~I2C_CR2_RD_WRN);
1452 else
1453 io_write32(base + I2C_CR2,
1454 ((dev_addr & I2C_CR2_SADD) |
1455 I2C_CR2_START | I2C_CR2_ADD10) &
1456 ~I2C_CR2_RD_WRN);
1457
1458 /*
1459 * No need to Check TC flag, with AUTOEND mode the stop
1460 * is automatically generated.
1461 * Wait until STOPF flag is set or a NACK flag is set.
1462 */
1463 timeout_ref = timeout_init_us(timeout_ms * 1000);
1464 while (!timeout_elapsed(timeout_ref))
1465 if (io_read32(isr) & (I2C_ISR_STOPF | I2C_ISR_NACKF))
1466 break;
1467
1468 if ((io_read32(isr) & (I2C_ISR_STOPF | I2C_ISR_NACKF)) == 0) {
1469 notif_i2c_timeout(hi2c);
1470 goto bail;
1471 }
1472
1473 if ((io_read32(base + I2C_ISR) & I2C_ISR_NACKF) == 0U) {
1474 if (wait_isr_event(hi2c, I2C_ISR_STOPF, 1, timeout_ref))
1475 goto bail;
1476
1477 io_write32(base + I2C_ICR, I2C_ISR_STOPF);
1478
1479 hi2c->i2c_state = I2C_STATE_READY;
1480
1481 rc = true;
1482 goto bail;
1483 }
1484
1485 if (wait_isr_event(hi2c, I2C_ISR_STOPF, 1, timeout_ref))
1486 goto bail;
1487
1488 io_write32(base + I2C_ICR, I2C_ISR_NACKF);
1489 io_write32(base + I2C_ICR, I2C_ISR_STOPF);
1490
1491 if (i2c_trials == trials) {
1492 io_setbits32(base + I2C_CR2, I2C_CR2_STOP);
1493
1494 if (wait_isr_event(hi2c, I2C_ISR_STOPF, 1, timeout_ref))
1495 goto bail;
1496
1497 io_write32(base + I2C_ICR, I2C_ISR_STOPF);
1498 }
1499
1500 i2c_trials++;
1501 } while (i2c_trials < trials);
1502
1503 notif_i2c_timeout(hi2c);
1504
1505 bail:
1506 clk_disable(hi2c->clock);
1507
1508 return rc;
1509 }
1510
stm32_i2c_resume(struct i2c_handle_s * hi2c)1511 void stm32_i2c_resume(struct i2c_handle_s *hi2c)
1512 {
1513 if (hi2c->i2c_state == I2C_STATE_READY)
1514 return;
1515
1516 if ((hi2c->i2c_state != I2C_STATE_RESET) &&
1517 (hi2c->i2c_state != I2C_STATE_SUSPENDED))
1518 panic();
1519
1520 stm32_pinctrl_load_active_cfg(hi2c->pinctrl, hi2c->pinctrl_count);
1521
1522 if (hi2c->i2c_state == I2C_STATE_RESET) {
1523 /* There is no valid I2C configuration to be loaded yet */
1524 return;
1525 }
1526
1527 restore_cfg(hi2c, &hi2c->sec_cfg);
1528
1529 hi2c->i2c_state = I2C_STATE_READY;
1530 }
1531
stm32_i2c_suspend(struct i2c_handle_s * hi2c)1532 void stm32_i2c_suspend(struct i2c_handle_s *hi2c)
1533 {
1534 if (hi2c->i2c_state == I2C_STATE_SUSPENDED)
1535 return;
1536
1537 if (hi2c->i2c_state != I2C_STATE_READY)
1538 panic();
1539
1540 save_cfg(hi2c, &hi2c->sec_cfg);
1541 stm32_pinctrl_load_standby_cfg(hi2c->pinctrl, hi2c->pinctrl_count);
1542
1543 hi2c->i2c_state = I2C_STATE_SUSPENDED;
1544 }
1545