1 /*
2 * Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <string.h>
9
10 #include <arch.h>
11 #include <arch_helpers.h>
12 #include <common/debug.h>
13 #include <lib/bakery_lock.h>
14 #include <lib/mmio.h>
15 #include <lib/xlat_tables/xlat_tables_v2.h>
16 #include <plat/common/platform.h>
17
18 #include "iic_dvfs.h"
19 #include "micro_delay.h"
20 #include "pwrc.h"
21 #include "rcar_def.h"
22 #include "rcar_private.h"
23 #include "cpg_registers.h"
24
25 /*
26 * Someday there will be a generic power controller api. At the moment each
27 * platform has its own pwrc so just exporting functions should be acceptable.
28 */
29 RCAR_INSTANTIATE_LOCK
30
31 #define WUP_IRQ_SHIFT (0U)
32 #define WUP_FIQ_SHIFT (8U)
33 #define WUP_CSD_SHIFT (16U)
34 #define BIT_SOFTRESET (1U << 15)
35 #define BIT_CA53_SCU (1U << 21)
36 #define BIT_CA57_SCU (1U << 12)
37 #define REQ_RESUME (1U << 1)
38 #define REQ_OFF (1U << 0)
39 #define STATUS_PWRUP (1U << 4)
40 #define STATUS_PWRDOWN (1U << 0)
41 #define STATE_CA57_CPU (27U)
42 #define STATE_CA53_CPU (22U)
43 #define MODE_L2_DOWN (0x00000002U)
44 #define CPU_PWR_OFF (0x00000003U)
45 #define RCAR_PSTR_MASK (0x00000003U)
46 #define ST_ALL_STANDBY (0x00003333U)
47 #define SYSCEXTMASK_EXTMSK0 (0x00000001U)
48 /* Suspend to ram */
49 #define DBSC4_REG_BASE (0xE6790000U)
50 #define DBSC4_REG_DBSYSCNT0 (DBSC4_REG_BASE + 0x0100U)
51 #define DBSC4_REG_DBACEN (DBSC4_REG_BASE + 0x0200U)
52 #define DBSC4_REG_DBCMD (DBSC4_REG_BASE + 0x0208U)
53 #define DBSC4_REG_DBRFEN (DBSC4_REG_BASE + 0x0204U)
54 #define DBSC4_REG_DBWAIT (DBSC4_REG_BASE + 0x0210U)
55 #define DBSC4_REG_DBCALCNF (DBSC4_REG_BASE + 0x0424U)
56 #define DBSC4_REG_DBDFIPMSTRCNF (DBSC4_REG_BASE + 0x0520U)
57 #define DBSC4_REG_DBPDLK0 (DBSC4_REG_BASE + 0x0620U)
58 #define DBSC4_REG_DBPDRGA0 (DBSC4_REG_BASE + 0x0624U)
59 #define DBSC4_REG_DBPDRGD0 (DBSC4_REG_BASE + 0x0628U)
60 #define DBSC4_REG_DBCAM0CTRL0 (DBSC4_REG_BASE + 0x0940U)
61 #define DBSC4_REG_DBCAM0STAT0 (DBSC4_REG_BASE + 0x0980U)
62 #define DBSC4_REG_DBCAM1STAT0 (DBSC4_REG_BASE + 0x0990U)
63 #define DBSC4_REG_DBCAM2STAT0 (DBSC4_REG_BASE + 0x09A0U)
64 #define DBSC4_REG_DBCAM3STAT0 (DBSC4_REG_BASE + 0x09B0U)
65 #define DBSC4_BIT_DBACEN_ACCEN ((uint32_t)(1U << 0))
66 #define DBSC4_BIT_DBRFEN_ARFEN ((uint32_t)(1U << 0))
67 #define DBSC4_BIT_DBCAMxSTAT0 (0x00000001U)
68 #define DBSC4_BIT_DBDFIPMSTRCNF_PMSTREN (0x00000001U)
69 #define DBSC4_SET_DBCMD_OPC_PRE (0x04000000U)
70 #define DBSC4_SET_DBCMD_OPC_SR (0x0A000000U)
71 #define DBSC4_SET_DBCMD_OPC_PD (0x08000000U)
72 #define DBSC4_SET_DBCMD_OPC_MRW (0x0E000000U)
73 #define DBSC4_SET_DBCMD_CH_ALL (0x00800000U)
74 #define DBSC4_SET_DBCMD_RANK_ALL (0x00040000U)
75 #define DBSC4_SET_DBCMD_ARG_ALL (0x00000010U)
76 #define DBSC4_SET_DBCMD_ARG_ENTER (0x00000000U)
77 #define DBSC4_SET_DBCMD_ARG_MRW_ODTC (0x00000B00U)
78 #define DBSC4_SET_DBSYSCNT0_WRITE_ENABLE (0x00001234U)
79 #define DBSC4_SET_DBSYSCNT0_WRITE_DISABLE (0x00000000U)
80 #define DBSC4_SET_DBPDLK0_PHY_ACCESS (0x0000A55AU)
81 #define DBSC4_SET_DBPDRGA0_ACIOCR0 (0x0000001AU)
82 #define DBSC4_SET_DBPDRGD0_ACIOCR0 (0x33C03C11U)
83 #define DBSC4_SET_DBPDRGA0_DXCCR (0x00000020U)
84 #define DBSC4_SET_DBPDRGD0_DXCCR (0x00181006U)
85 #define DBSC4_SET_DBPDRGA0_PGCR1 (0x00000003U)
86 #define DBSC4_SET_DBPDRGD0_PGCR1 (0x0380C600U)
87 #define DBSC4_SET_DBPDRGA0_ACIOCR1 (0x0000001BU)
88 #define DBSC4_SET_DBPDRGD0_ACIOCR1 (0xAAAAAAAAU)
89 #define DBSC4_SET_DBPDRGA0_ACIOCR3 (0x0000001DU)
90 #define DBSC4_SET_DBPDRGD0_ACIOCR3 (0xAAAAAAAAU)
91 #define DBSC4_SET_DBPDRGA0_ACIOCR5 (0x0000001FU)
92 #define DBSC4_SET_DBPDRGD0_ACIOCR5 (0x000000AAU)
93 #define DBSC4_SET_DBPDRGA0_DX0GCR2 (0x000000A2U)
94 #define DBSC4_SET_DBPDRGD0_DX0GCR2 (0xAAAA0000U)
95 #define DBSC4_SET_DBPDRGA0_DX1GCR2 (0x000000C2U)
96 #define DBSC4_SET_DBPDRGD0_DX1GCR2 (0xAAAA0000U)
97 #define DBSC4_SET_DBPDRGA0_DX2GCR2 (0x000000E2U)
98 #define DBSC4_SET_DBPDRGD0_DX2GCR2 (0xAAAA0000U)
99 #define DBSC4_SET_DBPDRGA0_DX3GCR2 (0x00000102U)
100 #define DBSC4_SET_DBPDRGD0_DX3GCR2 (0xAAAA0000U)
101 #define DBSC4_SET_DBPDRGA0_ZQCR (0x00000090U)
102 #define DBSC4_SET_DBPDRGD0_ZQCR_MD19_0 (0x04058904U)
103 #define DBSC4_SET_DBPDRGD0_ZQCR_MD19_1 (0x04058A04U)
104 #define DBSC4_SET_DBPDRGA0_DX0GCR0 (0x000000A0U)
105 #define DBSC4_SET_DBPDRGD0_DX0GCR0 (0x7C0002E5U)
106 #define DBSC4_SET_DBPDRGA0_DX1GCR0 (0x000000C0U)
107 #define DBSC4_SET_DBPDRGD0_DX1GCR0 (0x7C0002E5U)
108 #define DBSC4_SET_DBPDRGA0_DX2GCR0 (0x000000E0U)
109 #define DBSC4_SET_DBPDRGD0_DX2GCR0 (0x7C0002E5U)
110 #define DBSC4_SET_DBPDRGA0_DX3GCR0 (0x00000100U)
111 #define DBSC4_SET_DBPDRGD0_DX3GCR0 (0x7C0002E5U)
112 #define DBSC4_SET_DBPDRGA0_DX0GCR1 (0x000000A1U)
113 #define DBSC4_SET_DBPDRGD0_DX0GCR1 (0x55550000U)
114 #define DBSC4_SET_DBPDRGA0_DX1GCR1 (0x000000C1U)
115 #define DBSC4_SET_DBPDRGD0_DX1GCR1 (0x55550000U)
116 #define DBSC4_SET_DBPDRGA0_DX2GCR1 (0x000000E1U)
117 #define DBSC4_SET_DBPDRGD0_DX2GCR1 (0x55550000U)
118 #define DBSC4_SET_DBPDRGA0_DX3GCR1 (0x00000101U)
119 #define DBSC4_SET_DBPDRGD0_DX3GCR1 (0x55550000U)
120 #define DBSC4_SET_DBPDRGA0_DX0GCR3 (0x000000A3U)
121 #define DBSC4_SET_DBPDRGD0_DX0GCR3 (0x00008484U)
122 #define DBSC4_SET_DBPDRGA0_DX1GCR3 (0x000000C3U)
123 #define DBSC4_SET_DBPDRGD0_DX1GCR3 (0x00008484U)
124 #define DBSC4_SET_DBPDRGA0_DX2GCR3 (0x000000E3U)
125 #define DBSC4_SET_DBPDRGD0_DX2GCR3 (0x00008484U)
126 #define DBSC4_SET_DBPDRGA0_DX3GCR3 (0x00000103U)
127 #define DBSC4_SET_DBPDRGD0_DX3GCR3 (0x00008484U)
128 #define RST_BASE (0xE6160000U)
129 #define RST_MODEMR (RST_BASE + 0x0060U)
130 #define RST_MODEMR_BIT0 (0x00000001U)
131
132 #define RCAR_CNTCR_OFF (0x00U)
133 #define RCAR_CNTCVL_OFF (0x08U)
134 #define RCAR_CNTCVU_OFF (0x0CU)
135 #define RCAR_CNTFID_OFF (0x20U)
136
137 #define RCAR_CNTCR_EN ((uint32_t)1U << 0U)
138 #define RCAR_CNTCR_FCREQ(x) ((uint32_t)(x) << 8U)
139
140 #if PMIC_ROHM_BD9571
141 #define BIT_BKUP_CTRL_OUT ((uint8_t)(1U << 4))
142 #define PMIC_BKUP_MODE_CNT (0x20U)
143 #define PMIC_QLLM_CNT (0x27U)
144 #define PMIC_RETRY_MAX (100U)
145 #endif /* PMIC_ROHM_BD9571 */
146 #define SCTLR_EL3_M_BIT ((uint32_t)1U << 0)
147 #define RCAR_CA53CPU_NUM_MAX (4U)
148 #define RCAR_CA57CPU_NUM_MAX (4U)
149 #define IS_A53A57(c) ((c) == RCAR_CLUSTER_A53A57)
150 #define IS_CA57(c) ((c) == RCAR_CLUSTER_CA57)
151 #define IS_CA53(c) ((c) == RCAR_CLUSTER_CA53)
152
153 #ifndef __ASSEMBLER__
154 IMPORT_SYM(unsigned long, __system_ram_start__, SYSTEM_RAM_START);
155 IMPORT_SYM(unsigned long, __system_ram_end__, SYSTEM_RAM_END);
156 IMPORT_SYM(unsigned long, __SRAM_COPY_START__, SRAM_COPY_START);
157 #endif
158
rcar_pwrc_status(uint64_t mpidr)159 uint32_t rcar_pwrc_status(uint64_t mpidr)
160 {
161 uint32_t ret = 0;
162 uint64_t cm, cpu;
163 uint32_t reg;
164 uint32_t c;
165
166 rcar_lock_get();
167
168 c = rcar_pwrc_get_cluster();
169 cm = mpidr & MPIDR_CLUSTER_MASK;
170
171 if (!IS_A53A57(c) && cm != 0) {
172 ret = RCAR_INVALID;
173 goto done;
174 }
175
176 reg = mmio_read_32(RCAR_PRR);
177 cpu = mpidr & MPIDR_CPU_MASK;
178
179 if (IS_CA53(c))
180 if (reg & (1 << (STATE_CA53_CPU + cpu)))
181 ret = RCAR_INVALID;
182 if (IS_CA57(c))
183 if (reg & (1 << (STATE_CA57_CPU + cpu)))
184 ret = RCAR_INVALID;
185 done:
186 rcar_lock_release();
187
188 return ret;
189 }
190
scu_power_up(uint64_t mpidr)191 static void scu_power_up(uint64_t mpidr)
192 {
193 uintptr_t reg_pwrsr, reg_cpumcr, reg_pwron, reg_pwrer;
194 uint32_t c, sysc_reg_bit;
195 uint32_t lsi_product;
196 uint32_t lsi_cut;
197
198 c = rcar_pwrc_get_mpidr_cluster(mpidr);
199 reg_cpumcr = IS_CA57(c) ? RCAR_CA57CPUCMCR : RCAR_CA53CPUCMCR;
200 sysc_reg_bit = IS_CA57(c) ? BIT_CA57_SCU : BIT_CA53_SCU;
201 reg_pwron = IS_CA57(c) ? RCAR_PWRONCR5 : RCAR_PWRONCR3;
202 reg_pwrer = IS_CA57(c) ? RCAR_PWRER5 : RCAR_PWRER3;
203 reg_pwrsr = IS_CA57(c) ? RCAR_PWRSR5 : RCAR_PWRSR3;
204
205 if ((mmio_read_32(reg_pwrsr) & STATUS_PWRDOWN) == 0)
206 return;
207
208 if (mmio_read_32(reg_cpumcr) != 0)
209 mmio_write_32(reg_cpumcr, 0);
210
211 lsi_product = mmio_read_32((uintptr_t)RCAR_PRR);
212 lsi_cut = lsi_product & PRR_CUT_MASK;
213 lsi_product &= PRR_PRODUCT_MASK;
214
215 if ((lsi_product == PRR_PRODUCT_M3 && lsi_cut >= PRR_PRODUCT_30) ||
216 lsi_product == PRR_PRODUCT_H3 ||
217 lsi_product == PRR_PRODUCT_M3N ||
218 lsi_product == PRR_PRODUCT_E3) {
219 mmio_setbits_32(RCAR_SYSCEXTMASK, SYSCEXTMASK_EXTMSK0);
220 }
221
222 mmio_setbits_32(RCAR_SYSCIER, sysc_reg_bit);
223 mmio_setbits_32(RCAR_SYSCIMR, sysc_reg_bit);
224
225 do {
226 while ((mmio_read_32(RCAR_SYSCSR) & REQ_RESUME) == 0)
227 ;
228 mmio_write_32(reg_pwron, 1);
229 } while (mmio_read_32(reg_pwrer) & 1);
230
231 while ((mmio_read_32(RCAR_SYSCISR) & sysc_reg_bit) == 0)
232 ;
233 mmio_write_32(RCAR_SYSCISCR, sysc_reg_bit);
234
235 if ((lsi_product == PRR_PRODUCT_M3 && lsi_cut >= PRR_PRODUCT_30) ||
236 lsi_product == PRR_PRODUCT_H3 ||
237 lsi_product == PRR_PRODUCT_M3N ||
238 lsi_product == PRR_PRODUCT_E3) {
239 mmio_clrbits_32(RCAR_SYSCEXTMASK, SYSCEXTMASK_EXTMSK0);
240 }
241
242 while ((mmio_read_32(reg_pwrsr) & STATUS_PWRUP) == 0)
243 ;
244 }
245
rcar_pwrc_cpuon(uint64_t mpidr)246 void rcar_pwrc_cpuon(uint64_t mpidr)
247 {
248 uint32_t res_data, on_data;
249 uintptr_t res_reg, on_reg;
250 uint32_t limit, c;
251 uint64_t cpu;
252
253 rcar_lock_get();
254
255 c = rcar_pwrc_get_mpidr_cluster(mpidr);
256 res_reg = IS_CA53(c) ? RCAR_CA53RESCNT : RCAR_CA57RESCNT;
257 on_reg = IS_CA53(c) ? RCAR_CA53WUPCR : RCAR_CA57WUPCR;
258 limit = IS_CA53(c) ? 0x5A5A0000 : 0xA5A50000;
259
260 res_data = mmio_read_32(res_reg) | limit;
261 scu_power_up(mpidr);
262 cpu = mpidr & MPIDR_CPU_MASK;
263 on_data = 1 << cpu;
264 mmio_write_32(CPG_CPGWPR, ~on_data);
265 mmio_write_32(on_reg, on_data);
266 mmio_write_32(res_reg, res_data & (~(1 << (3 - cpu))));
267
268 rcar_lock_release();
269 }
270
rcar_pwrc_cpuoff(uint64_t mpidr)271 void rcar_pwrc_cpuoff(uint64_t mpidr)
272 {
273 uint32_t c;
274 uintptr_t reg;
275 uint64_t cpu;
276
277 rcar_lock_get();
278
279 cpu = mpidr & MPIDR_CPU_MASK;
280 c = rcar_pwrc_get_mpidr_cluster(mpidr);
281 reg = IS_CA53(c) ? RCAR_CA53CPU0CR : RCAR_CA57CPU0CR;
282
283 if (read_mpidr_el1() != mpidr)
284 panic();
285
286 mmio_write_32(CPG_CPGWPR, ~CPU_PWR_OFF);
287 mmio_write_32(reg + cpu * 0x0010, CPU_PWR_OFF);
288
289 rcar_lock_release();
290 }
291
rcar_pwrc_enable_interrupt_wakeup(uint64_t mpidr)292 void rcar_pwrc_enable_interrupt_wakeup(uint64_t mpidr)
293 {
294 uint32_t c, shift_irq, shift_fiq;
295 uintptr_t reg;
296 uint64_t cpu;
297
298 rcar_lock_get();
299
300 cpu = mpidr & MPIDR_CPU_MASK;
301 c = rcar_pwrc_get_mpidr_cluster(mpidr);
302 reg = IS_CA53(c) ? RCAR_WUPMSKCA53 : RCAR_WUPMSKCA57;
303
304 shift_irq = WUP_IRQ_SHIFT + cpu;
305 shift_fiq = WUP_FIQ_SHIFT + cpu;
306
307 mmio_write_32(reg, ~((uint32_t) 1 << shift_irq) &
308 ~((uint32_t) 1 << shift_fiq));
309 rcar_lock_release();
310 }
311
rcar_pwrc_disable_interrupt_wakeup(uint64_t mpidr)312 void rcar_pwrc_disable_interrupt_wakeup(uint64_t mpidr)
313 {
314 uint32_t c, shift_irq, shift_fiq;
315 uintptr_t reg;
316 uint64_t cpu;
317
318 rcar_lock_get();
319
320 cpu = mpidr & MPIDR_CPU_MASK;
321 c = rcar_pwrc_get_mpidr_cluster(mpidr);
322 reg = IS_CA53(c) ? RCAR_WUPMSKCA53 : RCAR_WUPMSKCA57;
323
324 shift_irq = WUP_IRQ_SHIFT + cpu;
325 shift_fiq = WUP_FIQ_SHIFT + cpu;
326
327 mmio_write_32(reg, ((uint32_t) 1 << shift_irq) |
328 ((uint32_t) 1 << shift_fiq));
329 rcar_lock_release();
330 }
331
rcar_pwrc_clusteroff(uint64_t mpidr)332 void rcar_pwrc_clusteroff(uint64_t mpidr)
333 {
334 uint32_t c, product, cut, reg;
335 uintptr_t dst;
336
337 rcar_lock_get();
338
339 reg = mmio_read_32(RCAR_PRR);
340 product = reg & PRR_PRODUCT_MASK;
341 cut = reg & PRR_CUT_MASK;
342
343 c = rcar_pwrc_get_mpidr_cluster(mpidr);
344 dst = IS_CA53(c) ? RCAR_CA53CPUCMCR : RCAR_CA57CPUCMCR;
345
346 if (product == PRR_PRODUCT_M3 && cut < PRR_PRODUCT_30) {
347 goto done;
348 }
349
350 if (product == PRR_PRODUCT_H3 && cut <= PRR_PRODUCT_20) {
351 goto done;
352 }
353
354 /* all of the CPUs in the cluster is in the CoreStandby mode */
355 mmio_write_32(dst, MODE_L2_DOWN);
356 done:
357 rcar_lock_release();
358 }
359
360 static uint64_t rcar_pwrc_saved_cntpct_el0;
361 static uint32_t rcar_pwrc_saved_cntfid;
362
363 #if RCAR_SYSTEM_SUSPEND
rcar_pwrc_save_timer_state(void)364 static void rcar_pwrc_save_timer_state(void)
365 {
366 rcar_pwrc_saved_cntpct_el0 = read_cntpct_el0();
367
368 rcar_pwrc_saved_cntfid =
369 mmio_read_32((uintptr_t)(RCAR_CNTC_BASE + RCAR_CNTFID_OFF));
370 }
371 #endif /* RCAR_SYSTEM_SUSPEND */
372
rcar_pwrc_restore_timer_state(void)373 void rcar_pwrc_restore_timer_state(void)
374 {
375 /* Stop timer before restoring counter value */
376 mmio_write_32((uintptr_t)(RCAR_CNTC_BASE + RCAR_CNTCR_OFF), 0U);
377
378 mmio_write_32((uintptr_t)(RCAR_CNTC_BASE + RCAR_CNTCVL_OFF),
379 (uint32_t)(rcar_pwrc_saved_cntpct_el0 & 0xFFFFFFFFU));
380 mmio_write_32((uintptr_t)(RCAR_CNTC_BASE + RCAR_CNTCVU_OFF),
381 (uint32_t)(rcar_pwrc_saved_cntpct_el0 >> 32U));
382
383 mmio_write_32((uintptr_t)(RCAR_CNTC_BASE + RCAR_CNTFID_OFF),
384 rcar_pwrc_saved_cntfid);
385
386 /* Start generic timer back */
387 write_cntfrq_el0((u_register_t)plat_get_syscnt_freq2());
388
389 mmio_write_32((uintptr_t)(RCAR_CNTC_BASE + RCAR_CNTCR_OFF),
390 (RCAR_CNTCR_FCREQ(0U) | RCAR_CNTCR_EN));
391 }
392
393 #if !PMIC_ROHM_BD9571
rcar_pwrc_system_reset(void)394 void rcar_pwrc_system_reset(void)
395 {
396 mmio_write_32(RCAR_SRESCR, 0x5AA50000U | BIT_SOFTRESET);
397 }
398 #endif /* PMIC_ROHM_BD9571 */
399
400 #define RST_CA53_CPU0_BARH (0xE6160080U)
401 #define RST_CA53_CPU0_BARL (0xE6160084U)
402 #define RST_CA57_CPU0_BARH (0xE61600C0U)
403 #define RST_CA57_CPU0_BARL (0xE61600C4U)
404
rcar_pwrc_setup(void)405 void rcar_pwrc_setup(void)
406 {
407 uintptr_t rst_barh;
408 uintptr_t rst_barl;
409 uint32_t i, j;
410 uint64_t reset = (uint64_t) (&plat_secondary_reset) & 0xFFFFFFFF;
411
412 const uint32_t cluster[PLATFORM_CLUSTER_COUNT] = {
413 RCAR_CLUSTER_CA53,
414 RCAR_CLUSTER_CA57
415 };
416 const uintptr_t reg_barh[PLATFORM_CLUSTER_COUNT] = {
417 RST_CA53_CPU0_BARH,
418 RST_CA57_CPU0_BARH
419 };
420 const uintptr_t reg_barl[PLATFORM_CLUSTER_COUNT] = {
421 RST_CA53_CPU0_BARL,
422 RST_CA57_CPU0_BARL
423 };
424
425 for (i = 0; i < PLATFORM_CLUSTER_COUNT; i++) {
426 rst_barh = reg_barh[i];
427 rst_barl = reg_barl[i];
428 for (j = 0; j < rcar_pwrc_get_cpu_num(cluster[i]); j++) {
429 mmio_write_32(rst_barh, 0);
430 mmio_write_32(rst_barl, (uint32_t) reset);
431 rst_barh += 0x10;
432 rst_barl += 0x10;
433 }
434 }
435
436 rcar_lock_init();
437 }
438
439 #if RCAR_SYSTEM_SUSPEND
440 #define DBCAM_FLUSH(__bit) \
441 do { \
442 ; \
443 } while (!(mmio_read_32(DBSC4_REG_DBCAM##__bit##STAT0) & DBSC4_BIT_DBCAMxSTAT0))
444
445
446 static void __attribute__ ((section(".system_ram")))
rcar_pwrc_set_self_refresh(void)447 rcar_pwrc_set_self_refresh(void)
448 {
449 uint32_t reg = mmio_read_32(RCAR_PRR);
450 uint32_t cut, product;
451
452 product = reg & PRR_PRODUCT_MASK;
453 cut = reg & PRR_CUT_MASK;
454
455 if (product == PRR_PRODUCT_M3 && cut < PRR_PRODUCT_30) {
456 goto self_refresh;
457 }
458
459 if (product == PRR_PRODUCT_H3 && cut < PRR_PRODUCT_20) {
460 goto self_refresh;
461 }
462
463 mmio_write_32(DBSC4_REG_DBSYSCNT0, DBSC4_SET_DBSYSCNT0_WRITE_ENABLE);
464
465 self_refresh:
466
467 /* DFI_PHYMSTR_ACK setting */
468 mmio_write_32(DBSC4_REG_DBDFIPMSTRCNF,
469 mmio_read_32(DBSC4_REG_DBDFIPMSTRCNF) &
470 (~DBSC4_BIT_DBDFIPMSTRCNF_PMSTREN));
471
472 /* Set the Self-Refresh mode */
473 mmio_write_32(DBSC4_REG_DBACEN, 0);
474
475 if (product == PRR_PRODUCT_H3 && cut < PRR_PRODUCT_20)
476 rcar_micro_delay(100);
477 else if (product == PRR_PRODUCT_H3) {
478 mmio_write_32(DBSC4_REG_DBCAM0CTRL0, 1);
479 DBCAM_FLUSH(0);
480 DBCAM_FLUSH(1);
481 DBCAM_FLUSH(2);
482 DBCAM_FLUSH(3);
483 mmio_write_32(DBSC4_REG_DBCAM0CTRL0, 0);
484 } else if (product == PRR_PRODUCT_M3) {
485 mmio_write_32(DBSC4_REG_DBCAM0CTRL0, 1);
486 DBCAM_FLUSH(0);
487 DBCAM_FLUSH(1);
488 mmio_write_32(DBSC4_REG_DBCAM0CTRL0, 0);
489 } else {
490 mmio_write_32(DBSC4_REG_DBCAM0CTRL0, 1);
491 DBCAM_FLUSH(0);
492 mmio_write_32(DBSC4_REG_DBCAM0CTRL0, 0);
493 }
494
495 /* Set the SDRAM calibration configuration register */
496 mmio_write_32(DBSC4_REG_DBCALCNF, 0);
497
498 reg = DBSC4_SET_DBCMD_OPC_PRE | DBSC4_SET_DBCMD_CH_ALL |
499 DBSC4_SET_DBCMD_RANK_ALL | DBSC4_SET_DBCMD_ARG_ALL;
500 mmio_write_32(DBSC4_REG_DBCMD, reg);
501 while (mmio_read_32(DBSC4_REG_DBWAIT))
502 ;
503
504 /* Self-Refresh entry command */
505 reg = DBSC4_SET_DBCMD_OPC_SR | DBSC4_SET_DBCMD_CH_ALL |
506 DBSC4_SET_DBCMD_RANK_ALL | DBSC4_SET_DBCMD_ARG_ENTER;
507 mmio_write_32(DBSC4_REG_DBCMD, reg);
508 while (mmio_read_32(DBSC4_REG_DBWAIT))
509 ;
510
511 /* Mode Register Write command. (ODT disabled) */
512 reg = DBSC4_SET_DBCMD_OPC_MRW | DBSC4_SET_DBCMD_CH_ALL |
513 DBSC4_SET_DBCMD_RANK_ALL | DBSC4_SET_DBCMD_ARG_MRW_ODTC;
514 mmio_write_32(DBSC4_REG_DBCMD, reg);
515 while (mmio_read_32(DBSC4_REG_DBWAIT))
516 ;
517
518 /* Power Down entry command */
519 reg = DBSC4_SET_DBCMD_OPC_PD | DBSC4_SET_DBCMD_CH_ALL |
520 DBSC4_SET_DBCMD_RANK_ALL | DBSC4_SET_DBCMD_ARG_ENTER;
521 mmio_write_32(DBSC4_REG_DBCMD, reg);
522 while (mmio_read_32(DBSC4_REG_DBWAIT))
523 ;
524
525 /* Set the auto-refresh enable register */
526 mmio_write_32(DBSC4_REG_DBRFEN, 0U);
527 rcar_micro_delay(1U);
528
529 if (product == PRR_PRODUCT_M3 && cut < PRR_PRODUCT_30)
530 return;
531
532 if (product == PRR_PRODUCT_H3 && cut < PRR_PRODUCT_20)
533 return;
534
535 mmio_write_32(DBSC4_REG_DBSYSCNT0, DBSC4_SET_DBSYSCNT0_WRITE_DISABLE);
536 }
537
538 static void __attribute__ ((section(".system_ram")))
rcar_pwrc_set_self_refresh_e3(void)539 rcar_pwrc_set_self_refresh_e3(void)
540 {
541 uint32_t ddr_md;
542 uint32_t reg;
543
544 ddr_md = (mmio_read_32(RST_MODEMR) >> 19) & RST_MODEMR_BIT0;
545
546 /* Write enable */
547 mmio_write_32(DBSC4_REG_DBSYSCNT0, DBSC4_SET_DBSYSCNT0_WRITE_ENABLE);
548 mmio_write_32(DBSC4_REG_DBACEN, 0);
549 DBCAM_FLUSH(0);
550
551 reg = DBSC4_SET_DBCMD_OPC_PRE | DBSC4_SET_DBCMD_CH_ALL |
552 DBSC4_SET_DBCMD_RANK_ALL | DBSC4_SET_DBCMD_ARG_ALL;
553 mmio_write_32(DBSC4_REG_DBCMD, reg);
554 while (mmio_read_32(DBSC4_REG_DBWAIT))
555 ;
556
557 reg = DBSC4_SET_DBCMD_OPC_SR | DBSC4_SET_DBCMD_CH_ALL |
558 DBSC4_SET_DBCMD_RANK_ALL | DBSC4_SET_DBCMD_ARG_ENTER;
559 mmio_write_32(DBSC4_REG_DBCMD, reg);
560 while (mmio_read_32(DBSC4_REG_DBWAIT))
561 ;
562
563 /*
564 * Set the auto-refresh enable register
565 * Set the ARFEN bit to 0 in the DBRFEN
566 */
567 mmio_write_32(DBSC4_REG_DBRFEN, 0);
568
569 mmio_write_32(DBSC4_REG_DBPDLK0, DBSC4_SET_DBPDLK0_PHY_ACCESS);
570
571 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_ACIOCR0);
572 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_ACIOCR0);
573
574 /* DDR_DXCCR */
575 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DXCCR);
576 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DXCCR);
577
578 /* DDR_PGCR1 */
579 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_PGCR1);
580 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_PGCR1);
581
582 /* DDR_ACIOCR1 */
583 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_ACIOCR1);
584 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_ACIOCR1);
585
586 /* DDR_ACIOCR3 */
587 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_ACIOCR3);
588 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_ACIOCR3);
589
590 /* DDR_ACIOCR5 */
591 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_ACIOCR5);
592 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_ACIOCR5);
593
594 /* DDR_DX0GCR2 */
595 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX0GCR2);
596 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX0GCR2);
597
598 /* DDR_DX1GCR2 */
599 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX1GCR2);
600 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX1GCR2);
601
602 /* DDR_DX2GCR2 */
603 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX2GCR2);
604 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX2GCR2);
605
606 /* DDR_DX3GCR2 */
607 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX3GCR2);
608 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX3GCR2);
609
610 /* DDR_ZQCR */
611 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_ZQCR);
612
613 mmio_write_32(DBSC4_REG_DBPDRGD0, ddr_md == 0 ?
614 DBSC4_SET_DBPDRGD0_ZQCR_MD19_0 :
615 DBSC4_SET_DBPDRGD0_ZQCR_MD19_1);
616
617 /* DDR_DX0GCR0 */
618 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX0GCR0);
619 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX0GCR0);
620
621 /* DDR_DX1GCR0 */
622 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX1GCR0);
623 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX1GCR0);
624
625 /* DDR_DX2GCR0 */
626 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX2GCR0);
627 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX2GCR0);
628
629 /* DDR_DX3GCR0 */
630 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX3GCR0);
631 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX3GCR0);
632
633 /* DDR_DX0GCR1 */
634 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX0GCR1);
635 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX0GCR1);
636
637 /* DDR_DX1GCR1 */
638 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX1GCR1);
639 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX1GCR1);
640
641 /* DDR_DX2GCR1 */
642 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX2GCR1);
643 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX2GCR1);
644
645 /* DDR_DX3GCR1 */
646 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX3GCR1);
647 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX3GCR1);
648
649 /* DDR_DX0GCR3 */
650 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX0GCR3);
651 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX0GCR3);
652
653 /* DDR_DX1GCR3 */
654 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX1GCR3);
655 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX1GCR3);
656
657 /* DDR_DX2GCR3 */
658 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX2GCR3);
659 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX2GCR3);
660
661 /* DDR_DX3GCR3 */
662 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX3GCR3);
663 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX3GCR3);
664
665 /* Write disable */
666 mmio_write_32(DBSC4_REG_DBSYSCNT0, DBSC4_SET_DBSYSCNT0_WRITE_DISABLE);
667 }
668
669 void __attribute__ ((section(".system_ram"))) __attribute__ ((noinline))
rcar_pwrc_go_suspend_to_ram(void)670 rcar_pwrc_go_suspend_to_ram(void)
671 {
672 #if PMIC_ROHM_BD9571
673 int32_t rc = -1, qllm = -1;
674 uint8_t mode;
675 uint32_t i;
676 #endif
677 uint32_t reg, product;
678
679 reg = mmio_read_32(RCAR_PRR);
680 product = reg & PRR_PRODUCT_MASK;
681
682 if (product != PRR_PRODUCT_E3)
683 rcar_pwrc_set_self_refresh();
684 else
685 rcar_pwrc_set_self_refresh_e3();
686
687 #if PMIC_ROHM_BD9571
688 /* Set QLLM Cnt Disable */
689 for (i = 0; (i < PMIC_RETRY_MAX) && (qllm != 0); i++)
690 qllm = rcar_iic_dvfs_send(PMIC, PMIC_QLLM_CNT, 0);
691
692 /* Set trigger of power down to PMIV */
693 for (i = 0; (i < PMIC_RETRY_MAX) && (rc != 0) && (qllm == 0); i++) {
694 rc = rcar_iic_dvfs_receive(PMIC, PMIC_BKUP_MODE_CNT, &mode);
695 if (rc == 0) {
696 mode |= BIT_BKUP_CTRL_OUT;
697 rc = rcar_iic_dvfs_send(PMIC, PMIC_BKUP_MODE_CNT, mode);
698 }
699 }
700 #endif
701 wfi();
702
703 while (1)
704 ;
705 }
706
rcar_pwrc_set_suspend_to_ram(void)707 void rcar_pwrc_set_suspend_to_ram(void)
708 {
709 uintptr_t jump = (uintptr_t) &rcar_pwrc_go_suspend_to_ram;
710 uintptr_t stack = (uintptr_t) (DEVICE_SRAM_STACK_BASE +
711 DEVICE_SRAM_STACK_SIZE);
712 uint32_t sctlr;
713
714 rcar_pwrc_save_timer_state();
715
716 /* disable MMU */
717 sctlr = (uint32_t) read_sctlr_el3();
718 sctlr &= (uint32_t) ~SCTLR_EL3_M_BIT;
719 write_sctlr_el3((uint64_t) sctlr);
720
721 rcar_pwrc_switch_stack(jump, stack, NULL);
722 }
723
rcar_pwrc_init_suspend_to_ram(void)724 void rcar_pwrc_init_suspend_to_ram(void)
725 {
726 #if PMIC_ROHM_BD9571
727 uint8_t mode;
728
729 if (rcar_iic_dvfs_receive(PMIC, PMIC_BKUP_MODE_CNT, &mode))
730 panic();
731
732 mode &= (uint8_t) (~BIT_BKUP_CTRL_OUT);
733 if (rcar_iic_dvfs_send(PMIC, PMIC_BKUP_MODE_CNT, mode))
734 panic();
735 #endif
736 }
737
rcar_pwrc_suspend_to_ram(void)738 void rcar_pwrc_suspend_to_ram(void)
739 {
740 #if RCAR_SYSTEM_RESET_KEEPON_DDR
741 int32_t error;
742
743 error = rcar_iic_dvfs_send(PMIC, REG_KEEP10, 0);
744 if (error) {
745 ERROR("Failed send KEEP10 init ret=%d\n", error);
746 return;
747 }
748 #endif
749 rcar_pwrc_set_suspend_to_ram();
750 }
751 #endif
752
rcar_pwrc_code_copy_to_system_ram(void)753 void rcar_pwrc_code_copy_to_system_ram(void)
754 {
755 int ret __attribute__ ((unused)); /* in assert */
756 uint32_t attr;
757 struct device_sram_t {
758 uintptr_t base;
759 size_t len;
760 } sram = {
761 .base = (uintptr_t) DEVICE_SRAM_BASE,
762 .len = DEVICE_SRAM_SIZE,
763 };
764 struct ddr_code_t {
765 void *base;
766 size_t len;
767 } code = {
768 .base = (void *) SRAM_COPY_START,
769 .len = SYSTEM_RAM_END - SYSTEM_RAM_START,
770 };
771
772 attr = MT_MEMORY | MT_RW | MT_SECURE | MT_EXECUTE_NEVER;
773 ret = xlat_change_mem_attributes(sram.base, sram.len, attr);
774 assert(ret == 0);
775
776 memcpy((void *)sram.base, code.base, code.len);
777 flush_dcache_range((uint64_t) sram.base, code.len);
778
779 attr = MT_MEMORY | MT_RO | MT_SECURE | MT_EXECUTE;
780 ret = xlat_change_mem_attributes(sram.base, sram.len, attr);
781 assert(ret == 0);
782
783 /* Invalidate instruction cache */
784 plat_invalidate_icache();
785 dsb();
786 isb();
787 }
788
rcar_pwrc_get_cluster(void)789 uint32_t rcar_pwrc_get_cluster(void)
790 {
791 uint32_t reg;
792
793 reg = mmio_read_32(RCAR_PRR);
794
795 if (reg & (1U << (STATE_CA53_CPU + RCAR_CA53CPU_NUM_MAX)))
796 return RCAR_CLUSTER_CA57;
797
798 if (reg & (1U << (STATE_CA57_CPU + RCAR_CA57CPU_NUM_MAX)))
799 return RCAR_CLUSTER_CA53;
800
801 return RCAR_CLUSTER_A53A57;
802 }
803
rcar_pwrc_get_mpidr_cluster(uint64_t mpidr)804 uint32_t rcar_pwrc_get_mpidr_cluster(uint64_t mpidr)
805 {
806 uint32_t c = rcar_pwrc_get_cluster();
807
808 if (IS_A53A57(c)) {
809 if (mpidr & MPIDR_CLUSTER_MASK)
810 return RCAR_CLUSTER_CA53;
811
812 return RCAR_CLUSTER_CA57;
813 }
814
815 return c;
816 }
817
818 #if RCAR_LSI == RCAR_D3
rcar_pwrc_get_cpu_num(uint32_t c)819 uint32_t rcar_pwrc_get_cpu_num(uint32_t c)
820 {
821 return 1;
822 }
823 #else
rcar_pwrc_get_cpu_num(uint32_t c)824 uint32_t rcar_pwrc_get_cpu_num(uint32_t c)
825 {
826 uint32_t reg = mmio_read_32(RCAR_PRR);
827 uint32_t count = 0, i;
828
829 if (IS_A53A57(c) || IS_CA53(c)) {
830 if (reg & (1 << (STATE_CA53_CPU + RCAR_CA53CPU_NUM_MAX)))
831 goto count_ca57;
832
833 for (i = 0; i < RCAR_CA53CPU_NUM_MAX; i++) {
834 if (reg & (1 << (STATE_CA53_CPU + i)))
835 continue;
836 count++;
837 }
838 }
839
840 count_ca57:
841 if (IS_A53A57(c) || IS_CA57(c)) {
842 if (reg & (1U << (STATE_CA57_CPU + RCAR_CA57CPU_NUM_MAX)))
843 goto done;
844
845 for (i = 0; i < RCAR_CA57CPU_NUM_MAX; i++) {
846 if (reg & (1 << (STATE_CA57_CPU + i)))
847 continue;
848 count++;
849 }
850 }
851
852 done:
853 return count;
854 }
855 #endif
856
rcar_pwrc_cpu_on_check(uint64_t mpidr)857 int32_t rcar_pwrc_cpu_on_check(uint64_t mpidr)
858 {
859 uint64_t i;
860 uint64_t j;
861 uint64_t cpu_count;
862 uintptr_t reg_PSTR;
863 uint32_t status;
864 uint64_t my_cpu;
865 int32_t rtn;
866 uint32_t my_cluster_type;
867 const uint32_t cluster_type[PLATFORM_CLUSTER_COUNT] = {
868 RCAR_CLUSTER_CA53,
869 RCAR_CLUSTER_CA57
870 };
871 const uintptr_t registerPSTR[PLATFORM_CLUSTER_COUNT] = {
872 RCAR_CA53PSTR,
873 RCAR_CA57PSTR
874 };
875
876 my_cluster_type = rcar_pwrc_get_cluster();
877
878 rtn = 0;
879 my_cpu = mpidr & ((uint64_t)(MPIDR_CPU_MASK));
880 for (i = 0U; i < ((uint64_t)(PLATFORM_CLUSTER_COUNT)); i++) {
881 cpu_count = rcar_pwrc_get_cpu_num(cluster_type[i]);
882 reg_PSTR = registerPSTR[i];
883 for (j = 0U; j < cpu_count; j++) {
884 if ((my_cluster_type != cluster_type[i]) || (my_cpu != j)) {
885 status = mmio_read_32(reg_PSTR) >> (j * 4U);
886 if ((status & 0x00000003U) == 0U) {
887 rtn--;
888 }
889 }
890 }
891 }
892
893 return rtn;
894 }
895