1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright (c) 2017-2021, STMicroelectronics - All Rights Reserved
4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
5 */
6#include <dt-bindings/interrupt-controller/arm-gic.h>
7#include <dt-bindings/clock/stm32mp1-clks.h>
8#include <dt-bindings/reset/stm32mp1-resets.h>
9
10/ {
11	#address-cells = <1>;
12	#size-cells = <1>;
13
14	cpus {
15		#address-cells = <1>;
16		#size-cells = <0>;
17
18		cpu0: cpu@0 {
19			compatible = "arm,cortex-a7";
20			device_type = "cpu";
21			reg = <0>;
22		};
23	};
24
25	psci {
26		compatible = "arm,psci-1.0";
27		method = "smc";
28	};
29
30	intc: interrupt-controller@a0021000 {
31		compatible = "arm,cortex-a7-gic";
32		#interrupt-cells = <3>;
33		interrupt-controller;
34		reg = <0xa0021000 0x1000>,
35		      <0xa0022000 0x2000>;
36	};
37
38	clocks {
39		clk_hse: clk-hse {
40			#clock-cells = <0>;
41			compatible = "fixed-clock";
42			clock-frequency = <24000000>;
43		};
44
45		clk_hsi: clk-hsi {
46			#clock-cells = <0>;
47			compatible = "fixed-clock";
48			clock-frequency = <64000000>;
49		};
50
51		clk_lse: clk-lse {
52			#clock-cells = <0>;
53			compatible = "fixed-clock";
54			clock-frequency = <32768>;
55		};
56
57		clk_lsi: clk-lsi {
58			#clock-cells = <0>;
59			compatible = "fixed-clock";
60			clock-frequency = <32000>;
61		};
62
63		clk_csi: clk-csi {
64			#clock-cells = <0>;
65			compatible = "fixed-clock";
66			clock-frequency = <4000000>;
67		};
68	};
69
70	soc {
71		compatible = "simple-bus";
72		#address-cells = <1>;
73		#size-cells = <1>;
74		interrupt-parent = <&intc>;
75		ranges;
76
77		timers12: timer@40006000 {
78			#address-cells = <1>;
79			#size-cells = <0>;
80			compatible = "st,stm32-timers";
81			reg = <0x40006000 0x400>;
82			clocks = <&rcc TIM12_K>;
83			clock-names = "int";
84			status = "disabled";
85		};
86
87		usart2: serial@4000e000 {
88			compatible = "st,stm32h7-uart";
89			reg = <0x4000e000 0x400>;
90			interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>;
91			clocks = <&rcc USART2_K>;
92			resets = <&rcc USART2_R>;
93			status = "disabled";
94		};
95
96		usart3: serial@4000f000 {
97			compatible = "st,stm32h7-uart";
98			reg = <0x4000f000 0x400>;
99			interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>;
100			clocks = <&rcc USART3_K>;
101			resets = <&rcc USART3_R>;
102			status = "disabled";
103		};
104
105		uart4: serial@40010000 {
106			compatible = "st,stm32h7-uart";
107			reg = <0x40010000 0x400>;
108			interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>;
109			clocks = <&rcc UART4_K>;
110			resets = <&rcc UART4_R>;
111			wakeup-source;
112			status = "disabled";
113		};
114
115		uart5: serial@40011000 {
116			compatible = "st,stm32h7-uart";
117			reg = <0x40011000 0x400>;
118			interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>;
119			clocks = <&rcc UART5_K>;
120			resets = <&rcc UART5_R>;
121			status = "disabled";
122		};
123
124		i2c2: i2c@40013000 {
125			compatible = "st,stm32mp15-i2c";
126			reg = <0x40013000 0x400>;
127			interrupt-names = "event", "error";
128			interrupts = <&exti 22 IRQ_TYPE_LEVEL_HIGH>,
129				     <&intc GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
130			clocks = <&rcc I2C2_K>;
131			resets = <&rcc I2C2_R>;
132			#address-cells = <1>;
133			#size-cells = <0>;
134			st,syscfg-fmp = <&syscfg 0x4 0x2>;
135			wakeup-source;
136			status = "disabled";
137		};
138
139		uart7: serial@40018000 {
140			compatible = "st,stm32h7-uart";
141			reg = <0x40018000 0x400>;
142			interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>;
143			clocks = <&rcc UART7_K>;
144			resets = <&rcc UART7_R>;
145			status = "disabled";
146		};
147
148		uart8: serial@40019000 {
149			compatible = "st,stm32h7-uart";
150			reg = <0x40019000 0x400>;
151			interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>;
152			clocks = <&rcc UART8_K>;
153			resets = <&rcc UART8_R>;
154			status = "disabled";
155		};
156
157		usart6: serial@44003000 {
158			compatible = "st,stm32h7-uart";
159			reg = <0x44003000 0x400>;
160			interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>;
161			clocks = <&rcc USART6_K>;
162			resets = <&rcc USART6_R>;
163			status = "disabled";
164		};
165
166		timers15: timer@44006000 {
167			#address-cells = <1>;
168			#size-cells = <0>;
169			compatible = "st,stm32-timers";
170			reg = <0x44006000 0x400>;
171			clocks = <&rcc TIM15_K>;
172			clock-names = "int";
173			status = "disabled";
174		};
175
176		usbotg_hs: usb-otg@49000000 {
177			compatible = "st,stm32mp15-hsotg", "snps,dwc2";
178			reg = <0x49000000 0x10000>;
179			clocks = <&rcc USBO_K>;
180			clock-names = "otg";
181			resets = <&rcc USBO_R>;
182			reset-names = "dwc2";
183			interrupts-extended = <&exti 44 IRQ_TYPE_LEVEL_HIGH>;
184			g-rx-fifo-size = <512>;
185			g-np-tx-fifo-size = <32>;
186			g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
187			dr_mode = "otg";
188			usb33d-supply = <&usb33>;
189			status = "disabled";
190		};
191
192		rcc: rcc@50000000 {
193			compatible = "st,stm32mp1-rcc", "syscon";
194			reg = <0x50000000 0x1000>;
195			#address-cells = <1>;
196			#size-cells = <0>;
197			#clock-cells = <1>;
198			#reset-cells = <1>;
199			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
200			secure-interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
201			secure-interrupt-names = "wakeup";
202		};
203
204		pwr_regulators: pwr@50001000 {
205			compatible = "st,stm32mp1,pwr-reg";
206			reg = <0x50001000 0x10>;
207			st,tzcr = <&rcc 0x0 0x1>;
208
209			reg11: reg11 {
210				regulator-name = "reg11";
211				regulator-min-microvolt = <1100000>;
212				regulator-max-microvolt = <1100000>;
213			};
214
215			reg18: reg18 {
216				regulator-name = "reg18";
217				regulator-min-microvolt = <1800000>;
218				regulator-max-microvolt = <1800000>;
219			};
220
221			usb33: usb33 {
222				regulator-name = "usb33";
223				regulator-min-microvolt = <3300000>;
224				regulator-max-microvolt = <3300000>;
225			};
226		};
227
228		pwr_mcu: pwr_mcu@50001014 {
229			compatible = "st,stm32mp151-pwr-mcu", "syscon";
230			reg = <0x50001014 0x4>;
231		};
232
233		pwr_irq: pwr@50001020 {
234			compatible = "st,stm32mp1-pwr";
235			reg = <0x50001020 0x100>;
236			interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
237			interrupt-controller;
238			#interrupt-cells = <3>;
239		};
240
241		exti: interrupt-controller@5000d000 {
242			compatible = "st,stm32mp1-exti", "syscon";
243			interrupt-controller;
244			#interrupt-cells = <2>;
245			reg = <0x5000d000 0x400>;
246
247			/* exti_pwr is an extra interrupt controller used for
248			 * EXTI 55 to 60. It's mapped on pwr interrupt
249			 * controller.
250			 */
251			exti_pwr: exti-pwr {
252				interrupt-controller;
253				#interrupt-cells = <2>;
254				interrupt-parent = <&pwr_irq>;
255				st,irq-number = <6>;
256			};
257		};
258
259		syscfg: syscon@50020000 {
260			compatible = "st,stm32mp157-syscfg", "syscon";
261			reg = <0x50020000 0x400>;
262			clocks = <&rcc SYSCFG>;
263		};
264
265		hash1: hash@54002000 {
266			compatible = "st,stm32f756-hash";
267			reg = <0x54002000 0x400>;
268			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
269			clocks = <&rcc HASH1>;
270			resets = <&rcc HASH1_R>;
271			status = "disabled";
272		};
273
274		rng1: rng@54003000 {
275			compatible = "st,stm32-rng";
276			reg = <0x54003000 0x400>;
277			clocks = <&rcc RNG1_K>;
278			resets = <&rcc RNG1_R>;
279			status = "disabled";
280		};
281
282		fmc: memory-controller@58002000 {
283			#address-cells = <2>;
284			#size-cells = <1>;
285			compatible = "st,stm32mp1-fmc2-ebi";
286			reg = <0x58002000 0x1000>;
287			clocks = <&rcc FMC_K>;
288			resets = <&rcc FMC_R>;
289			status = "disabled";
290
291			ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
292				 <1 0 0x64000000 0x04000000>, /* EBI CS 2 */
293				 <2 0 0x68000000 0x04000000>, /* EBI CS 3 */
294				 <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
295				 <4 0 0x80000000 0x10000000>; /* NAND */
296
297			nand-controller@4,0 {
298				#address-cells = <1>;
299				#size-cells = <0>;
300				compatible = "st,stm32mp1-fmc2-nfc";
301				reg = <4 0x00000000 0x1000>,
302				      <4 0x08010000 0x1000>,
303				      <4 0x08020000 0x1000>,
304				      <4 0x01000000 0x1000>,
305				      <4 0x09010000 0x1000>,
306				      <4 0x09020000 0x1000>;
307				interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
308				status = "disabled";
309			};
310		};
311
312		qspi: spi@58003000 {
313			compatible = "st,stm32f469-qspi";
314			reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
315			reg-names = "qspi", "qspi_mm";
316			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
317			clocks = <&rcc QSPI_K>;
318			resets = <&rcc QSPI_R>;
319			status = "disabled";
320		};
321
322		sdmmc1: mmc@58005000 {
323			compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
324			arm,primecell-periphid = <0x00253180>;
325			reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
326			interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
327			interrupt-names = "cmd_irq";
328			clocks = <&rcc SDMMC1_K>;
329			clock-names = "apb_pclk";
330			resets = <&rcc SDMMC1_R>;
331			cap-sd-highspeed;
332			cap-mmc-highspeed;
333			max-frequency = <120000000>;
334			status = "disabled";
335		};
336
337		sdmmc2: mmc@58007000 {
338			compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
339			arm,primecell-periphid = <0x00253180>;
340			reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
341			interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
342			interrupt-names = "cmd_irq";
343			clocks = <&rcc SDMMC2_K>;
344			clock-names = "apb_pclk";
345			resets = <&rcc SDMMC2_R>;
346			cap-sd-highspeed;
347			cap-mmc-highspeed;
348			max-frequency = <120000000>;
349			status = "disabled";
350		};
351
352		iwdg2: watchdog@5a002000 {
353			compatible = "st,stm32mp1-iwdg";
354			reg = <0x5a002000 0x400>;
355			secure-interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
356			clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
357			clock-names = "pclk", "lsi";
358			status = "disabled";
359		};
360
361		ddr: ddr@5a003000{
362			compatible = "st,stm32mp1-ddr";
363			reg = <0x5A003000 0x550 0x5A004000 0x234>;
364			clocks = <&rcc AXIDCG>,
365				 <&rcc DDRC1>,
366				 <&rcc DDRC2>,
367				 <&rcc DDRPHYC>,
368				 <&rcc DDRCAPB>,
369				 <&rcc DDRPHYCAPB>;
370			clock-names = "axidcg",
371				      "ddrc1",
372				      "ddrc2",
373				      "ddrphyc",
374				      "ddrcapb",
375				      "ddrphycapb";
376			status = "okay";
377		};
378
379		usbphyc: usbphyc@5a006000 {
380			#address-cells = <1>;
381			#size-cells = <0>;
382			#clock-cells = <0>;
383			compatible = "st,stm32mp1-usbphyc";
384			reg = <0x5a006000 0x1000>;
385			clocks = <&rcc USBPHY_K>;
386			resets = <&rcc USBPHY_R>;
387			vdda1v1-supply = <&reg11>;
388			vdda1v8-supply = <&reg18>;
389			status = "disabled";
390
391			usbphyc_port0: usb-phy@0 {
392				#phy-cells = <0>;
393				reg = <0>;
394			};
395
396			usbphyc_port1: usb-phy@1 {
397				#phy-cells = <1>;
398				reg = <1>;
399			};
400		};
401
402		usart1: serial@5c000000 {
403			compatible = "st,stm32h7-uart";
404			reg = <0x5c000000 0x400>;
405			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
406			clocks = <&rcc USART1_K>;
407			resets = <&rcc USART1_R>;
408			status = "disabled";
409		};
410
411		spi6: spi@5c001000 {
412			#address-cells = <1>;
413			#size-cells = <0>;
414			compatible = "st,stm32h7-spi";
415			reg = <0x5c001000 0x400>;
416			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
417			clocks = <&rcc SPI6_K>;
418			resets = <&rcc SPI6_R>;
419			status = "disabled";
420		};
421
422		i2c4: i2c@5c002000 {
423			compatible = "st,stm32mp15-i2c";
424			reg = <0x5c002000 0x400>;
425			interrupt-names = "event", "error";
426			interrupts-extended = <&exti 24 IRQ_TYPE_LEVEL_HIGH>,
427					      <&intc GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
428			clocks = <&rcc I2C4_K>;
429			resets = <&rcc I2C4_R>;
430			#address-cells = <1>;
431			#size-cells = <0>;
432			st,syscfg-fmp = <&syscfg 0x4 0x8>;
433			wakeup-source;
434			status = "disabled";
435		};
436
437		iwdg1: watchdog@5c003000 {
438			compatible = "st,stm32mp1-iwdg";
439			reg = <0x5C003000 0x400>;
440			interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
441			clocks = <&rcc IWDG1>, <&rcc CK_LSI>;
442			clock-names = "pclk", "lsi";
443			status = "disabled";
444		};
445
446		rtc: rtc@5c004000 {
447			compatible = "st,stm32mp1-rtc";
448			reg = <0x5c004000 0x400>;
449			clocks = <&rcc RTCAPB>, <&rcc RTC>;
450			clock-names = "pclk", "rtc_ck";
451			interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>;
452			status = "disabled";
453		};
454
455		bsec: efuse@5c005000 {
456			compatible = "st,stm32mp15-bsec";
457			reg = <0x5c005000 0x400>;
458			#address-cells = <1>;
459			#size-cells = <1>;
460			ts_cal1: calib@5c {
461				reg = <0x5c 0x2>;
462			};
463			ts_cal2: calib@5e {
464				reg = <0x5e 0x2>;
465			};
466		};
467
468		etzpc: etzpc@5c007000 {
469			compatible = "st,stm32-etzpc";
470			reg = <0x5C007000 0x400>;
471			clocks = <&rcc TZPC>;
472			status = "disabled";
473			secure-status = "okay";
474		};
475
476		stgen: stgen@5c008000 {
477			compatible = "st,stm32-stgen";
478			reg = <0x5C008000 0x1000>;
479		};
480
481		i2c6: i2c@5c009000 {
482			compatible = "st,stm32mp15-i2c";
483			reg = <0x5c009000 0x400>;
484			interrupt-names = "event", "error";
485			interrupts-extended = <&exti 54 IRQ_TYPE_LEVEL_HIGH>,
486					      <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
487			clocks = <&rcc I2C6_K>;
488			resets = <&rcc I2C6_R>;
489			#address-cells = <1>;
490			#size-cells = <0>;
491			st,syscfg-fmp = <&syscfg 0x4 0x20>;
492			wakeup-source;
493			status = "disabled";
494		};
495
496		tamp: tamp@5c00a000 {
497			compatible = "st,stm32-tamp", "simple-bus", "syscon", "simple-mfd";
498			reg = <0x5c00a000 0x400>;
499			secure-interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
500			clocks = <&rcc RTCAPB>;
501		};
502
503		/*
504		 * Break node order to solve dependency probe issue between
505		 * pinctrl and exti.
506		 */
507		pinctrl: pin-controller@50002000 {
508			#address-cells = <1>;
509			#size-cells = <1>;
510			compatible = "st,stm32mp157-pinctrl";
511			ranges = <0 0x50002000 0xa400>;
512			interrupt-parent = <&exti>;
513			st,syscfg = <&exti 0x60 0xff>;
514			pins-are-numbered;
515
516			gpioa: gpio@50002000 {
517				gpio-controller;
518				#gpio-cells = <2>;
519				interrupt-controller;
520				#interrupt-cells = <2>;
521				reg = <0x0 0x400>;
522				clocks = <&rcc GPIOA>;
523				st,bank-name = "GPIOA";
524				status = "disabled";
525			};
526
527			gpiob: gpio@50003000 {
528				gpio-controller;
529				#gpio-cells = <2>;
530				interrupt-controller;
531				#interrupt-cells = <2>;
532				reg = <0x1000 0x400>;
533				clocks = <&rcc GPIOB>;
534				st,bank-name = "GPIOB";
535				status = "disabled";
536			};
537
538			gpioc: gpio@50004000 {
539				gpio-controller;
540				#gpio-cells = <2>;
541				interrupt-controller;
542				#interrupt-cells = <2>;
543				reg = <0x2000 0x400>;
544				clocks = <&rcc GPIOC>;
545				st,bank-name = "GPIOC";
546				status = "disabled";
547			};
548
549			gpiod: gpio@50005000 {
550				gpio-controller;
551				#gpio-cells = <2>;
552				interrupt-controller;
553				#interrupt-cells = <2>;
554				reg = <0x3000 0x400>;
555				clocks = <&rcc GPIOD>;
556				st,bank-name = "GPIOD";
557				status = "disabled";
558			};
559
560			gpioe: gpio@50006000 {
561				gpio-controller;
562				#gpio-cells = <2>;
563				interrupt-controller;
564				#interrupt-cells = <2>;
565				reg = <0x4000 0x400>;
566				clocks = <&rcc GPIOE>;
567				st,bank-name = "GPIOE";
568				status = "disabled";
569			};
570
571			gpiof: gpio@50007000 {
572				gpio-controller;
573				#gpio-cells = <2>;
574				interrupt-controller;
575				#interrupt-cells = <2>;
576				reg = <0x5000 0x400>;
577				clocks = <&rcc GPIOF>;
578				st,bank-name = "GPIOF";
579				status = "disabled";
580			};
581
582			gpiog: gpio@50008000 {
583				gpio-controller;
584				#gpio-cells = <2>;
585				interrupt-controller;
586				#interrupt-cells = <2>;
587				reg = <0x6000 0x400>;
588				clocks = <&rcc GPIOG>;
589				st,bank-name = "GPIOG";
590				status = "disabled";
591			};
592
593			gpioh: gpio@50009000 {
594				gpio-controller;
595				#gpio-cells = <2>;
596				interrupt-controller;
597				#interrupt-cells = <2>;
598				reg = <0x7000 0x400>;
599				clocks = <&rcc GPIOH>;
600				st,bank-name = "GPIOH";
601				status = "disabled";
602			};
603
604			gpioi: gpio@5000a000 {
605				gpio-controller;
606				#gpio-cells = <2>;
607				interrupt-controller;
608				#interrupt-cells = <2>;
609				reg = <0x8000 0x400>;
610				clocks = <&rcc GPIOI>;
611				st,bank-name = "GPIOI";
612				status = "disabled";
613			};
614
615			gpioj: gpio@5000b000 {
616				gpio-controller;
617				#gpio-cells = <2>;
618				interrupt-controller;
619				#interrupt-cells = <2>;
620				reg = <0x9000 0x400>;
621				clocks = <&rcc GPIOJ>;
622				st,bank-name = "GPIOJ";
623				status = "disabled";
624			};
625
626			gpiok: gpio@5000c000 {
627				gpio-controller;
628				#gpio-cells = <2>;
629				interrupt-controller;
630				#interrupt-cells = <2>;
631				reg = <0xa000 0x400>;
632				clocks = <&rcc GPIOK>;
633				st,bank-name = "GPIOK";
634				status = "disabled";
635			};
636		};
637
638		pinctrl_z: pin-controller-z@54004000 {
639			#address-cells = <1>;
640			#size-cells = <1>;
641			compatible = "st,stm32mp157-z-pinctrl";
642			ranges = <0 0x54004000 0x400>;
643			pins-are-numbered;
644			interrupt-parent = <&exti>;
645			st,syscfg = <&exti 0x60 0xff>;
646
647			gpioz: gpio@54004000 {
648				gpio-controller;
649				#gpio-cells = <2>;
650				interrupt-controller;
651				#interrupt-cells = <2>;
652				reg = <0 0x400>;
653				clocks = <&rcc GPIOZ>;
654				st,bank-name = "GPIOZ";
655				st,bank-ioport = <11>;
656				status = "disabled";
657			};
658		};
659	};
660};
661