1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright (C) Arrow Electronics 2019 - All Rights Reserved
4 * Author: Botond Kardos <botond.kardos@arroweurope.com>
5 *
6 * Copyright (C) Linaro Ltd 2019 - All Rights Reserved
7 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
8 */
9
10/dts-v1/;
11
12#include "stm32mp157.dtsi"
13#include "stm32mp15-pinctrl.dtsi"
14#include "stm32mp15xxac-pinctrl.dtsi"
15#include <dt-bindings/clock/stm32mp1-clksrc.h>
16#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
17
18/ {
19	model = "Arrow Electronics STM32MP157A Avenger96 board";
20	compatible = "arrow,stm32mp157a-avenger96", "st,stm32mp157";
21
22	aliases {
23		mmc0 = &sdmmc1;
24		serial0 = &uart4;
25		serial1 = &uart7;
26	};
27
28	chosen {
29		stdout-path = "serial0:115200n8";
30	};
31
32	memory@c0000000 {
33		device_type = "memory";
34		reg = <0xc0000000 0x40000000>;
35	};
36};
37
38&i2c4 {
39	pinctrl-names = "default";
40	pinctrl-0 = <&i2c4_pins_a>;
41	i2c-scl-rising-time-ns = <185>;
42	i2c-scl-falling-time-ns = <20>;
43	status = "okay";
44
45	pmic: stpmic@33 {
46		compatible = "st,stpmic1";
47		reg = <0x33>;
48		interrupts-extended = <&exti_pwr 55 IRQ_TYPE_EDGE_FALLING>;
49		interrupt-controller;
50		#interrupt-cells = <2>;
51		status = "okay";
52
53		st,main-control-register = <0x04>;
54		st,vin-control-register = <0xc0>;
55		st,usb-control-register = <0x30>;
56
57		regulators {
58			compatible = "st,stpmic1-regulators";
59			ldo1-supply = <&v3v3>;
60			ldo2-supply = <&v3v3>;
61			ldo3-supply = <&vdd_ddr>;
62			ldo5-supply = <&v3v3>;
63			ldo6-supply = <&v3v3>;
64			pwr_sw1-supply = <&bst_out>;
65			pwr_sw2-supply = <&bst_out>;
66
67			vddcore: buck1 {
68				regulator-name = "vddcore";
69				regulator-min-microvolt = <1200000>;
70				regulator-max-microvolt = <1350000>;
71				regulator-always-on;
72				regulator-initial-mode = <0>;
73				regulator-over-current-protection;
74			};
75
76			vdd_ddr: buck2 {
77				regulator-name = "vdd_ddr";
78				regulator-min-microvolt = <1350000>;
79				regulator-max-microvolt = <1350000>;
80				regulator-always-on;
81				regulator-initial-mode = <0>;
82				regulator-over-current-protection;
83			};
84
85			vdd: buck3 {
86				regulator-name = "vdd";
87				regulator-min-microvolt = <3300000>;
88				regulator-max-microvolt = <3300000>;
89				regulator-always-on;
90				st,mask-reset;
91				regulator-initial-mode = <0>;
92				regulator-over-current-protection;
93			};
94
95			v3v3: buck4 {
96				regulator-name = "v3v3";
97				regulator-min-microvolt = <3300000>;
98				regulator-max-microvolt = <3300000>;
99				regulator-always-on;
100				regulator-over-current-protection;
101				regulator-initial-mode = <0>;
102			};
103
104			vdda: ldo1 {
105				regulator-name = "vdda";
106				regulator-min-microvolt = <2900000>;
107				regulator-max-microvolt = <2900000>;
108			};
109
110			v2v8: ldo2 {
111				regulator-name = "v2v8";
112				regulator-min-microvolt = <2800000>;
113				regulator-max-microvolt = <2800000>;
114			};
115
116			vtt_ddr: ldo3 {
117				regulator-name = "vtt_ddr";
118				regulator-min-microvolt = <500000>;
119				regulator-max-microvolt = <750000>;
120				regulator-always-on;
121				regulator-over-current-protection;
122			};
123
124			vdd_usb: ldo4 {
125				regulator-name = "vdd_usb";
126				regulator-min-microvolt = <3300000>;
127				regulator-max-microvolt = <3300000>;
128			};
129
130			vdd_sd: ldo5 {
131				regulator-name = "vdd_sd";
132				regulator-min-microvolt = <2900000>;
133				regulator-max-microvolt = <2900000>;
134				regulator-boot-on;
135			};
136
137			v1v8: ldo6 {
138				regulator-name = "v1v8";
139				regulator-min-microvolt = <1800000>;
140				regulator-max-microvolt = <1800000>;
141			};
142
143			vref_ddr: vref_ddr {
144				regulator-name = "vref_ddr";
145				regulator-always-on;
146				regulator-over-current-protection;
147			};
148
149			bst_out: boost {
150				regulator-name = "bst_out";
151			};
152
153			vbus_otg: pwr_sw1 {
154				regulator-name = "vbus_otg";
155			};
156
157			vbus_sw: pwr_sw2 {
158				regulator-name = "vbus_sw";
159				regulator-active-discharge = <1>;
160			};
161		};
162	};
163};
164
165&iwdg2 {
166	timeout-sec = <32>;
167	status = "okay";
168	secure-status = "okay";
169};
170
171&pwr_regulators {
172	vdd-supply = <&vdd>;
173	vdd_3v3_usbfs-supply = <&vdd_usb>;
174};
175
176&rcc {
177	secure-status = "disabled";
178	st,clksrc = <
179		CLK_MPU_PLL1P
180		CLK_AXI_PLL2P
181		CLK_MCU_PLL3P
182		CLK_PLL12_HSE
183		CLK_PLL3_HSE
184		CLK_PLL4_HSE
185		CLK_RTC_LSE
186		CLK_MCO1_DISABLED
187		CLK_MCO2_DISABLED
188	>;
189
190	st,clkdiv = <
191		1 /*MPU*/
192		0 /*AXI*/
193		0 /*MCU*/
194		1 /*APB1*/
195		1 /*APB2*/
196		1 /*APB3*/
197		1 /*APB4*/
198		2 /*APB5*/
199		23 /*RTC*/
200		0 /*MCO1*/
201		0 /*MCO2*/
202	>;
203
204	st,pkcs = <
205		CLK_CKPER_HSE
206		CLK_FMC_ACLK
207		CLK_QSPI_ACLK
208		CLK_ETH_DISABLED
209		CLK_SDMMC12_PLL4P
210		CLK_DSI_DSIPLL
211		CLK_STGEN_HSE
212		CLK_USBPHY_HSE
213		CLK_SPI2S1_PLL3Q
214		CLK_SPI2S23_PLL3Q
215		CLK_SPI45_HSI
216		CLK_SPI6_HSI
217		CLK_I2C46_HSI
218		CLK_SDMMC3_PLL4P
219		CLK_USBO_USBPHY
220		CLK_ADC_CKPER
221		CLK_CEC_LSE
222		CLK_I2C12_HSI
223		CLK_I2C35_HSI
224		CLK_UART1_HSI
225		CLK_UART24_HSI
226		CLK_UART35_HSI
227		CLK_UART6_HSI
228		CLK_UART78_HSI
229		CLK_SPDIF_PLL4P
230		CLK_FDCAN_PLL4R
231		CLK_SAI1_PLL3Q
232		CLK_SAI2_PLL3Q
233		CLK_SAI3_PLL3Q
234		CLK_SAI4_PLL3Q
235		CLK_RNG1_LSI
236		CLK_RNG2_LSI
237		CLK_LPTIM1_PCLK1
238		CLK_LPTIM23_PCLK3
239		CLK_LPTIM45_LSE
240	>;
241
242	/* VCO = 1300.0 MHz => P = 650 (CPU) */
243	pll1: st,pll@0 {
244		compatible = "st,stm32mp1-pll";
245		reg = <0>;
246		cfg = <2 80 0 0 0 PQR(1,0,0)>;
247		frac = <0x800>;
248	};
249
250	/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
251	pll2: st,pll@1 {
252		compatible = "st,stm32mp1-pll";
253		reg = <1>;
254		cfg = <2 65 1 0 0 PQR(1,1,1)>;
255		frac = <0x1400>;
256	};
257
258	/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
259	pll3: st,pll@2 {
260		compatible = "st,stm32mp1-pll";
261		reg = <2>;
262		cfg = <1 33 1 16 36 PQR(1,1,1)>;
263		frac = <0x1a04>;
264	};
265
266	/* VCO = 480.0 MHz => P = 120, Q = 40, R = 96 */
267	pll4: st,pll@3 {
268		compatible = "st,stm32mp1-pll";
269		reg = <3>;
270		cfg = <1 39 3 11 4 PQR(1,1,1)>;
271	};
272};
273
274&rng1 {
275	status = "okay";
276};
277
278&rtc {
279	status = "okay";
280};
281
282&sdmmc1 {
283	pinctrl-names = "default";
284	pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
285	st,sig-dir;
286	st,neg-edge;
287	st,use-ckin;
288	bus-width = <4>;
289	vmmc-supply = <&vdd_sd>;
290	status = "okay";
291};
292
293&uart4 {
294	/* On Low speed expansion header */
295	label = "LS-UART1";
296	pinctrl-names = "default";
297	pinctrl-0 = <&uart4_pins_b>;
298	status = "okay";
299};
300
301&uart7 {
302	/* On Low speed expansion header */
303	label = "LS-UART0";
304	pinctrl-names = "default";
305	pinctrl-0 = <&uart7_pins_a>;
306	status = "okay";
307};
308