1/* 2 * Copyright (c) 2019-2021, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <neoverse_v1.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13 14/* Hardware handled coherency */ 15#if HW_ASSISTED_COHERENCY == 0 16#error "Neoverse V1 must be compiled with HW_ASSISTED_COHERENCY enabled" 17#endif 18 19/* 64-bit only core */ 20#if CTX_INCLUDE_AARCH32_REGS == 1 21#error "Neoverse-V1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 22#endif 23 24 /* -------------------------------------------------- 25 * Errata Workaround for Neoverse V1 Errata #1774420. 26 * This applies to revisions r0p0 and r1p0, fixed in r1p1. 27 * x0: variant[4:7] and revision[0:3] of current cpu. 28 * Shall clobber: x0-x17 29 * -------------------------------------------------- 30 */ 31func errata_neoverse_v1_1774420_wa 32 /* Check workaround compatibility. */ 33 mov x17, x30 34 bl check_errata_1774420 35 cbz x0, 1f 36 37 /* Set bit 53 in CPUECTLR_EL1 */ 38 mrs x1, NEOVERSE_V1_CPUECTLR_EL1 39 orr x1, x1, #NEOVERSE_V1_CPUECTLR_EL1_BIT_53 40 msr NEOVERSE_V1_CPUECTLR_EL1, x1 41 isb 421: 43 ret x17 44endfunc errata_neoverse_v1_1774420_wa 45 46func check_errata_1774420 47 /* Applies to r0p0 and r1p0. */ 48 mov x1, #0x10 49 b cpu_rev_var_ls 50endfunc check_errata_1774420 51 52 /* -------------------------------------------------- 53 * Errata Workaround for Neoverse V1 Errata #1791573. 54 * This applies to revisions r0p0 and r1p0, fixed in r1p1. 55 * x0: variant[4:7] and revision[0:3] of current cpu. 56 * Shall clobber: x0-x17 57 * -------------------------------------------------- 58 */ 59func errata_neoverse_v1_1791573_wa 60 /* Check workaround compatibility. */ 61 mov x17, x30 62 bl check_errata_1791573 63 cbz x0, 1f 64 65 /* Set bit 2 in ACTLR2_EL1 */ 66 mrs x1, NEOVERSE_V1_ACTLR2_EL1 67 orr x1, x1, #NEOVERSE_V1_ACTLR2_EL1_BIT_2 68 msr NEOVERSE_V1_ACTLR2_EL1, x1 69 isb 701: 71 ret x17 72endfunc errata_neoverse_v1_1791573_wa 73 74func check_errata_1791573 75 /* Applies to r0p0 and r1p0. */ 76 mov x1, #0x10 77 b cpu_rev_var_ls 78endfunc check_errata_1791573 79 80 /* -------------------------------------------------- 81 * Errata Workaround for Neoverse V1 Errata #1852267. 82 * This applies to revisions r0p0 and r1p0, fixed in r1p1. 83 * x0: variant[4:7] and revision[0:3] of current cpu. 84 * Shall clobber: x0-x17 85 * -------------------------------------------------- 86 */ 87func errata_neoverse_v1_1852267_wa 88 /* Check workaround compatibility. */ 89 mov x17, x30 90 bl check_errata_1852267 91 cbz x0, 1f 92 93 /* Set bit 28 in ACTLR2_EL1 */ 94 mrs x1, NEOVERSE_V1_ACTLR2_EL1 95 orr x1, x1, #NEOVERSE_V1_ACTLR2_EL1_BIT_28 96 msr NEOVERSE_V1_ACTLR2_EL1, x1 97 isb 981: 99 ret x17 100endfunc errata_neoverse_v1_1852267_wa 101 102func check_errata_1852267 103 /* Applies to r0p0 and r1p0. */ 104 mov x1, #0x10 105 b cpu_rev_var_ls 106endfunc check_errata_1852267 107 108 /* -------------------------------------------------- 109 * Errata Workaround for Neoverse V1 Errata #1925756. 110 * This applies to revisions <= r1p1. 111 * x0: variant[4:7] and revision[0:3] of current cpu. 112 * Shall clobber: x0-x17 113 * -------------------------------------------------- 114 */ 115func errata_neoverse_v1_1925756_wa 116 /* Check workaround compatibility. */ 117 mov x17, x30 118 bl check_errata_1925756 119 cbz x0, 1f 120 121 /* Set bit 8 in CPUECTLR_EL1 */ 122 mrs x1, NEOVERSE_V1_CPUECTLR_EL1 123 orr x1, x1, #NEOVERSE_V1_CPUECTLR_EL1_BIT_8 124 msr NEOVERSE_V1_CPUECTLR_EL1, x1 125 isb 1261: 127 ret x17 128endfunc errata_neoverse_v1_1925756_wa 129 130func check_errata_1925756 131 /* Applies to <= r1p1. */ 132 mov x1, #0x11 133 b cpu_rev_var_ls 134endfunc check_errata_1925756 135 136 /* -------------------------------------------------- 137 * Errata Workaround for Neoverse V1 Erratum #1940577 138 * This applies to revisions r1p0 - r1p1 and is open. 139 * It also exists in r0p0 but there is no fix in that 140 * revision. 141 * Inputs: 142 * x0: variant[4:7] and revision[0:3] of current cpu. 143 * Shall clobber: x0-x17 144 * -------------------------------------------------- 145 */ 146func errata_neoverse_v1_1940577_wa 147 /* Compare x0 against revisions r1p0 - r1p1 */ 148 mov x17, x30 149 bl check_errata_1940577 150 cbz x0, 1f 151 152 mov x0, #0 153 msr S3_6_C15_C8_0, x0 154 ldr x0, =0x10E3900002 155 msr S3_6_C15_C8_2, x0 156 ldr x0, =0x10FFF00083 157 msr S3_6_C15_C8_3, x0 158 ldr x0, =0x2001003FF 159 msr S3_6_C15_C8_1, x0 160 161 mov x0, #1 162 msr S3_6_C15_C8_0, x0 163 ldr x0, =0x10E3800082 164 msr S3_6_C15_C8_2, x0 165 ldr x0, =0x10FFF00083 166 msr S3_6_C15_C8_3, x0 167 ldr x0, =0x2001003FF 168 msr S3_6_C15_C8_1, x0 169 170 mov x0, #2 171 msr S3_6_C15_C8_0, x0 172 ldr x0, =0x10E3800200 173 msr S3_6_C15_C8_2, x0 174 ldr x0, =0x10FFF003E0 175 msr S3_6_C15_C8_3, x0 176 ldr x0, =0x2001003FF 177 msr S3_6_C15_C8_1, x0 178 179 isb 1801: 181 ret x17 182endfunc errata_neoverse_v1_1940577_wa 183 184func check_errata_1940577 185 /* Applies to revisions r1p0 - r1p1. */ 186 mov x1, #0x10 187 mov x2, #0x11 188 b cpu_rev_var_range 189endfunc check_errata_1940577 190 191 /* -------------------------------------------------- 192 * Errata Workaround for Neoverse V1 Errata #1966096 193 * This applies to revisions r1p0 - r1p1 and is open. 194 * It also exists in r0p0 but there is no workaround 195 * for that revision. 196 * x0: variant[4:7] and revision[0:3] of current cpu. 197 * Shall clobber: x0-x17 198 * -------------------------------------------------- 199 */ 200func errata_neoverse_v1_1966096_wa 201 /* Check workaround compatibility. */ 202 mov x17, x30 203 bl check_errata_1966096 204 cbz x0, 1f 205 206 /* Apply the workaround. */ 207 mov x0, #0x3 208 msr S3_6_C15_C8_0, x0 209 ldr x0, =0xEE010F12 210 msr S3_6_C15_C8_2, x0 211 ldr x0, =0xFFFF0FFF 212 msr S3_6_C15_C8_3, x0 213 ldr x0, =0x80000000003FF 214 msr S3_6_C15_C8_1, x0 215 isb 216 2171: 218 ret x17 219endfunc errata_neoverse_v1_1966096_wa 220 221func check_errata_1966096 222 mov x1, #0x10 223 mov x2, #0x11 224 b cpu_rev_var_range 225endfunc check_errata_1966096 226 227 /* -------------------------------------------------- 228 * Errata Workaround for Neoverse V1 Errata #2139242. 229 * This applies to revisions r0p0, r1p0, and r1p1, it 230 * is still open. 231 * x0: variant[4:7] and revision[0:3] of current cpu. 232 * Shall clobber: x0-x17 233 * -------------------------------------------------- 234 */ 235func errata_neoverse_v1_2139242_wa 236 /* Check workaround compatibility. */ 237 mov x17, x30 238 bl check_errata_2139242 239 cbz x0, 1f 240 241 /* Apply the workaround. */ 242 mov x0, #0x3 243 msr S3_6_C15_C8_0, x0 244 ldr x0, =0xEE720F14 245 msr S3_6_C15_C8_2, x0 246 ldr x0, =0xFFFF0FDF 247 msr S3_6_C15_C8_3, x0 248 ldr x0, =0x40000005003FF 249 msr S3_6_C15_C8_1, x0 250 isb 251 2521: 253 ret x17 254endfunc errata_neoverse_v1_2139242_wa 255 256func check_errata_2139242 257 /* Applies to r0p0, r1p0, r1p1 */ 258 mov x1, #0x11 259 b cpu_rev_var_ls 260endfunc check_errata_2139242 261 262 /* -------------------------------------------------- 263 * Errata Workaround for Neoverse V1 Errata #2108267. 264 * This applies to revisions r0p0, r1p0, and r1p1, it 265 * is still open. 266 * x0: variant[4:7] and revision[0:3] of current cpu. 267 * Shall clobber: x0-x1, x17 268 * -------------------------------------------------- 269 */ 270func errata_neoverse_v1_2108267_wa 271 /* Check workaround compatibility. */ 272 mov x17, x30 273 bl check_errata_2108267 274 cbz x0, 1f 275 276 /* Apply the workaround. */ 277 mrs x1, NEOVERSE_V1_CPUECTLR_EL1 278 mov x0, #NEOVERSE_V1_CPUECTLR_EL1_PF_MODE_CNSRV 279 bfi x1, x0, #CPUECTLR_EL1_PF_MODE_LSB, #CPUECTLR_EL1_PF_MODE_WIDTH 280 msr NEOVERSE_V1_CPUECTLR_EL1, x1 2811: 282 ret x17 283endfunc errata_neoverse_v1_2108267_wa 284 285func check_errata_2108267 286 /* Applies to r0p0, r1p0, r1p1 */ 287 mov x1, #0x11 288 b cpu_rev_var_ls 289endfunc check_errata_2108267 290 291 /* -------------------------------------------------- 292 * Errata Workaround for Neoverse V1 Errata #2216392. 293 * This applies to revisions r1p0 and r1p1 and is 294 * still open. 295 * This issue is also present in r0p0 but there is no 296 * workaround in that revision. 297 * x0: variant[4:7] and revision[0:3] of current cpu. 298 * Shall clobber: x0-x17 299 * -------------------------------------------------- 300 */ 301func errata_neoverse_v1_2216392_wa 302 /* Check workaround compatibility. */ 303 mov x17, x30 304 bl check_errata_2216392 305 cbz x0, 1f 306 307 ldr x0, =0x5 308 msr S3_6_c15_c8_0, x0 /* CPUPSELR_EL3 */ 309 ldr x0, =0x10F600E000 310 msr S3_6_c15_c8_2, x0 /* CPUPOR_EL3 */ 311 ldr x0, =0x10FF80E000 312 msr S3_6_c15_c8_3, x0 /* CPUPMR_EL3 */ 313 ldr x0, =0x80000000003FF 314 msr S3_6_c15_c8_1, x0 /* CPUPCR_EL3 */ 315 316 isb 3171: 318 ret x17 319endfunc errata_neoverse_v1_2216392_wa 320 321func check_errata_2216392 322 /* Applies to revisions r1p0 and r1p1. */ 323 mov x1, #CPU_REV(1, 0) 324 mov x2, #CPU_REV(1, 1) 325 b cpu_rev_var_range 326endfunc check_errata_2216392 327 328 /* --------------------------------------------- 329 * HW will do the cache maintenance while powering down 330 * --------------------------------------------- 331 */ 332func neoverse_v1_core_pwr_dwn 333 /* --------------------------------------------- 334 * Enable CPU power down bit in power control register 335 * --------------------------------------------- 336 */ 337 mrs x0, NEOVERSE_V1_CPUPWRCTLR_EL1 338 orr x0, x0, #NEOVERSE_V1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 339 msr NEOVERSE_V1_CPUPWRCTLR_EL1, x0 340 isb 341 ret 342endfunc neoverse_v1_core_pwr_dwn 343 344 /* 345 * Errata printing function for Neoverse V1. Must follow AAPCS. 346 */ 347#if REPORT_ERRATA 348func neoverse_v1_errata_report 349 stp x8, x30, [sp, #-16]! 350 351 bl cpu_get_rev_var 352 mov x8, x0 353 354 /* 355 * Report all errata. The revision-variant information is passed to 356 * checking functions of each errata. 357 */ 358 report_errata ERRATA_V1_1774420, neoverse_v1, 1774420 359 report_errata ERRATA_V1_1791573, neoverse_v1, 1791573 360 report_errata ERRATA_V1_1852267, neoverse_v1, 1852267 361 report_errata ERRATA_V1_1925756, neoverse_v1, 1925756 362 report_errata ERRATA_V1_1940577, neoverse_v1, 1940577 363 report_errata ERRATA_V1_1966096, neoverse_v1, 1966096 364 report_errata ERRATA_V1_2139242, neoverse_v1, 2139242 365 report_errata ERRATA_V1_2108267, neoverse_v1, 2108267 366 report_errata ERRATA_V1_2216392, neoverse_v1, 2216392 367 368 ldp x8, x30, [sp], #16 369 ret 370endfunc neoverse_v1_errata_report 371#endif 372 373func neoverse_v1_reset_func 374 mov x19, x30 375 376 /* Disable speculative loads */ 377 msr SSBS, xzr 378 isb 379 380#if ERRATA_V1_1774420 381 mov x0, x18 382 bl errata_neoverse_v1_1774420_wa 383#endif 384 385#if ERRATA_V1_1791573 386 mov x0, x18 387 bl errata_neoverse_v1_1791573_wa 388#endif 389 390#if ERRATA_V1_1852267 391 mov x0, x18 392 bl errata_neoverse_v1_1852267_wa 393#endif 394 395#if ERRATA_V1_1925756 396 mov x0, x18 397 bl errata_neoverse_v1_1925756_wa 398#endif 399 400#if ERRATA_V1_1940577 401 mov x0, x18 402 bl errata_neoverse_v1_1940577_wa 403#endif 404 405#if ERRATA_V1_1966096 406 mov x0, x18 407 bl errata_neoverse_v1_1966096_wa 408#endif 409 410#if ERRATA_V1_2139242 411 mov x0, x18 412 bl errata_neoverse_v1_2139242_wa 413#endif 414 415#if ERRATA_V1_2108267 416 mov x0, x18 417 bl errata_neoverse_v1_2108267_wa 418#endif 419 420#if ERRATA_V1_2216392 421 mov x0, x18 422 bl errata_neoverse_v1_2216392_wa 423#endif 424 425 ret x19 426endfunc neoverse_v1_reset_func 427 428 /* --------------------------------------------- 429 * This function provides Neoverse-V1 specific 430 * register information for crash reporting. 431 * It needs to return with x6 pointing to 432 * a list of register names in ascii and 433 * x8 - x15 having values of registers to be 434 * reported. 435 * --------------------------------------------- 436 */ 437.section .rodata.neoverse_v1_regs, "aS" 438neoverse_v1_regs: /* The ascii list of register names to be reported */ 439 .asciz "cpuectlr_el1", "" 440 441func neoverse_v1_cpu_reg_dump 442 adr x6, neoverse_v1_regs 443 mrs x8, NEOVERSE_V1_CPUECTLR_EL1 444 ret 445endfunc neoverse_v1_cpu_reg_dump 446 447declare_cpu_ops neoverse_v1, NEOVERSE_V1_MIDR, \ 448 neoverse_v1_reset_func, \ 449 neoverse_v1_core_pwr_dwn 450