1 /*
2 * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <errno.h>
8
9 #include <common/debug.h>
10 #include <lib/mmio.h>
11 #include <lib/xlat_tables/xlat_tables_v2.h>
12
13 #include <sunxi_def.h>
14 #include <sunxi_mmap.h>
15 #include <sunxi_private.h>
16
17 static const mmap_region_t sunxi_mmap[MAX_STATIC_MMAP_REGIONS + 1] = {
18 MAP_REGION_FLAT(SUNXI_SRAM_BASE, SUNXI_SRAM_SIZE,
19 MT_DEVICE | MT_RW | MT_SECURE | MT_EXECUTE_NEVER),
20 MAP_REGION_FLAT(SUNXI_DEV_BASE, SUNXI_DEV_SIZE,
21 MT_DEVICE | MT_RW | MT_SECURE | MT_EXECUTE_NEVER),
22 MAP_REGION(PRELOADED_BL33_BASE, SUNXI_BL33_VIRT_BASE,
23 SUNXI_DRAM_MAP_SIZE, MT_RW_DATA | MT_NS),
24 {},
25 };
26
plat_get_syscnt_freq2(void)27 unsigned int plat_get_syscnt_freq2(void)
28 {
29 return SUNXI_OSC24M_CLK_IN_HZ;
30 }
31
sunxi_configure_mmu_el3(int flags)32 void sunxi_configure_mmu_el3(int flags)
33 {
34 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE,
35 BL_CODE_END - BL_CODE_BASE,
36 MT_CODE | MT_SECURE);
37 mmap_add_region(BL_CODE_END, BL_CODE_END,
38 BL_END - BL_CODE_END,
39 MT_RW_DATA | MT_SECURE);
40 #if SEPARATE_CODE_AND_RODATA
41 mmap_add_region(BL_RO_DATA_BASE, BL_RO_DATA_BASE,
42 BL_RO_DATA_END - BL_RO_DATA_BASE,
43 MT_RO_DATA | MT_SECURE);
44 #endif
45 #if SEPARATE_NOBITS_REGION
46 mmap_add_region(BL_NOBITS_BASE, BL_NOBITS_BASE,
47 BL_NOBITS_END - BL_NOBITS_BASE,
48 MT_RW_DATA | MT_SECURE);
49 #endif
50 #if USE_COHERENT_MEM
51 mmap_add_region(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_BASE,
52 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE,
53 MT_DEVICE | MT_RW | MT_SECURE | MT_EXECUTE_NEVER);
54 #endif
55
56 mmap_add(sunxi_mmap);
57 init_xlat_tables();
58
59 enable_mmu_el3(0);
60 }
61
62 #define SRAM_VER_REG (SUNXI_SYSCON_BASE + 0x24)
sunxi_read_soc_id(void)63 uint16_t sunxi_read_soc_id(void)
64 {
65 uint32_t reg = mmio_read_32(SRAM_VER_REG);
66
67 /* Set bit 15 to prepare for the SOCID read. */
68 mmio_write_32(SRAM_VER_REG, reg | BIT(15));
69
70 reg = mmio_read_32(SRAM_VER_REG);
71
72 /* deactivate the SOCID access again */
73 mmio_write_32(SRAM_VER_REG, reg & ~BIT(15));
74
75 return reg >> 16;
76 }
77
78 /*
79 * Configure a given pin to the GPIO-OUT function and sets its level.
80 * The port is given as a capital letter, the pin is the number within
81 * this port group.
82 * So to set pin PC7 to high, use: sunxi_set_gpio_out('C', 7, true);
83 */
sunxi_set_gpio_out(char port,int pin,bool level_high)84 void sunxi_set_gpio_out(char port, int pin, bool level_high)
85 {
86 uintptr_t port_base;
87
88 if (port < 'A' || port > 'L')
89 return;
90 if (port == 'L')
91 port_base = SUNXI_R_PIO_BASE;
92 else
93 port_base = SUNXI_PIO_BASE + (port - 'A') * 0x24;
94
95 /* Set the new level first before configuring the pin. */
96 if (level_high)
97 mmio_setbits_32(port_base + 0x10, BIT(pin));
98 else
99 mmio_clrbits_32(port_base + 0x10, BIT(pin));
100
101 /* configure pin as GPIO out (4(3) bits per pin, 1: GPIO out */
102 mmio_clrsetbits_32(port_base + (pin / 8) * 4,
103 0x7 << ((pin % 8) * 4),
104 0x1 << ((pin % 8) * 4));
105 }
106
sunxi_init_platform_r_twi(uint16_t socid,bool use_rsb)107 int sunxi_init_platform_r_twi(uint16_t socid, bool use_rsb)
108 {
109 uint32_t pin_func = 0x77;
110 uint32_t device_bit;
111 unsigned int reset_offset = 0xb0;
112
113 switch (socid) {
114 case SUNXI_SOC_H5:
115 if (use_rsb)
116 return -ENODEV;
117 pin_func = 0x22;
118 device_bit = BIT(6);
119 break;
120 case SUNXI_SOC_H6:
121 case SUNXI_SOC_H616:
122 pin_func = use_rsb ? 0x22 : 0x33;
123 device_bit = BIT(16);
124 reset_offset = use_rsb ? 0x1bc : 0x19c;
125 break;
126 case SUNXI_SOC_A64:
127 pin_func = use_rsb ? 0x22 : 0x33;
128 device_bit = use_rsb ? BIT(3) : BIT(6);
129 break;
130 default:
131 INFO("R_I2C/RSB on Allwinner 0x%x SoC not supported\n", socid);
132 return -ENODEV;
133 }
134
135 /* un-gate R_PIO clock */
136 if (socid != SUNXI_SOC_H6 && socid != SUNXI_SOC_H616)
137 mmio_setbits_32(SUNXI_R_PRCM_BASE + 0x28, BIT(0));
138
139 /* switch pins PL0 and PL1 to the desired function */
140 mmio_clrsetbits_32(SUNXI_R_PIO_BASE + 0x00, 0xffU, pin_func);
141
142 /* level 2 drive strength */
143 mmio_clrsetbits_32(SUNXI_R_PIO_BASE + 0x14, 0x0fU, 0xaU);
144
145 /* set both pins to pull-up */
146 mmio_clrsetbits_32(SUNXI_R_PIO_BASE + 0x1c, 0x0fU, 0x5U);
147
148 /* un-gate clock */
149 if (socid != SUNXI_SOC_H6 && socid != SUNXI_SOC_H616)
150 mmio_setbits_32(SUNXI_R_PRCM_BASE + 0x28, device_bit);
151 else
152 mmio_setbits_32(SUNXI_R_PRCM_BASE + reset_offset, BIT(0));
153
154 /* assert, then de-assert reset of I2C/RSB controller */
155 mmio_clrbits_32(SUNXI_R_PRCM_BASE + reset_offset, device_bit);
156 mmio_setbits_32(SUNXI_R_PRCM_BASE + reset_offset, device_bit);
157
158 return 0;
159 }
160