1 /*
2 * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8
9 #include <common/debug.h>
10 #include <drivers/arm/cci.h>
11 #include <drivers/arm/ccn.h>
12 #include <drivers/arm/gicv2.h>
13 #include <drivers/arm/sp804_delay_timer.h>
14 #include <drivers/generic_delay_timer.h>
15 #include <lib/mmio.h>
16 #include <lib/smccc.h>
17 #include <lib/xlat_tables/xlat_tables_compat.h>
18 #include <platform_def.h>
19 #include <services/arm_arch_svc.h>
20 #if SPM_MM
21 #include <services/spm_mm_partition.h>
22 #endif
23
24 #include <plat/arm/common/arm_config.h>
25 #include <plat/arm/common/plat_arm.h>
26 #include <plat/common/platform.h>
27
28 #include "fvp_private.h"
29
30 /* Defines for GIC Driver build time selection */
31 #define FVP_GICV2 1
32 #define FVP_GICV3 2
33
34 /*******************************************************************************
35 * arm_config holds the characteristics of the differences between the three FVP
36 * platforms (Base, A53_A57 & Foundation). It will be populated during cold boot
37 * at each boot stage by the primary before enabling the MMU (to allow
38 * interconnect configuration) & used thereafter. Each BL will have its own copy
39 * to allow independent operation.
40 ******************************************************************************/
41 arm_config_t arm_config;
42
43 #define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \
44 DEVICE0_SIZE, \
45 MT_DEVICE | MT_RW | MT_SECURE)
46
47 #define MAP_DEVICE1 MAP_REGION_FLAT(DEVICE1_BASE, \
48 DEVICE1_SIZE, \
49 MT_DEVICE | MT_RW | MT_SECURE)
50
51 #if FVP_GICR_REGION_PROTECTION
52 #define MAP_GICD_MEM MAP_REGION_FLAT(BASE_GICD_BASE, \
53 BASE_GICD_SIZE, \
54 MT_DEVICE | MT_RW | MT_SECURE)
55
56 /* Map all core's redistributor memory as read-only. After boots up,
57 * per-core map its redistributor memory as read-write */
58 #define MAP_GICR_MEM MAP_REGION_FLAT(BASE_GICR_BASE, \
59 (BASE_GICR_SIZE * PLATFORM_CORE_COUNT),\
60 MT_DEVICE | MT_RO | MT_SECURE)
61 #endif /* FVP_GICR_REGION_PROTECTION */
62
63 /*
64 * Need to be mapped with write permissions in order to set a new non-volatile
65 * counter value.
66 */
67 #define MAP_DEVICE2 MAP_REGION_FLAT(DEVICE2_BASE, \
68 DEVICE2_SIZE, \
69 MT_DEVICE | MT_RW | MT_SECURE)
70
71 /*
72 * Table of memory regions for various BL stages to map using the MMU.
73 * This doesn't include Trusted SRAM as setup_page_tables() already takes care
74 * of mapping it.
75 */
76 #ifdef IMAGE_BL1
77 const mmap_region_t plat_arm_mmap[] = {
78 ARM_MAP_SHARED_RAM,
79 V2M_MAP_FLASH0_RO,
80 V2M_MAP_IOFPGA,
81 MAP_DEVICE0,
82 #if FVP_INTERCONNECT_DRIVER == FVP_CCN
83 MAP_DEVICE1,
84 #endif
85 #if TRUSTED_BOARD_BOOT
86 /* To access the Root of Trust Public Key registers. */
87 MAP_DEVICE2,
88 /* Map DRAM to authenticate NS_BL2U image. */
89 ARM_MAP_NS_DRAM1,
90 #endif
91 {0}
92 };
93 #endif
94 #ifdef IMAGE_BL2
95 const mmap_region_t plat_arm_mmap[] = {
96 ARM_MAP_SHARED_RAM,
97 V2M_MAP_FLASH0_RW,
98 V2M_MAP_IOFPGA,
99 MAP_DEVICE0,
100 #if FVP_INTERCONNECT_DRIVER == FVP_CCN
101 MAP_DEVICE1,
102 #endif
103 ARM_MAP_NS_DRAM1,
104 #ifdef __aarch64__
105 ARM_MAP_DRAM2,
106 #endif
107 #if defined(SPD_spmd)
108 ARM_MAP_TRUSTED_DRAM,
109 #endif
110 #if ENABLE_RME
111 ARM_MAP_RMM_DRAM,
112 ARM_MAP_GPT_L1_DRAM,
113 #endif /* ENABLE_RME */
114 #ifdef SPD_tspd
115 ARM_MAP_TSP_SEC_MEM,
116 #endif
117 #if TRUSTED_BOARD_BOOT
118 /* To access the Root of Trust Public Key registers. */
119 MAP_DEVICE2,
120 #if !BL2_AT_EL3
121 ARM_MAP_BL1_RW,
122 #endif
123 #endif /* TRUSTED_BOARD_BOOT */
124 #if SPM_MM
125 ARM_SP_IMAGE_MMAP,
126 #endif
127 #if ARM_BL31_IN_DRAM
128 ARM_MAP_BL31_SEC_DRAM,
129 #endif
130 #ifdef SPD_opteed
131 ARM_MAP_OPTEE_CORE_MEM,
132 ARM_OPTEE_PAGEABLE_LOAD_MEM,
133 #endif
134 {0}
135 };
136 #endif
137 #ifdef IMAGE_BL2U
138 const mmap_region_t plat_arm_mmap[] = {
139 MAP_DEVICE0,
140 V2M_MAP_IOFPGA,
141 {0}
142 };
143 #endif
144 #ifdef IMAGE_BL31
145 const mmap_region_t plat_arm_mmap[] = {
146 ARM_MAP_SHARED_RAM,
147 #if USE_DEBUGFS
148 /* Required by devfip, can be removed if devfip is not used */
149 V2M_MAP_FLASH0_RW,
150 #endif /* USE_DEBUGFS */
151 ARM_MAP_EL3_TZC_DRAM,
152 V2M_MAP_IOFPGA,
153 MAP_DEVICE0,
154 #if FVP_GICR_REGION_PROTECTION
155 MAP_GICD_MEM,
156 MAP_GICR_MEM,
157 #else
158 MAP_DEVICE1,
159 #endif /* FVP_GICR_REGION_PROTECTION */
160 ARM_V2M_MAP_MEM_PROTECT,
161 #if SPM_MM
162 ARM_SPM_BUF_EL3_MMAP,
163 #endif
164 /* Required by fconf APIs to read HW_CONFIG dtb loaded into DRAM */
165 ARM_DTB_DRAM_NS,
166 #if ENABLE_RME
167 ARM_MAP_GPT_L1_DRAM,
168 #endif
169 {0}
170 };
171
172 #if defined(IMAGE_BL31) && SPM_MM
173 const mmap_region_t plat_arm_secure_partition_mmap[] = {
174 V2M_MAP_IOFPGA_EL0, /* for the UART */
175 MAP_REGION_FLAT(DEVICE0_BASE, \
176 DEVICE0_SIZE, \
177 MT_DEVICE | MT_RO | MT_SECURE | MT_USER),
178 ARM_SP_IMAGE_MMAP,
179 ARM_SP_IMAGE_NS_BUF_MMAP,
180 ARM_SP_IMAGE_RW_MMAP,
181 ARM_SPM_BUF_EL0_MMAP,
182 {0}
183 };
184 #endif
185 #endif
186 #ifdef IMAGE_BL32
187 const mmap_region_t plat_arm_mmap[] = {
188 #ifndef __aarch64__
189 ARM_MAP_SHARED_RAM,
190 ARM_V2M_MAP_MEM_PROTECT,
191 #endif
192 V2M_MAP_IOFPGA,
193 MAP_DEVICE0,
194 MAP_DEVICE1,
195 /* Required by fconf APIs to read HW_CONFIG dtb loaded into DRAM */
196 ARM_DTB_DRAM_NS,
197 {0}
198 };
199 #endif
200
201 #ifdef IMAGE_RMM
202 const mmap_region_t plat_arm_mmap[] = {
203 V2M_MAP_IOFPGA,
204 MAP_DEVICE0,
205 MAP_DEVICE1,
206 {0}
207 };
208 #endif
209
210 ARM_CASSERT_MMAP
211
212 #if FVP_INTERCONNECT_DRIVER != FVP_CCN
213 static const int fvp_cci400_map[] = {
214 PLAT_FVP_CCI400_CLUS0_SL_PORT,
215 PLAT_FVP_CCI400_CLUS1_SL_PORT,
216 };
217
218 static const int fvp_cci5xx_map[] = {
219 PLAT_FVP_CCI5XX_CLUS0_SL_PORT,
220 PLAT_FVP_CCI5XX_CLUS1_SL_PORT,
221 };
222
get_interconnect_master(void)223 static unsigned int get_interconnect_master(void)
224 {
225 unsigned int master;
226 u_register_t mpidr;
227
228 mpidr = read_mpidr_el1();
229 master = ((arm_config.flags & ARM_CONFIG_FVP_SHIFTED_AFF) != 0U) ?
230 MPIDR_AFFLVL2_VAL(mpidr) : MPIDR_AFFLVL1_VAL(mpidr);
231
232 assert(master < FVP_CLUSTER_COUNT);
233 return master;
234 }
235 #endif
236
237 #if defined(IMAGE_BL31) && SPM_MM
238 /*
239 * Boot information passed to a secure partition during initialisation. Linear
240 * indices in MP information will be filled at runtime.
241 */
242 static spm_mm_mp_info_t sp_mp_info[] = {
243 [0] = {0x80000000, 0},
244 [1] = {0x80000001, 0},
245 [2] = {0x80000002, 0},
246 [3] = {0x80000003, 0},
247 [4] = {0x80000100, 0},
248 [5] = {0x80000101, 0},
249 [6] = {0x80000102, 0},
250 [7] = {0x80000103, 0},
251 };
252
253 const spm_mm_boot_info_t plat_arm_secure_partition_boot_info = {
254 .h.type = PARAM_SP_IMAGE_BOOT_INFO,
255 .h.version = VERSION_1,
256 .h.size = sizeof(spm_mm_boot_info_t),
257 .h.attr = 0,
258 .sp_mem_base = ARM_SP_IMAGE_BASE,
259 .sp_mem_limit = ARM_SP_IMAGE_LIMIT,
260 .sp_image_base = ARM_SP_IMAGE_BASE,
261 .sp_stack_base = PLAT_SP_IMAGE_STACK_BASE,
262 .sp_heap_base = ARM_SP_IMAGE_HEAP_BASE,
263 .sp_ns_comm_buf_base = PLAT_SP_IMAGE_NS_BUF_BASE,
264 .sp_shared_buf_base = PLAT_SPM_BUF_BASE,
265 .sp_image_size = ARM_SP_IMAGE_SIZE,
266 .sp_pcpu_stack_size = PLAT_SP_IMAGE_STACK_PCPU_SIZE,
267 .sp_heap_size = ARM_SP_IMAGE_HEAP_SIZE,
268 .sp_ns_comm_buf_size = PLAT_SP_IMAGE_NS_BUF_SIZE,
269 .sp_shared_buf_size = PLAT_SPM_BUF_SIZE,
270 .num_sp_mem_regions = ARM_SP_IMAGE_NUM_MEM_REGIONS,
271 .num_cpus = PLATFORM_CORE_COUNT,
272 .mp_info = &sp_mp_info[0],
273 };
274
plat_get_secure_partition_mmap(void * cookie)275 const struct mmap_region *plat_get_secure_partition_mmap(void *cookie)
276 {
277 return plat_arm_secure_partition_mmap;
278 }
279
plat_get_secure_partition_boot_info(void * cookie)280 const struct spm_mm_boot_info *plat_get_secure_partition_boot_info(
281 void *cookie)
282 {
283 return &plat_arm_secure_partition_boot_info;
284 }
285 #endif
286
287 /*******************************************************************************
288 * A single boot loader stack is expected to work on both the Foundation FVP
289 * models and the two flavours of the Base FVP models (AEMv8 & Cortex). The
290 * SYS_ID register provides a mechanism for detecting the differences between
291 * these platforms. This information is stored in a per-BL array to allow the
292 * code to take the correct path.Per BL platform configuration.
293 ******************************************************************************/
fvp_config_setup(void)294 void __init fvp_config_setup(void)
295 {
296 unsigned int rev, hbi, bld, arch, sys_id;
297
298 sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_ID);
299 rev = (sys_id >> V2M_SYS_ID_REV_SHIFT) & V2M_SYS_ID_REV_MASK;
300 hbi = (sys_id >> V2M_SYS_ID_HBI_SHIFT) & V2M_SYS_ID_HBI_MASK;
301 bld = (sys_id >> V2M_SYS_ID_BLD_SHIFT) & V2M_SYS_ID_BLD_MASK;
302 arch = (sys_id >> V2M_SYS_ID_ARCH_SHIFT) & V2M_SYS_ID_ARCH_MASK;
303
304 if (arch != ARCH_MODEL) {
305 ERROR("This firmware is for FVP models\n");
306 panic();
307 }
308
309 /*
310 * The build field in the SYS_ID tells which variant of the GIC
311 * memory is implemented by the model.
312 */
313 switch (bld) {
314 case BLD_GIC_VE_MMAP:
315 ERROR("Legacy Versatile Express memory map for GIC peripheral"
316 " is not supported\n");
317 panic();
318 break;
319 case BLD_GIC_A53A57_MMAP:
320 break;
321 default:
322 ERROR("Unsupported board build %x\n", bld);
323 panic();
324 }
325
326 /*
327 * The hbi field in the SYS_ID is 0x020 for the Base FVP & 0x010
328 * for the Foundation FVP.
329 */
330 switch (hbi) {
331 case HBI_FOUNDATION_FVP:
332 arm_config.flags = 0;
333
334 /*
335 * Check for supported revisions of Foundation FVP
336 * Allow future revisions to run but emit warning diagnostic
337 */
338 switch (rev) {
339 case REV_FOUNDATION_FVP_V2_0:
340 case REV_FOUNDATION_FVP_V2_1:
341 case REV_FOUNDATION_FVP_v9_1:
342 case REV_FOUNDATION_FVP_v9_6:
343 break;
344 default:
345 WARN("Unrecognized Foundation FVP revision %x\n", rev);
346 break;
347 }
348 break;
349 case HBI_BASE_FVP:
350 arm_config.flags |= (ARM_CONFIG_BASE_MMAP | ARM_CONFIG_HAS_TZC);
351
352 /*
353 * Check for supported revisions
354 * Allow future revisions to run but emit warning diagnostic
355 */
356 switch (rev) {
357 case REV_BASE_FVP_V0:
358 arm_config.flags |= ARM_CONFIG_FVP_HAS_CCI400;
359 break;
360 case REV_BASE_FVP_REVC:
361 arm_config.flags |= (ARM_CONFIG_FVP_HAS_SMMUV3 |
362 ARM_CONFIG_FVP_HAS_CCI5XX);
363 break;
364 default:
365 WARN("Unrecognized Base FVP revision %x\n", rev);
366 break;
367 }
368 break;
369 default:
370 ERROR("Unsupported board HBI number 0x%x\n", hbi);
371 panic();
372 }
373
374 /*
375 * We assume that the presence of MT bit, and therefore shifted
376 * affinities, is uniform across the platform: either all CPUs, or no
377 * CPUs implement it.
378 */
379 if ((read_mpidr_el1() & MPIDR_MT_MASK) != 0U)
380 arm_config.flags |= ARM_CONFIG_FVP_SHIFTED_AFF;
381 }
382
383
fvp_interconnect_init(void)384 void __init fvp_interconnect_init(void)
385 {
386 #if FVP_INTERCONNECT_DRIVER == FVP_CCN
387 if (ccn_get_part0_id(PLAT_ARM_CCN_BASE) != CCN_502_PART0_ID) {
388 ERROR("Unrecognized CCN variant detected. Only CCN-502 is supported");
389 panic();
390 }
391
392 plat_arm_interconnect_init();
393 #else
394 uintptr_t cci_base = 0U;
395 const int *cci_map = NULL;
396 unsigned int map_size = 0U;
397
398 /* Initialize the right interconnect */
399 if ((arm_config.flags & ARM_CONFIG_FVP_HAS_CCI5XX) != 0U) {
400 cci_base = PLAT_FVP_CCI5XX_BASE;
401 cci_map = fvp_cci5xx_map;
402 map_size = ARRAY_SIZE(fvp_cci5xx_map);
403 } else if ((arm_config.flags & ARM_CONFIG_FVP_HAS_CCI400) != 0U) {
404 cci_base = PLAT_FVP_CCI400_BASE;
405 cci_map = fvp_cci400_map;
406 map_size = ARRAY_SIZE(fvp_cci400_map);
407 } else {
408 return;
409 }
410
411 assert(cci_base != 0U);
412 assert(cci_map != NULL);
413 cci_init(cci_base, cci_map, map_size);
414 #endif
415 }
416
fvp_interconnect_enable(void)417 void fvp_interconnect_enable(void)
418 {
419 #if FVP_INTERCONNECT_DRIVER == FVP_CCN
420 plat_arm_interconnect_enter_coherency();
421 #else
422 unsigned int master;
423
424 if ((arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 |
425 ARM_CONFIG_FVP_HAS_CCI5XX)) != 0U) {
426 master = get_interconnect_master();
427 cci_enable_snoop_dvm_reqs(master);
428 }
429 #endif
430 }
431
fvp_interconnect_disable(void)432 void fvp_interconnect_disable(void)
433 {
434 #if FVP_INTERCONNECT_DRIVER == FVP_CCN
435 plat_arm_interconnect_exit_coherency();
436 #else
437 unsigned int master;
438
439 if ((arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 |
440 ARM_CONFIG_FVP_HAS_CCI5XX)) != 0U) {
441 master = get_interconnect_master();
442 cci_disable_snoop_dvm_reqs(master);
443 }
444 #endif
445 }
446
447 #if TRUSTED_BOARD_BOOT
plat_get_mbedtls_heap(void ** heap_addr,size_t * heap_size)448 int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
449 {
450 assert(heap_addr != NULL);
451 assert(heap_size != NULL);
452
453 return arm_get_mbedtls_heap(heap_addr, heap_size);
454 }
455 #endif
456
fvp_timer_init(void)457 void fvp_timer_init(void)
458 {
459 #if USE_SP804_TIMER
460 /* Enable the clock override for SP804 timer 0, which means that no
461 * clock dividers are applied and the raw (35MHz) clock will be used.
462 */
463 mmio_write_32(V2M_SP810_BASE, FVP_SP810_CTRL_TIM0_OV);
464
465 /* Initialize delay timer driver using SP804 dual timer 0 */
466 sp804_timer_init(V2M_SP804_TIMER0_BASE,
467 SP804_TIMER_CLKMULT, SP804_TIMER_CLKDIV);
468 #else
469 generic_delay_timer_init();
470
471 /* Enable System level generic timer */
472 mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF,
473 CNTCR_FCREQ(0U) | CNTCR_EN);
474 #endif /* USE_SP804_TIMER */
475 }
476
477 /*****************************************************************************
478 * plat_is_smccc_feature_available() - This function checks whether SMCCC
479 * feature is availabile for platform.
480 * @fid: SMCCC function id
481 *
482 * Return SMC_ARCH_CALL_SUCCESS if SMCCC feature is available and
483 * SMC_ARCH_CALL_NOT_SUPPORTED otherwise.
484 *****************************************************************************/
plat_is_smccc_feature_available(u_register_t fid)485 int32_t plat_is_smccc_feature_available(u_register_t fid)
486 {
487 switch (fid) {
488 case SMCCC_ARCH_SOC_ID:
489 return SMC_ARCH_CALL_SUCCESS;
490 default:
491 return SMC_ARCH_CALL_NOT_SUPPORTED;
492 }
493 }
494
495 /* Get SOC version */
plat_get_soc_version(void)496 int32_t plat_get_soc_version(void)
497 {
498 return (int32_t)
499 (SOC_ID_SET_JEP_106(ARM_SOC_CONTINUATION_CODE,
500 ARM_SOC_IDENTIFICATION_CODE) |
501 (FVP_SOC_ID & SOC_ID_IMPL_DEF_MASK));
502 }
503
504 /* Get SOC revision */
plat_get_soc_revision(void)505 int32_t plat_get_soc_revision(void)
506 {
507 unsigned int sys_id;
508
509 sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_ID);
510 return (int32_t)(((sys_id >> V2M_SYS_ID_REV_SHIFT) &
511 V2M_SYS_ID_REV_MASK) & SOC_ID_REV_MASK);
512 }
513