1 /* 2 * Copyright 2021 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 #ifndef SOC_DEFAULT_BASE_ADDR_H 9 #define SOC_DEFAULT_BASE_ADDR_H 10 11 /* CCSR mmu_def.h */ 12 #define NXP_CCSR_ADDR 0x01000000 13 #define NXP_CCSR_SIZE 0x0F000000 14 15 #define NXP_DCSR_ADDR 0x20000000 16 #define NXP_DCSR_SIZE 0x4000000 17 18 /* Flex-SPI controller address */ 19 #define NXP_FLEXSPI_ADDR 0x020C0000 20 /* QSPI Flash Start address */ 21 #define NXP_QSPI_FLASH_ADDR 0x40000000 22 /* NOR Flash Start address */ 23 #define NXP_IFC_REGION_ADDR 0x60000000 24 #define NXP_NOR_FLASH_ADDR NXP_IFC_REGION_ADDR 25 26 /* MMU 500 soc.c*/ 27 #define NXP_SMMU_ADDR 0x09000000 28 29 #define NXP_SNVS_ADDR 0x01E90000 30 31 #define NXP_DCFG_ADDR 0x01EE0000 32 #define NXP_SFP_ADDR 0x01E80000 33 #define NXP_RCPM_ADDR 0x01EE2000 34 #define NXP_CSU_ADDR 0x01510000 35 #define NXP_SCFG_ADDR 0x01570000 36 #define NXP_DCSR_ADDR 0x20000000 37 #define NXP_DCSR_DCFG_ADDR (NXP_DCSR_ADDR + 0x00140000) 38 #define NXP_I2C_ADDR 0x02180000 39 #define NXP_ESDHC_ADDR 0x01560000 40 #define NXP_UART_ADDR 0x021C0500 41 #define NXP_UART1_ADDR 0x021C0600 42 43 #define NXP_GPIO1_ADDR 0x02300000 44 #define NXP_GPIO2_ADDR 0x02310000 45 #define NXP_GPIO3_ADDR 0x02320000 46 #define NXP_GPIO4_ADDR 0x02330000 47 48 #define NXP_WDOG1_NS_ADDR 0x02390000 49 #define NXP_WDOG2_NS_ADDR 0x023A0000 50 #define NXP_WDOG1_TZ_ADDR 0x023B0000 51 #define NXP_WDOG2_TZ_ADDR 0x023C0000 52 53 #define NXP_TIMER_STATUS_ADDR 0x023F0000 54 55 #define NXP_GICD_4K_ADDR 0x01401000 56 #define NXP_GICC_4K_ADDR 0x01402000 57 #define NXP_GICD_64K_ADDR 0x01410000 58 #define NXP_GICC_64K_ADDR 0x01420000 59 60 #define NXP_CAAM_ADDR 0x01700000 61 62 #define NXP_TZC_ADDR 0x01500000 63 #define NXP_DDR_ADDR 0x01080000 64 65 #define NXP_TIMER_ADDR 0x02B00000 66 #define NXP_CCI_ADDR 0x01180000 67 #define NXP_RESET_ADDR 0x01E60000 68 #define NXP_SEC_REGFILE_ADDR 0x01E88000 69 #endif /* SOC_DEFAULT_BASE_ADDR_H */ 70