1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2015 Freescale Semiconductor, Inc.
4 * Copyright 2019 NXP.
5 */
6
7 #include <common.h>
8 #include <clock_legacy.h>
9 #include <cpu_func.h>
10 #include <asm/global_data.h>
11 #include <linux/compiler.h>
12 #include <asm/io.h>
13 #include <asm/processor.h>
14 #include <asm/arch/clock.h>
15 #include <asm/arch/soc.h>
16 #include <fsl_ifc.h>
17 #include "cpu.h"
18
19 DECLARE_GLOBAL_DATA_PTR;
20
21 #ifndef CONFIG_SYS_FSL_NUM_CC_PLLS
22 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
23 #endif
24
get_sys_info(struct sys_info * sys_info)25 void get_sys_info(struct sys_info *sys_info)
26 {
27 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
28 /* rcw_tmp is needed to get FMAN clock, or to get cluster group A
29 * mux 2 clock for LS1043A/LS1046A.
30 */
31 #if defined(CONFIG_SYS_DPAA_FMAN) || \
32 defined(CONFIG_TARGET_LS1046ARDB) || \
33 defined(CONFIG_TARGET_LS1043ARDB)
34 u32 rcw_tmp;
35 #endif
36 struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_CLK_ADDR);
37 unsigned int cpu;
38 const u8 core_cplx_pll[8] = {
39 [0] = 0, /* CC1 PPL / 1 */
40 [1] = 0, /* CC1 PPL / 2 */
41 [4] = 1, /* CC2 PPL / 1 */
42 [5] = 1, /* CC2 PPL / 2 */
43 };
44
45 const u8 core_cplx_pll_div[8] = {
46 [0] = 1, /* CC1 PPL / 1 */
47 [1] = 2, /* CC1 PPL / 2 */
48 [4] = 1, /* CC2 PPL / 1 */
49 [5] = 2, /* CC2 PPL / 2 */
50 };
51
52 uint i, cluster;
53 uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
54 uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
55 unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
56 unsigned long cluster_clk;
57
58 sys_info->freq_systembus = sysclk;
59 #ifndef CONFIG_CLUSTER_CLK_FREQ
60 #define CONFIG_CLUSTER_CLK_FREQ CONFIG_SYS_CLK_FREQ
61 #endif
62 cluster_clk = CONFIG_CLUSTER_CLK_FREQ;
63
64 #ifdef CONFIG_DDR_CLK_FREQ
65 sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
66 #else
67 sys_info->freq_ddrbus = sysclk;
68 #endif
69
70 /* The freq_systembus is used to record frequency of platform PLL */
71 sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >>
72 FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
73 FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
74
75 #ifdef CONFIG_ARCH_LS1012A
76 sys_info->freq_ddrbus = 2 * sys_info->freq_systembus;
77 #else
78 sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
79 FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT) &
80 FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK;
81 #endif
82
83 for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
84 ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0xff;
85 if (ratio[i] > 4)
86 freq_c_pll[i] = cluster_clk * ratio[i];
87 else
88 freq_c_pll[i] = sys_info->freq_systembus * ratio[i];
89 }
90
91 for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
92 cluster = fsl_qoriq_core_to_cluster(cpu);
93 u32 c_pll_sel = (in_be32(&clk->clkcsr[cluster].clkcncsr) >> 27)
94 & 0xf;
95 u32 cplx_pll = core_cplx_pll[c_pll_sel];
96
97 sys_info->freq_processor[cpu] =
98 freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
99 }
100
101 #define HWA_CGA_M1_CLK_SEL 0xe0000000
102 #define HWA_CGA_M1_CLK_SHIFT 29
103 #ifdef CONFIG_SYS_DPAA_FMAN
104 rcw_tmp = in_be32(&gur->rcwsr[7]);
105 switch ((rcw_tmp & HWA_CGA_M1_CLK_SEL) >> HWA_CGA_M1_CLK_SHIFT) {
106 case 2:
107 sys_info->freq_fman[0] = freq_c_pll[0] / 2;
108 break;
109 case 3:
110 sys_info->freq_fman[0] = freq_c_pll[0] / 3;
111 break;
112 case 4:
113 sys_info->freq_fman[0] = freq_c_pll[0] / 4;
114 break;
115 case 5:
116 sys_info->freq_fman[0] = sys_info->freq_systembus;
117 break;
118 case 6:
119 sys_info->freq_fman[0] = freq_c_pll[1] / 2;
120 break;
121 case 7:
122 sys_info->freq_fman[0] = freq_c_pll[1] / 3;
123 break;
124 default:
125 printf("Error: Unknown FMan1 clock select!\n");
126 break;
127 }
128 #endif
129
130 #define HWA_CGA_M2_CLK_SEL 0x00000007
131 #define HWA_CGA_M2_CLK_SHIFT 0
132 #if defined(CONFIG_TARGET_LS1046ARDB) || defined(CONFIG_TARGET_LS1043ARDB)
133 rcw_tmp = in_be32(&gur->rcwsr[15]);
134 switch ((rcw_tmp & HWA_CGA_M2_CLK_SEL) >> HWA_CGA_M2_CLK_SHIFT) {
135 case 1:
136 sys_info->freq_cga_m2 = freq_c_pll[1];
137 break;
138 #if defined(CONFIG_TARGET_LS1046ARDB)
139 case 2:
140 sys_info->freq_cga_m2 = freq_c_pll[1] / 2;
141 break;
142 #endif
143 case 3:
144 sys_info->freq_cga_m2 = freq_c_pll[1] / 3;
145 break;
146 #if defined(CONFIG_TARGET_LS1046ARDB)
147 case 6:
148 sys_info->freq_cga_m2 = freq_c_pll[0] / 2;
149 break;
150 #endif
151 default:
152 printf("Error: Unknown cluster group A mux 2 clock select!\n");
153 break;
154 }
155 #endif
156
157 #if defined(CONFIG_FSL_IFC)
158 sys_info->freq_localbus = sys_info->freq_systembus /
159 CONFIG_SYS_FSL_IFC_CLK_DIV;
160 #endif
161 #ifdef CONFIG_SYS_DPAA_QBMAN
162 sys_info->freq_qman = (sys_info->freq_systembus /
163 CONFIG_SYS_FSL_PCLK_DIV) /
164 CONFIG_SYS_FSL_QMAN_CLK_DIV;
165 #endif
166 }
167
168 #ifdef CONFIG_SYS_DPAA_QBMAN
get_qman_freq(void)169 unsigned long get_qman_freq(void)
170 {
171 struct sys_info sys_info;
172
173 get_sys_info(&sys_info);
174
175 return sys_info.freq_qman;
176 }
177 #endif
178
get_clocks(void)179 int get_clocks(void)
180 {
181 struct sys_info sys_info;
182 #ifdef CONFIG_FSL_ESDHC
183 u32 clock = 0;
184 #endif
185 get_sys_info(&sys_info);
186 gd->cpu_clk = sys_info.freq_processor[0];
187 gd->bus_clk = sys_info.freq_systembus / CONFIG_SYS_FSL_PCLK_DIV;
188 gd->mem_clk = sys_info.freq_ddrbus;
189 #ifdef CONFIG_FSL_ESDHC
190 #if defined(CONFIG_ARCH_LS1012A)
191 clock = sys_info.freq_systembus;
192 #elif defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
193 clock = sys_info.freq_cga_m2;
194 #endif
195 gd->arch.sdhc_per_clk = clock / CONFIG_SYS_FSL_SDHC_CLK_DIV;
196 gd->arch.sdhc_clk = gd->bus_clk / CONFIG_SYS_FSL_SDHC_CLK_DIV;
197 #endif
198 if (gd->cpu_clk != 0)
199 return 0;
200 else
201 return 1;
202 }
203
204 /********************************************
205 * get_bus_freq
206 * return platform clock in Hz
207 *********************************************/
get_bus_freq(ulong dummy)208 ulong get_bus_freq(ulong dummy)
209 {
210 if (!gd->bus_clk)
211 get_clocks();
212
213 return gd->bus_clk;
214 }
215
get_ddr_freq(ulong dummy)216 ulong get_ddr_freq(ulong dummy)
217 {
218 if (!gd->mem_clk)
219 get_clocks();
220
221 return gd->mem_clk;
222 }
223
get_serial_clock(void)224 int get_serial_clock(void)
225 {
226 return get_bus_freq(0) / CONFIG_SYS_FSL_DUART_CLK_DIV;
227 }
228
get_i2c_freq(ulong dummy)229 int get_i2c_freq(ulong dummy)
230 {
231 return get_bus_freq(0) / CONFIG_SYS_FSL_I2C_CLK_DIV;
232 }
233
get_dspi_freq(ulong dummy)234 int get_dspi_freq(ulong dummy)
235 {
236 return get_bus_freq(0) / CONFIG_SYS_FSL_DSPI_CLK_DIV;
237 }
238
239 #ifdef CONFIG_FSL_LPUART
get_uart_freq(ulong dummy)240 int get_uart_freq(ulong dummy)
241 {
242 return get_bus_freq(0) / CONFIG_SYS_FSL_LPUART_CLK_DIV;
243 }
244 #endif
245
mxc_get_clock(enum mxc_clock clk)246 unsigned int mxc_get_clock(enum mxc_clock clk)
247 {
248 switch (clk) {
249 case MXC_I2C_CLK:
250 return get_i2c_freq(0);
251 case MXC_DSPI_CLK:
252 return get_dspi_freq(0);
253 #ifdef CONFIG_FSL_LPUART
254 case MXC_UART_CLK:
255 return get_uart_freq(0);
256 #endif
257 default:
258 printf("Unsupported clock\n");
259 }
260 return 0;
261 }
262