1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * (C) Copyright 2013 4 * David Feng <fenghua@phytium.com.cn> 5 */ 6 7#include <asm-offsets.h> 8#include <config.h> 9#include <linux/linkage.h> 10#include <asm/macro.h> 11#include <asm/armv8/mmu.h> 12 13/************************************************************************* 14 * 15 * Startup Code (reset vector) 16 * 17 *************************************************************************/ 18 19.globl _start 20_start: 21#if defined(CONFIG_LINUX_KERNEL_IMAGE_HEADER) 22#include <asm/boot0-linux-kernel-header.h> 23#elif defined(CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK) 24/* 25 * Various SoCs need something special and SoC-specific up front in 26 * order to boot, allow them to set that in their boot0.h file and then 27 * use it here. 28 */ 29#include <asm/arch/boot0.h> 30#else 31 b reset 32#endif 33 34 .align 3 35 36.globl _TEXT_BASE 37_TEXT_BASE: 38 .quad CONFIG_SYS_TEXT_BASE 39 40/* 41 * These are defined in the linker script. 42 */ 43.globl _end_ofs 44_end_ofs: 45 .quad _end - _start 46 47.globl _bss_start_ofs 48_bss_start_ofs: 49 .quad __bss_start - _start 50 51.globl _bss_end_ofs 52_bss_end_ofs: 53 .quad __bss_end - _start 54 55reset: 56 /* Allow the board to save important registers */ 57 b save_boot_params 58.globl save_boot_params_ret 59save_boot_params_ret: 60 61#if CONFIG_POSITION_INDEPENDENT 62 /* Verify that we're 4K aligned. */ 63 adr x0, _start 64 ands x0, x0, #0xfff 65 b.eq 1f 660: 67 /* 68 * FATAL, can't continue. 69 * U-Boot needs to be loaded at a 4K aligned address. 70 * 71 * We use ADRP and ADD to load some symbol addresses during startup. 72 * The ADD uses an absolute (non pc-relative) lo12 relocation 73 * thus requiring 4K alignment. 74 */ 75 wfi 76 b 0b 771: 78 79 /* 80 * Fix .rela.dyn relocations. This allows U-Boot to be loaded to and 81 * executed at a different address than it was linked at. 82 */ 83pie_fixup: 84 adr x0, _start /* x0 <- Runtime value of _start */ 85 ldr x1, _TEXT_BASE /* x1 <- Linked value of _start */ 86 subs x9, x0, x1 /* x9 <- Run-vs-link offset */ 87 beq pie_fixup_done 88 adrp x2, __rel_dyn_start /* x2 <- Runtime &__rel_dyn_start */ 89 add x2, x2, #:lo12:__rel_dyn_start 90 adrp x3, __rel_dyn_end /* x3 <- Runtime &__rel_dyn_end */ 91 add x3, x3, #:lo12:__rel_dyn_end 92pie_fix_loop: 93 ldp x0, x1, [x2], #16 /* (x0, x1) <- (Link location, fixup) */ 94 ldr x4, [x2], #8 /* x4 <- addend */ 95 cmp w1, #1027 /* relative fixup? */ 96 bne pie_skip_reloc 97 /* relative fix: store addend plus offset at dest location */ 98 add x0, x0, x9 99 add x4, x4, x9 100 str x4, [x0] 101pie_skip_reloc: 102 cmp x2, x3 103 b.lo pie_fix_loop 104pie_fixup_done: 105#endif 106 107#ifdef CONFIG_SYS_RESET_SCTRL 108 bl reset_sctrl 109#endif 110 111#if defined(CONFIG_ARMV8_SPL_EXCEPTION_VECTORS) || !defined(CONFIG_SPL_BUILD) 112.macro set_vbar, regname, reg 113 msr \regname, \reg 114.endm 115 adr x0, vectors 116#else 117.macro set_vbar, regname, reg 118.endm 119#endif 120 /* 121 * Could be EL3/EL2/EL1, Initial State: 122 * Little Endian, MMU Disabled, i/dCache Disabled 123 */ 124 switch_el x1, 3f, 2f, 1f 1253: set_vbar vbar_el3, x0 126 mrs x0, scr_el3 127 orr x0, x0, #0xf /* SCR_EL3.NS|IRQ|FIQ|EA */ 128 msr scr_el3, x0 129 msr cptr_el3, xzr /* Enable FP/SIMD */ 130#ifdef COUNTER_FREQUENCY 131 ldr x0, =COUNTER_FREQUENCY 132 msr cntfrq_el0, x0 /* Initialize CNTFRQ */ 133#endif 134 b 0f 1352: set_vbar vbar_el2, x0 136 mov x0, #0x33ff 137 msr cptr_el2, x0 /* Enable FP/SIMD */ 138 b 0f 1391: set_vbar vbar_el1, x0 140 mov x0, #3 << 20 141 msr cpacr_el1, x0 /* Enable FP/SIMD */ 1420: 143 isb 144 145 /* 146 * Enable SMPEN bit for coherency. 147 * This register is not architectural but at the moment 148 * this bit should be set for A53/A57/A72. 149 */ 150#ifdef CONFIG_ARMV8_SET_SMPEN 151 switch_el x1, 3f, 1f, 1f 1523: 153 mrs x0, S3_1_c15_c2_1 /* cpuectlr_el1 */ 154 orr x0, x0, #0x40 155 msr S3_1_c15_c2_1, x0 156 isb 1571: 158#endif 159 160 /* Apply ARM core specific erratas */ 161 bl apply_core_errata 162 163 /* 164 * Cache/BPB/TLB Invalidate 165 * i-cache is invalidated before enabled in icache_enable() 166 * tlb is invalidated before mmu is enabled in dcache_enable() 167 * d-cache is invalidated before enabled in dcache_enable() 168 */ 169 170 /* Processor specific initialization */ 171 bl lowlevel_init 172 173#if defined(CONFIG_ARMV8_SPIN_TABLE) && !defined(CONFIG_SPL_BUILD) 174 branch_if_master x0, x1, master_cpu 175 b spin_table_secondary_jump 176 /* never return */ 177#elif defined(CONFIG_ARMV8_MULTIENTRY) 178 branch_if_master x0, x1, master_cpu 179 180 /* 181 * Slave CPUs 182 */ 183slave_cpu: 184 wfe 185 ldr x1, =CPU_RELEASE_ADDR 186 ldr x0, [x1] 187 cbz x0, slave_cpu 188 br x0 /* branch to the given address */ 189#endif /* CONFIG_ARMV8_MULTIENTRY */ 190master_cpu: 191 bl _main 192 193#ifdef CONFIG_SYS_RESET_SCTRL 194reset_sctrl: 195 switch_el x1, 3f, 2f, 1f 1963: 197 mrs x0, sctlr_el3 198 b 0f 1992: 200 mrs x0, sctlr_el2 201 b 0f 2021: 203 mrs x0, sctlr_el1 204 2050: 206 ldr x1, =0xfdfffffa 207 and x0, x0, x1 208 209 switch_el x1, 6f, 5f, 4f 2106: 211 msr sctlr_el3, x0 212 b 7f 2135: 214 msr sctlr_el2, x0 215 b 7f 2164: 217 msr sctlr_el1, x0 218 2197: 220 dsb sy 221 isb 222 b __asm_invalidate_tlb_all 223 ret 224#endif 225 226/*-----------------------------------------------------------------------*/ 227 228WEAK(apply_core_errata) 229 230 mov x29, lr /* Save LR */ 231 /* For now, we support Cortex-A53, Cortex-A57 specific errata */ 232 233 /* Check if we are running on a Cortex-A53 core */ 234 branch_if_a53_core x0, apply_a53_core_errata 235 236 /* Check if we are running on a Cortex-A57 core */ 237 branch_if_a57_core x0, apply_a57_core_errata 2380: 239 mov lr, x29 /* Restore LR */ 240 ret 241 242apply_a53_core_errata: 243 244#ifdef CONFIG_ARM_ERRATA_855873 245 mrs x0, midr_el1 246 tst x0, #(0xf << 20) 247 b.ne 0b 248 249 mrs x0, midr_el1 250 and x0, x0, #0xf 251 cmp x0, #3 252 b.lt 0b 253 254 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */ 255 /* Enable data cache clean as data cache clean/invalidate */ 256 orr x0, x0, #1 << 44 257 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */ 258 isb 259#endif 260 b 0b 261 262apply_a57_core_errata: 263 264#ifdef CONFIG_ARM_ERRATA_828024 265 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */ 266 /* Disable non-allocate hint of w-b-n-a memory type */ 267 orr x0, x0, #1 << 49 268 /* Disable write streaming no L1-allocate threshold */ 269 orr x0, x0, #3 << 25 270 /* Disable write streaming no-allocate threshold */ 271 orr x0, x0, #3 << 27 272 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */ 273 isb 274#endif 275 276#ifdef CONFIG_ARM_ERRATA_826974 277 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */ 278 /* Disable speculative load execution ahead of a DMB */ 279 orr x0, x0, #1 << 59 280 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */ 281 isb 282#endif 283 284#ifdef CONFIG_ARM_ERRATA_833471 285 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */ 286 /* FPSCR write flush. 287 * Note that in some cases where a flush is unnecessary this 288 could impact performance. */ 289 orr x0, x0, #1 << 38 290 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */ 291 isb 292#endif 293 294#ifdef CONFIG_ARM_ERRATA_829520 295 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */ 296 /* Disable Indirect Predictor bit will prevent this erratum 297 from occurring 298 * Note that in some cases where a flush is unnecessary this 299 could impact performance. */ 300 orr x0, x0, #1 << 4 301 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */ 302 isb 303#endif 304 305#ifdef CONFIG_ARM_ERRATA_833069 306 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */ 307 /* Disable Enable Invalidates of BTB bit */ 308 and x0, x0, #0xE 309 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */ 310 isb 311#endif 312 b 0b 313ENDPROC(apply_core_errata) 314 315/*-----------------------------------------------------------------------*/ 316 317WEAK(lowlevel_init) 318 mov x29, lr /* Save LR */ 319 320#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) 321 branch_if_slave x0, 1f 322 ldr x0, =GICD_BASE 323 bl gic_init_secure 3241: 325#if defined(CONFIG_GICV3) 326 ldr x0, =GICR_BASE 327 bl gic_init_secure_percpu 328#elif defined(CONFIG_GICV2) 329 ldr x0, =GICD_BASE 330 ldr x1, =GICC_BASE 331 bl gic_init_secure_percpu 332#endif 333#endif 334 335#ifdef CONFIG_ARMV8_MULTIENTRY 336 branch_if_master x0, x1, 2f 337 338 /* 339 * Slave should wait for master clearing spin table. 340 * This sync prevent salves observing incorrect 341 * value of spin table and jumping to wrong place. 342 */ 343#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) 344#ifdef CONFIG_GICV2 345 ldr x0, =GICC_BASE 346#endif 347 bl gic_wait_for_interrupt 348#endif 349 350 /* 351 * All slaves will enter EL2 and optionally EL1. 352 */ 353 adr x4, lowlevel_in_el2 354 ldr x5, =ES_TO_AARCH64 355 bl armv8_switch_to_el2 356 357lowlevel_in_el2: 358#ifdef CONFIG_ARMV8_SWITCH_TO_EL1 359 adr x4, lowlevel_in_el1 360 ldr x5, =ES_TO_AARCH64 361 bl armv8_switch_to_el1 362 363lowlevel_in_el1: 364#endif 365 366#endif /* CONFIG_ARMV8_MULTIENTRY */ 367 3682: 369 mov lr, x29 /* Restore LR */ 370 ret 371ENDPROC(lowlevel_init) 372 373WEAK(smp_kick_all_cpus) 374 /* Kick secondary cpus up by SGI 0 interrupt */ 375#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) 376 ldr x0, =GICD_BASE 377 b gic_kick_secondary_cpus 378#endif 379 ret 380ENDPROC(smp_kick_all_cpus) 381 382/*-----------------------------------------------------------------------*/ 383 384ENTRY(c_runtime_cpu_setup) 385#if defined(CONFIG_ARMV8_SPL_EXCEPTION_VECTORS) || !defined(CONFIG_SPL_BUILD) 386 /* Relocate vBAR */ 387 adr x0, vectors 388 switch_el x1, 3f, 2f, 1f 3893: msr vbar_el3, x0 390 b 0f 3912: msr vbar_el2, x0 392 b 0f 3931: msr vbar_el1, x0 3940: 395#endif 396 397 ret 398ENDPROC(c_runtime_cpu_setup) 399 400WEAK(save_boot_params) 401 b save_boot_params_ret /* back to my caller */ 402ENDPROC(save_boot_params) 403