1/*
2 * Copyright (C) 2018 MediaTek Inc.
3 * Author: Ryder Lee <ryder.lee@mediatek.com>
4 *
5 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 */
7
8#include <dt-bindings/clock/mt7629-clk.h>
9#include <dt-bindings/gpio/gpio.h>
10#include <dt-bindings/interrupt-controller/irq.h>
11#include <dt-bindings/interrupt-controller/arm-gic.h>
12#include <dt-bindings/power/mt7629-power.h>
13#include <dt-bindings/reset/mt7629-reset.h>
14#include <dt-bindings/phy/phy.h>
15#include "skeleton.dtsi"
16
17/ {
18	compatible = "mediatek,mt7629";
19	interrupt-parent = <&sysirq>;
20	#address-cells = <1>;
21	#size-cells = <1>;
22
23	cpus {
24		#address-cells = <1>;
25		#size-cells = <0>;
26		enable-method = "mediatek,mt6589-smp";
27
28		cpu@0 {
29			device_type = "cpu";
30			compatible = "arm,cortex-a7";
31			reg = <0x0>;
32			clock-frequency = <1250000000>;
33		};
34
35		cpu@1 {
36			device_type = "cpu";
37			compatible = "arm,cortex-a7";
38			reg = <0x1>;
39			clock-frequency = <1250000000>;
40		};
41	};
42
43	clk20m: oscillator@0 {
44		compatible = "fixed-clock";
45		#clock-cells = <0>;
46		clock-frequency = <20000000>;
47		clock-output-names = "clk20m";
48	};
49
50	clk40m: oscillator@1 {
51		compatible = "fixed-clock";
52		#clock-cells = <0>;
53		clock-frequency = <40000000>;
54		clock-output-names = "clkxtal";
55	};
56
57	timer {
58		compatible = "arm,armv7-timer";
59		interrupt-parent = <&gic>;
60		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
61			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
62			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
63			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
64		clock-frequency = <20000000>;
65		arm,cpu-registers-not-fw-configured;
66	};
67
68	infracfg: syscon@10000000 {
69		compatible = "mediatek,mt7629-infracfg", "syscon";
70		reg = <0x10000000 0x1000>;
71		#clock-cells = <1>;
72	};
73
74	pericfg: syscon@10002000 {
75		compatible = "mediatek,mt7629-pericfg", "syscon";
76		reg = <0x10002000 0x1000>;
77		#clock-cells = <1>;
78	};
79
80	timer0: timer@10004000 {
81		compatible = "mediatek,timer";
82		reg = <0x10004000 0x80>;
83		interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>;
84		clocks = <&topckgen CLK_TOP_CLKXTAL_D4>,
85			 <&topckgen CLK_TOP_10M_SEL>;
86		clock-names = "mux", "src";
87	};
88
89	scpsys: scpsys@10006000 {
90		compatible = "mediatek,mt7629-scpsys";
91		reg = <0x10006000 0x1000>;
92		clocks = <&topckgen CLK_TOP_HIF_SEL>;
93		clock-names = "hif_sel";
94		assigned-clocks = <&topckgen CLK_TOP_HIF_SEL>;
95		assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
96		#power-domain-cells = <1>;
97		infracfg = <&infracfg>;
98	};
99
100	mcucfg: syscon@10200000 {
101		compatible = "mediatek,mt7629-mcucfg", "syscon";
102		reg = <0x10200000 0x1000>;
103		#clock-cells = <1>;
104	};
105
106	sysirq: interrupt-controller@10200a80 {
107		compatible = "mediatek,sysirq";
108		reg = <0x10200a80 0x20>;
109		interrupt-controller;
110		#interrupt-cells = <3>;
111		interrupt-parent = <&gic>;
112	};
113
114	dramc: dramc@10203000 {
115		compatible = "mediatek,mt7629-dramc";
116		reg = <0x10203000 0x600>,	/* EMI */
117		      <0x10213000 0x1000>,	/* DDRPHY */
118		      <0x10214000 0xd00>;	/* DRAMC_AO */
119		clocks = <&topckgen CLK_TOP_DDRPHYCFG_SEL>,
120			 <&topckgen CLK_TOP_SYSPLL1_D8>,
121			 <&topckgen CLK_TOP_MEM_SEL>,
122			 <&topckgen CLK_TOP_DMPLL>;
123		clock-names = "phy", "phy_mux", "mem", "mem_mux";
124	};
125
126	apmixedsys: clock-controller@10209000 {
127		compatible = "mediatek,mt7629-apmixedsys";
128		reg = <0x10209000 0x1000>;
129		#clock-cells = <1>;
130	};
131
132	topckgen: clock-controller@10210000 {
133		compatible = "mediatek,mt7629-topckgen";
134		reg = <0x10210000 0x1000>;
135		#clock-cells = <1>;
136	};
137
138	watchdog: watchdog@10212000 {
139		compatible = "mediatek,wdt";
140		reg = <0x10212000 0x600>;
141		interrupts = <GIC_SPI 128 IRQ_TYPE_EDGE_FALLING>;
142		#reset-cells = <1>;
143		status = "disabled";
144	};
145
146	wdt-reboot {
147		compatible = "wdt-reboot";
148		wdt = <&watchdog>;
149	};
150
151	pinctrl: pinctrl@10217000 {
152		compatible = "mediatek,mt7629-pinctrl";
153		reg = <0x10217000 0x8000>;
154
155		gpio: gpio-controller {
156			gpio-controller;
157			#gpio-cells = <2>;
158		};
159	};
160
161	gic: interrupt-controller@10300000 {
162		compatible = "arm,gic-400";
163		interrupt-controller;
164		#interrupt-cells = <3>;
165		interrupt-parent = <&gic>;
166		reg = <0x10310000 0x1000>,
167		      <0x10320000 0x1000>,
168		      <0x10340000 0x2000>,
169		      <0x10360000 0x2000>;
170	};
171
172	uart0: serial@11002000 {
173		compatible = "mediatek,hsuart";
174		reg = <0x11002000 0x400>;
175		reg-shift = <2>;
176		interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
177		clocks = <&topckgen CLK_TOP_UART_SEL>,
178			 <&pericfg CLK_PERI_UART0_PD>;
179		clock-names = "baud", "bus";
180		status = "disabled";
181		assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>;
182		assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>;
183	};
184
185	uart1: serial@11003000 {
186		compatible = "mediatek,hsuart";
187		reg = <0x11003000 0x400>;
188		reg-shift = <2>;
189		interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
190		clocks = <&topckgen CLK_TOP_UART_SEL>,
191			 <&pericfg CLK_PERI_UART1_PD>;
192		clock-names = "baud", "bus";
193		assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>;
194		assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>;
195		status = "disabled";
196	};
197
198	uart2: serial@11004000 {
199		compatible = "mediatek,hsuart";
200		reg = <0x11004000 0x400>;
201		reg-shift = <2>;
202		interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
203		clocks = <&topckgen CLK_TOP_UART_SEL>,
204			 <&pericfg CLK_PERI_UART2_PD>;
205		clock-names = "baud", "bus";
206		assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>;
207		assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>;
208		status = "disabled";
209	};
210
211	snfi: snfi@1100d000 {
212		compatible = "mediatek,mtk-snfi-spi";
213		reg = <0x1100d000 0x2000>;
214		clocks = <&pericfg CLK_PERI_NFI_PD>,
215			 <&pericfg CLK_PERI_SNFI_PD>;
216		clock-names = "nfi_clk", "pad_clk";
217		assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>,
218				  <&topckgen CLK_TOP_NFI_INFRA_SEL>;
219		assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>,
220					 <&topckgen CLK_TOP_UNIVPLL2_D8>;
221		status = "disabled";
222		#address-cells = <1>;
223		#size-cells = <0>;
224	};
225
226	snor: snor@11014000 {
227		compatible = "mediatek,mtk-snor";
228		reg = <0x11014000 0x1000>;
229		clocks = <&pericfg CLK_PERI_FLASH_PD>,
230			 <&topckgen CLK_TOP_FLASH_SEL>;
231		clock-names = "spi", "sf";
232		status = "disabled";
233		#address-cells = <1>;
234		#size-cells = <0>;
235	};
236
237	ssusbsys: ssusbsys@1a000000 {
238		compatible = "mediatek,mt7629-ssusbsys", "syscon";
239		reg = <0x1a000000 0x1000>;
240		#clock-cells = <1>;
241	};
242
243	xhci: usb@1a0c0000 {
244		compatible = "mediatek,mt7629-xhci", "mediatek,mtk-xhci";
245		reg = <0x1a0c0000 0x1000>, <0x1a0c3e00 0x0100>;
246		reg-names = "mac", "ippc";
247		power-domains = <&scpsys MT7629_POWER_DOMAIN_HIF1>;
248		clocks = <&ssusbsys CLK_SSUSB_SYS_EN>,
249			 <&ssusbsys CLK_SSUSB_REF_EN>,
250			 <&ssusbsys CLK_SSUSB_MCU_EN>,
251			 <&ssusbsys CLK_SSUSB_DMA_EN>;
252		clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
253		phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
254		status = "disabled";
255	};
256
257	u3phy: usb-phy@1a0c4000 {
258		compatible = "mediatek,mt7629-tphy", "mediatek,generic-tphy-v2";
259		#address-cells = <1>;
260		#size-cells = <1>;
261		ranges = <0 0x1a0c4000 0x1000>;
262		status = "disabled";
263
264		u2port0: usb-phy@0 {
265			reg = <0x0 0x0700>;
266			#phy-cells = <1>;
267			clocks = <&ssusbsys CLK_SSUSB_U2_PHY_EN>;
268			clock-names = "ref";
269		};
270
271		u3port0: usb-phy@700 {
272			reg = <0x0700 0x0700>;
273			#phy-cells = <1>;
274		};
275	};
276
277	ethsys: syscon@1b000000 {
278		compatible = "mediatek,mt7629-ethsys", "syscon";
279		reg = <0x1b000000 0x1000>;
280		#clock-cells = <1>;
281		#reset-cells = <1>;
282	};
283
284	eth: ethernet@1b100000 {
285		compatible = "mediatek,mt7629-eth", "syscon";
286		reg = <0x1b100000 0x20000>;
287		clocks = <&topckgen CLK_TOP_ETH_SEL>,
288			<&topckgen CLK_TOP_F10M_REF_SEL>,
289			<&ethsys CLK_ETH_ESW_EN>,
290			<&ethsys CLK_ETH_GP0_EN>,
291			<&ethsys CLK_ETH_GP1_EN>,
292			<&ethsys CLK_ETH_GP2_EN>,
293			<&ethsys CLK_ETH_FE_EN>,
294			<&sgmiisys0 CLK_SGMII_TX_EN>,
295			<&sgmiisys0 CLK_SGMII_RX_EN>,
296			<&sgmiisys0 CLK_SGMII_CDR_REF>,
297			<&sgmiisys0 CLK_SGMII_CDR_FB>,
298			<&sgmiisys1 CLK_SGMII_TX_EN>,
299			<&sgmiisys1 CLK_SGMII_RX_EN>,
300			<&sgmiisys1 CLK_SGMII_CDR_REF>,
301			<&sgmiisys1 CLK_SGMII_CDR_FB>,
302			<&apmixedsys CLK_APMIXED_SGMIPLL>,
303			<&apmixedsys CLK_APMIXED_ETH2PLL>;
304		clock-names = "ethif", "sgmiitop", "esw", "gp0", "gp1", "gp2",
305				"fe", "sgmii_tx250m", "sgmii_rx250m",
306				"sgmii_cdr_ref", "sgmii_cdr_fb",
307				"sgmii2_tx250m", "sgmii2_rx250m",
308				"sgmii2_cdr_ref", "sgmii2_cdr_fb",
309				"sgmii_ck", "eth2pll";
310		assigned-clocks = <&topckgen CLK_TOP_ETH_SEL>,
311				  <&topckgen CLK_TOP_F10M_REF_SEL>;
312		assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>,
313					 <&topckgen CLK_TOP_SGMIIPLL_D2>;
314		power-domains = <&scpsys MT7629_POWER_DOMAIN_ETHSYS>;
315		resets = <&ethsys ETHSYS_FE_RST>;
316		reset-names = "fe";
317		mediatek,ethsys = <&ethsys>;
318		mediatek,sgmiisys = <&sgmiisys0>;
319		mediatek,infracfg = <&infracfg>;
320		#address-cells = <1>;
321		#size-cells = <0>;
322		status = "disabled";
323	};
324
325	sgmiisys0: syscon@1b128000 {
326		compatible = "mediatek,mt7629-sgmiisys", "syscon";
327		reg = <0x1b128000 0x1000>;
328		#clock-cells = <1>;
329	};
330
331	sgmiisys1: syscon@1b130000 {
332		compatible = "mediatek,mt7629-sgmiisys", "syscon";
333		reg = <0x1b130000 0x1000>;
334		#clock-cells = <1>;
335	};
336
337	pwm: pwm@11006000 {
338		compatible = "mediatek,mt7629-pwm";
339		reg = <0x11006000 0x1000>;
340		#clock-cells = <1>;
341		#pwm-cells = <2>;
342		interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
343		clocks = <&topckgen CLK_TOP_PWM_SEL>,
344			 <&pericfg CLK_PERI_PWM_PD>,
345			 <&pericfg CLK_PERI_PWM1_PD>;
346		clock-names = "top", "main", "pwm1";
347		assigned-clocks = <&topckgen CLK_TOP_PWM_SEL>;
348		assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL2_D4>;
349		status = "disabled";
350	};
351
352};
353