1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2012-2019 Altera Corporation <www.altera.com>
4 */
5
6 #include <common.h>
7 #include <cpu_func.h>
8 #include <hang.h>
9 #include <init.h>
10 #include <asm/global_data.h>
11 #include <asm/io.h>
12 #include <asm/pl310.h>
13 #include <asm/u-boot.h>
14 #include <asm/utils.h>
15 #include <image.h>
16 #include <asm/arch/reset_manager.h>
17 #include <spl.h>
18 #include <asm/arch/system_manager.h>
19 #include <asm/arch/freeze_controller.h>
20 #include <asm/arch/clock_manager.h>
21 #include <asm/arch/scan_manager.h>
22 #include <asm/arch/sdram.h>
23 #include <asm/arch/scu.h>
24 #include <asm/arch/misc.h>
25 #include <asm/arch/nic301.h>
26 #include <asm/sections.h>
27 #include <fdtdec.h>
28 #include <watchdog.h>
29 #include <asm/arch/pinmux.h>
30 #include <asm/arch/fpga_manager.h>
31 #include <mmc.h>
32 #include <memalign.h>
33
34 #define FPGA_BUFSIZ 16 * 1024
35
36 DECLARE_GLOBAL_DATA_PTR;
37
38 #define BOOTROM_SHARED_MEM_SIZE 0x800 /* 2KB */
39 #define BOOTROM_SHARED_MEM_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
40 SOCFPGA_PHYS_OCRAM_SIZE - \
41 BOOTROM_SHARED_MEM_SIZE)
42 #define RST_STATUS_SHARED_ADDR (BOOTROM_SHARED_MEM_ADDR + 0x438)
43 static u32 rst_mgr_status __section(.data);
44
45 /*
46 * Bootrom will clear the status register in reset manager and stores the
47 * reset status value in shared memory. Bootrom stores shared data at last
48 * 2KB of onchip RAM.
49 * This function save reset status provided by BootROM to rst_mgr_status.
50 * More information about reset status register value can be found in reset
51 * manager register description.
52 * When running in debugger without Bootrom, r0 to r3 are random values.
53 * So, skip save the value when r0 is not BootROM shared data address.
54 *
55 * r0 - Contains the pointer to the shared memory block. The shared
56 * memory block is located in the top 2 KB of on-chip RAM.
57 * r1 - contains the length of the shared memory.
58 * r2 - unused and set to 0x0.
59 * r3 - points to the version block.
60 */
save_boot_params(unsigned long r0,unsigned long r1,unsigned long r2,unsigned long r3)61 void save_boot_params(unsigned long r0, unsigned long r1, unsigned long r2,
62 unsigned long r3)
63 {
64 if (r0 == BOOTROM_SHARED_MEM_ADDR)
65 rst_mgr_status = readl(RST_STATUS_SHARED_ADDR);
66
67 save_boot_params_ret();
68 }
69
spl_boot_device(void)70 u32 spl_boot_device(void)
71 {
72 const u32 bsel = readl(socfpga_get_sysmgr_addr() + SYSMGR_A10_BOOTINFO);
73
74 switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) {
75 case 0x1: /* FPGA (HPS2FPGA Bridge) */
76 return BOOT_DEVICE_RAM;
77 case 0x2: /* NAND Flash (1.8V) */
78 case 0x3: /* NAND Flash (3.0V) */
79 socfpga_per_reset(SOCFPGA_RESET(NAND), 0);
80 return BOOT_DEVICE_NAND;
81 case 0x4: /* SD/MMC External Transceiver (1.8V) */
82 case 0x5: /* SD/MMC Internal Transceiver (3.0V) */
83 socfpga_per_reset(SOCFPGA_RESET(SDMMC), 0);
84 socfpga_per_reset(SOCFPGA_RESET(DMA), 0);
85 return BOOT_DEVICE_MMC1;
86 case 0x6: /* QSPI Flash (1.8V) */
87 case 0x7: /* QSPI Flash (3.0V) */
88 socfpga_per_reset(SOCFPGA_RESET(QSPI), 0);
89 return BOOT_DEVICE_SPI;
90 default:
91 printf("Invalid boot device (bsel=%08x)!\n", bsel);
92 hang();
93 }
94 }
95
96 #ifdef CONFIG_SPL_MMC_SUPPORT
spl_mmc_boot_mode(const u32 boot_device)97 u32 spl_mmc_boot_mode(const u32 boot_device)
98 {
99 #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
100 return MMCSD_MODE_FS;
101 #else
102 return MMCSD_MODE_RAW;
103 #endif
104 }
105 #endif
106
spl_board_init(void)107 void spl_board_init(void)
108 {
109 ALLOC_CACHE_ALIGN_BUFFER(char, buf, FPGA_BUFSIZ);
110
111 /* enable console uart printing */
112 preloader_console_init();
113 WATCHDOG_RESET();
114
115 arch_early_init_r();
116
117 /* If the full FPGA is already loaded, ie.from EPCQ, config fpga pins */
118 if (is_fpgamgr_user_mode()) {
119 int ret = config_pins(gd->fdt_blob, "shared");
120
121 if (ret)
122 return;
123
124 ret = config_pins(gd->fdt_blob, "fpga");
125 if (ret)
126 return;
127 } else if (!is_fpgamgr_early_user_mode()) {
128 /* Program IOSSM(early IO release) or full FPGA */
129 fpgamgr_program(buf, FPGA_BUFSIZ, 0);
130 }
131
132 /* If the IOSSM/full FPGA is already loaded, start DDR */
133 if (is_fpgamgr_early_user_mode() || is_fpgamgr_user_mode())
134 ddr_calibration_sequence();
135
136 if (!is_fpgamgr_user_mode())
137 fpgamgr_program(buf, FPGA_BUFSIZ, 0);
138 }
139
board_init_f(ulong dummy)140 void board_init_f(ulong dummy)
141 {
142 if (spl_early_init())
143 hang();
144
145 socfpga_get_managers_addr();
146
147 dcache_disable();
148
149 socfpga_init_security_policies();
150 socfpga_sdram_remap_zero();
151 socfpga_pl310_clear();
152
153 /* Assert reset to all except L4WD0 and L4TIMER0 */
154 socfpga_per_reset_all();
155 socfpga_watchdog_disable();
156
157 /* Configure the clock based on handoff */
158 cm_basic_init(gd->fdt_blob);
159
160 #ifdef CONFIG_HW_WATCHDOG
161 /* release osc1 watchdog timer 0 from reset */
162 socfpga_reset_deassert_osc1wd0();
163
164 /* reconfigure and enable the watchdog */
165 hw_watchdog_init();
166 WATCHDOG_RESET();
167 #endif /* CONFIG_HW_WATCHDOG */
168
169 config_dedicated_pins(gd->fdt_blob);
170 WATCHDOG_RESET();
171 }
172