1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2019 Intel Corporation <www.intel.com>
4 *
5 */
6
7 #include <init.h>
8 #include <log.h>
9 #include <asm/global_data.h>
10 #include <asm/io.h>
11 #include <asm/u-boot.h>
12 #include <asm/utils.h>
13 #include <common.h>
14 #include <hang.h>
15 #include <image.h>
16 #include <spl.h>
17 #include <asm/arch/clock_manager.h>
18 #include <asm/arch/firewall.h>
19 #include <asm/arch/mailbox_s10.h>
20 #include <asm/arch/misc.h>
21 #include <asm/arch/reset_manager.h>
22 #include <asm/arch/system_manager.h>
23 #include <watchdog.h>
24 #include <dm/uclass.h>
25
26 DECLARE_GLOBAL_DATA_PTR;
27
spl_boot_device(void)28 u32 spl_boot_device(void)
29 {
30 return BOOT_DEVICE_MMC1;
31 }
32
33 #ifdef CONFIG_SPL_MMC_SUPPORT
spl_mmc_boot_mode(const u32 boot_device)34 u32 spl_mmc_boot_mode(const u32 boot_device)
35 {
36 #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
37 return MMCSD_MODE_FS;
38 #else
39 return MMCSD_MODE_RAW;
40 #endif
41 }
42 #endif
43
board_init_f(ulong dummy)44 void board_init_f(ulong dummy)
45 {
46 int ret;
47 struct udevice *dev;
48
49 ret = spl_early_init();
50 if (ret)
51 hang();
52
53 socfpga_get_managers_addr();
54
55 /* Ensure watchdog is paused when debugging is happening */
56 writel(SYSMGR_WDDBG_PAUSE_ALL_CPU,
57 socfpga_get_sysmgr_addr() + SYSMGR_SOC64_WDDBG);
58
59 #ifdef CONFIG_HW_WATCHDOG
60 /* Enable watchdog before initializing the HW */
61 socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
62 socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
63 hw_watchdog_init();
64 #endif
65
66 /* ensure all processors are not released prior Linux boot */
67 writeq(0, CPU_RELEASE_ADDR);
68
69 timer_init();
70
71 sysmgr_pinmux_init();
72
73 ret = uclass_get_device(UCLASS_CLK, 0, &dev);
74 if (ret) {
75 debug("Clock init failed: %d\n", ret);
76 hang();
77 }
78
79 preloader_console_init();
80 print_reset_info();
81 cm_print_clock_quick_summary();
82
83 firewall_setup();
84 ret = uclass_get_device(UCLASS_CACHE, 0, &dev);
85 if (ret) {
86 debug("CCU init failed: %d\n", ret);
87 hang();
88 }
89
90 #if CONFIG_IS_ENABLED(ALTERA_SDRAM)
91 ret = uclass_get_device(UCLASS_RAM, 0, &dev);
92 if (ret) {
93 debug("DRAM init failed: %d\n", ret);
94 hang();
95 }
96 #endif
97
98 mbox_init();
99
100 #ifdef CONFIG_CADENCE_QSPI
101 mbox_qspi_open();
102 #endif
103 }
104