1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
2 /*
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
4 */
5
6 #define LOG_CATEGORY LOGC_ARCH
7
8 #include <common.h>
9 #include <clk.h>
10 #include <cpu_func.h>
11 #include <debug_uart.h>
12 #include <env.h>
13 #include <init.h>
14 #include <log.h>
15 #include <misc.h>
16 #include <net.h>
17 #include <asm/io.h>
18 #include <asm/arch/bsec.h>
19 #include <asm/arch/stm32.h>
20 #include <asm/arch/sys_proto.h>
21 #include <asm/global_data.h>
22 #include <dm/device.h>
23 #include <dm/uclass.h>
24 #include <linux/bitops.h>
25
26 /* RCC register */
27 #define RCC_TZCR (STM32_RCC_BASE + 0x00)
28 #define RCC_DBGCFGR (STM32_RCC_BASE + 0x080C)
29 #define RCC_BDCR (STM32_RCC_BASE + 0x0140)
30 #define RCC_MP_APB5ENSETR (STM32_RCC_BASE + 0x0208)
31 #define RCC_MP_AHB5ENSETR (STM32_RCC_BASE + 0x0210)
32 #define RCC_BDCR_VSWRST BIT(31)
33 #define RCC_BDCR_RTCSRC GENMASK(17, 16)
34 #define RCC_DBGCFGR_DBGCKEN BIT(8)
35
36 /* Security register */
37 #define ETZPC_TZMA1_SIZE (STM32_ETZPC_BASE + 0x04)
38 #define ETZPC_DECPROT0 (STM32_ETZPC_BASE + 0x10)
39
40 #define TZC_GATE_KEEPER (STM32_TZC_BASE + 0x008)
41 #define TZC_REGION_ATTRIBUTE0 (STM32_TZC_BASE + 0x110)
42 #define TZC_REGION_ID_ACCESS0 (STM32_TZC_BASE + 0x114)
43
44 #define TAMP_CR1 (STM32_TAMP_BASE + 0x00)
45
46 #define PWR_CR1 (STM32_PWR_BASE + 0x00)
47 #define PWR_MCUCR (STM32_PWR_BASE + 0x14)
48 #define PWR_CR1_DBP BIT(8)
49 #define PWR_MCUCR_SBF BIT(6)
50
51 /* DBGMCU register */
52 #define DBGMCU_IDC (STM32_DBGMCU_BASE + 0x00)
53 #define DBGMCU_APB4FZ1 (STM32_DBGMCU_BASE + 0x2C)
54 #define DBGMCU_APB4FZ1_IWDG2 BIT(2)
55 #define DBGMCU_IDC_DEV_ID_MASK GENMASK(11, 0)
56 #define DBGMCU_IDC_DEV_ID_SHIFT 0
57 #define DBGMCU_IDC_REV_ID_MASK GENMASK(31, 16)
58 #define DBGMCU_IDC_REV_ID_SHIFT 16
59
60 /* GPIOZ registers */
61 #define GPIOZ_SECCFGR 0x54004030
62
63 /* boot interface from Bootrom
64 * - boot instance = bit 31:16
65 * - boot device = bit 15:0
66 */
67 #define BOOTROM_PARAM_ADDR 0x2FFC0078
68 #define BOOTROM_MODE_MASK GENMASK(15, 0)
69 #define BOOTROM_MODE_SHIFT 0
70 #define BOOTROM_INSTANCE_MASK GENMASK(31, 16)
71 #define BOOTROM_INSTANCE_SHIFT 16
72
73 /* Device Part Number (RPN) = OTP_DATA1 lower 8 bits */
74 #define RPN_SHIFT 0
75 #define RPN_MASK GENMASK(7, 0)
76
77 /* Package = bit 27:29 of OTP16
78 * - 100: LBGA448 (FFI) => AA = LFBGA 18x18mm 448 balls p. 0.8mm
79 * - 011: LBGA354 (LCI) => AB = LFBGA 16x16mm 359 balls p. 0.8mm
80 * - 010: TFBGA361 (FFC) => AC = TFBGA 12x12mm 361 balls p. 0.5mm
81 * - 001: TFBGA257 (LCC) => AD = TFBGA 10x10mm 257 balls p. 0.5mm
82 * - others: Reserved
83 */
84 #define PKG_SHIFT 27
85 #define PKG_MASK GENMASK(2, 0)
86
87 /*
88 * early TLB into the .data section so that it not get cleared
89 * with 16kB allignment (see TTBR0_BASE_ADDR_MASK)
90 */
91 u8 early_tlb[PGTABLE_SIZE] __section(".data") __aligned(0x4000);
92
93 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
94 #ifndef CONFIG_TFABOOT
security_init(void)95 static void security_init(void)
96 {
97 /* Disable the backup domain write protection */
98 /* the protection is enable at each reset by hardware */
99 /* And must be disable by software */
100 setbits_le32(PWR_CR1, PWR_CR1_DBP);
101
102 while (!(readl(PWR_CR1) & PWR_CR1_DBP))
103 ;
104
105 /* If RTC clock isn't enable so this is a cold boot then we need
106 * to reset the backup domain
107 */
108 if (!(readl(RCC_BDCR) & RCC_BDCR_RTCSRC)) {
109 setbits_le32(RCC_BDCR, RCC_BDCR_VSWRST);
110 while (!(readl(RCC_BDCR) & RCC_BDCR_VSWRST))
111 ;
112 clrbits_le32(RCC_BDCR, RCC_BDCR_VSWRST);
113 }
114
115 /* allow non secure access in Write/Read for all peripheral */
116 writel(GENMASK(25, 0), ETZPC_DECPROT0);
117
118 /* Open SYSRAM for no secure access */
119 writel(0x0, ETZPC_TZMA1_SIZE);
120
121 /* enable TZC1 TZC2 clock */
122 writel(BIT(11) | BIT(12), RCC_MP_APB5ENSETR);
123
124 /* Region 0 set to no access by default */
125 /* bit 0 / 16 => nsaid0 read/write Enable
126 * bit 1 / 17 => nsaid1 read/write Enable
127 * ...
128 * bit 15 / 31 => nsaid15 read/write Enable
129 */
130 writel(0xFFFFFFFF, TZC_REGION_ID_ACCESS0);
131 /* bit 30 / 31 => Secure Global Enable : write/read */
132 /* bit 0 / 1 => Region Enable for filter 0/1 */
133 writel(BIT(0) | BIT(1) | BIT(30) | BIT(31), TZC_REGION_ATTRIBUTE0);
134
135 /* Enable Filter 0 and 1 */
136 setbits_le32(TZC_GATE_KEEPER, BIT(0) | BIT(1));
137
138 /* RCC trust zone deactivated */
139 writel(0x0, RCC_TZCR);
140
141 /* TAMP: deactivate the internal tamper
142 * Bit 23 ITAMP8E: monotonic counter overflow
143 * Bit 20 ITAMP5E: RTC calendar overflow
144 * Bit 19 ITAMP4E: HSE monitoring
145 * Bit 18 ITAMP3E: LSE monitoring
146 * Bit 16 ITAMP1E: RTC power domain supply monitoring
147 */
148 writel(0x0, TAMP_CR1);
149
150 /* GPIOZ: deactivate the security */
151 writel(BIT(0), RCC_MP_AHB5ENSETR);
152 writel(0x0, GPIOZ_SECCFGR);
153 }
154 #endif /* CONFIG_TFABOOT */
155
156 /*
157 * Debug init
158 */
dbgmcu_init(void)159 static void dbgmcu_init(void)
160 {
161 /*
162 * Freeze IWDG2 if Cortex-A7 is in debug mode
163 * done in TF-A for TRUSTED boot and
164 * DBGMCU access is controlled by BSEC_DENABLE.DBGSWENABLE
165 */
166 if (!IS_ENABLED(CONFIG_TFABOOT) && bsec_dbgswenable()) {
167 setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
168 setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2);
169 }
170 }
171
spl_board_init(void)172 void spl_board_init(void)
173 {
174 dbgmcu_init();
175 }
176 #endif /* !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) */
177
178 #if !defined(CONFIG_TFABOOT) && \
179 (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
180 /* get bootmode from ROM code boot context: saved in TAMP register */
update_bootmode(void)181 static void update_bootmode(void)
182 {
183 u32 boot_mode;
184 u32 bootrom_itf = readl(BOOTROM_PARAM_ADDR);
185 u32 bootrom_device, bootrom_instance;
186
187 /* enable TAMP clock = RTCAPBEN */
188 writel(BIT(8), RCC_MP_APB5ENSETR);
189
190 /* read bootrom context */
191 bootrom_device =
192 (bootrom_itf & BOOTROM_MODE_MASK) >> BOOTROM_MODE_SHIFT;
193 bootrom_instance =
194 (bootrom_itf & BOOTROM_INSTANCE_MASK) >> BOOTROM_INSTANCE_SHIFT;
195 boot_mode =
196 ((bootrom_device << BOOT_TYPE_SHIFT) & BOOT_TYPE_MASK) |
197 ((bootrom_instance << BOOT_INSTANCE_SHIFT) &
198 BOOT_INSTANCE_MASK);
199
200 /* save the boot mode in TAMP backup register */
201 clrsetbits_le32(TAMP_BOOT_CONTEXT,
202 TAMP_BOOT_MODE_MASK,
203 boot_mode << TAMP_BOOT_MODE_SHIFT);
204 }
205 #endif
206
get_bootmode(void)207 u32 get_bootmode(void)
208 {
209 /* read bootmode from TAMP backup register */
210 return (readl(TAMP_BOOT_CONTEXT) & TAMP_BOOT_MODE_MASK) >>
211 TAMP_BOOT_MODE_SHIFT;
212 }
213
214 /*
215 * initialize the MMU and activate cache in SPL or in U-Boot pre-reloc stage
216 * MMU/TLB is updated in enable_caches() for U-Boot after relocation
217 * or is deactivated in U-Boot entry function start.S::cpu_init_cp15
218 */
early_enable_caches(void)219 static void early_enable_caches(void)
220 {
221 /* I-cache is already enabled in start.S: cpu_init_cp15 */
222
223 if (CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
224 return;
225
226 if (!(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))) {
227 gd->arch.tlb_size = PGTABLE_SIZE;
228 gd->arch.tlb_addr = (unsigned long)&early_tlb;
229 }
230
231 dcache_enable();
232
233 if (IS_ENABLED(CONFIG_SPL_BUILD))
234 mmu_set_region_dcache_behaviour(
235 ALIGN_DOWN(STM32_SYSRAM_BASE, MMU_SECTION_SIZE),
236 ALIGN(STM32_SYSRAM_SIZE, MMU_SECTION_SIZE),
237 DCACHE_DEFAULT_OPTION);
238 else
239 mmu_set_region_dcache_behaviour(STM32_DDR_BASE,
240 CONFIG_DDR_CACHEABLE_SIZE,
241 DCACHE_DEFAULT_OPTION);
242 }
243
244 /*
245 * Early system init
246 */
arch_cpu_init(void)247 int arch_cpu_init(void)
248 {
249 u32 boot_mode;
250
251 early_enable_caches();
252
253 /* early armv7 timer init: needed for polling */
254 timer_init();
255
256 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
257 #ifndef CONFIG_TFABOOT
258 security_init();
259 update_bootmode();
260 #endif
261 /* Reset Coprocessor state unless it wakes up from Standby power mode */
262 if (!(readl(PWR_MCUCR) & PWR_MCUCR_SBF)) {
263 writel(TAMP_COPRO_STATE_OFF, TAMP_COPRO_STATE);
264 writel(0, TAMP_COPRO_RSC_TBL_ADDRESS);
265 }
266 #endif
267
268 boot_mode = get_bootmode();
269
270 if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL) &&
271 (boot_mode & TAMP_BOOT_DEVICE_MASK) == BOOT_SERIAL_UART)
272 gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
273 #if defined(CONFIG_DEBUG_UART) && \
274 !defined(CONFIG_TFABOOT) && \
275 (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
276 else
277 debug_uart_init();
278 #endif
279
280 return 0;
281 }
282
enable_caches(void)283 void enable_caches(void)
284 {
285 /* I-cache is already enabled in start.S: icache_enable() not needed */
286
287 /* deactivate the data cache, early enabled in arch_cpu_init() */
288 dcache_disable();
289 /*
290 * update MMU after relocation and enable the data cache
291 * warning: the TLB location udpated in board_f.c::reserve_mmu
292 */
293 dcache_enable();
294 }
295
read_idc(void)296 static u32 read_idc(void)
297 {
298 /* DBGMCU access is controlled by BSEC_DENABLE.DBGSWENABLE */
299 if (bsec_dbgswenable()) {
300 setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
301
302 return readl(DBGMCU_IDC);
303 }
304
305 if (CONFIG_IS_ENABLED(STM32MP15x))
306 return CPU_DEV_STM32MP15; /* STM32MP15x and unknown revision */
307 else
308 return 0x0;
309 }
310
get_cpu_dev(void)311 u32 get_cpu_dev(void)
312 {
313 return (read_idc() & DBGMCU_IDC_DEV_ID_MASK) >> DBGMCU_IDC_DEV_ID_SHIFT;
314 }
315
get_cpu_rev(void)316 u32 get_cpu_rev(void)
317 {
318 return (read_idc() & DBGMCU_IDC_REV_ID_MASK) >> DBGMCU_IDC_REV_ID_SHIFT;
319 }
320
get_otp(int index,int shift,int mask)321 static u32 get_otp(int index, int shift, int mask)
322 {
323 int ret;
324 struct udevice *dev;
325 u32 otp = 0;
326
327 ret = uclass_get_device_by_driver(UCLASS_MISC,
328 DM_DRIVER_GET(stm32mp_bsec),
329 &dev);
330
331 if (!ret)
332 ret = misc_read(dev, STM32_BSEC_SHADOW(index),
333 &otp, sizeof(otp));
334
335 return (otp >> shift) & mask;
336 }
337
338 /* Get Device Part Number (RPN) from OTP */
get_cpu_rpn(void)339 static u32 get_cpu_rpn(void)
340 {
341 return get_otp(BSEC_OTP_RPN, RPN_SHIFT, RPN_MASK);
342 }
343
get_cpu_type(void)344 u32 get_cpu_type(void)
345 {
346 return (get_cpu_dev() << 16) | get_cpu_rpn();
347 }
348
349 /* Get Package options from OTP */
get_cpu_package(void)350 u32 get_cpu_package(void)
351 {
352 return get_otp(BSEC_OTP_PKG, PKG_SHIFT, PKG_MASK);
353 }
354
get_soc_name(char name[SOC_NAME_SIZE])355 void get_soc_name(char name[SOC_NAME_SIZE])
356 {
357 char *cpu_s, *cpu_r, *pkg;
358
359 /* MPUs Part Numbers */
360 switch (get_cpu_type()) {
361 case CPU_STM32MP157Fxx:
362 cpu_s = "157F";
363 break;
364 case CPU_STM32MP157Dxx:
365 cpu_s = "157D";
366 break;
367 case CPU_STM32MP157Cxx:
368 cpu_s = "157C";
369 break;
370 case CPU_STM32MP157Axx:
371 cpu_s = "157A";
372 break;
373 case CPU_STM32MP153Fxx:
374 cpu_s = "153F";
375 break;
376 case CPU_STM32MP153Dxx:
377 cpu_s = "153D";
378 break;
379 case CPU_STM32MP153Cxx:
380 cpu_s = "153C";
381 break;
382 case CPU_STM32MP153Axx:
383 cpu_s = "153A";
384 break;
385 case CPU_STM32MP151Fxx:
386 cpu_s = "151F";
387 break;
388 case CPU_STM32MP151Dxx:
389 cpu_s = "151D";
390 break;
391 case CPU_STM32MP151Cxx:
392 cpu_s = "151C";
393 break;
394 case CPU_STM32MP151Axx:
395 cpu_s = "151A";
396 break;
397 default:
398 cpu_s = "????";
399 break;
400 }
401
402 /* Package */
403 switch (get_cpu_package()) {
404 case PKG_AA_LBGA448:
405 pkg = "AA";
406 break;
407 case PKG_AB_LBGA354:
408 pkg = "AB";
409 break;
410 case PKG_AC_TFBGA361:
411 pkg = "AC";
412 break;
413 case PKG_AD_TFBGA257:
414 pkg = "AD";
415 break;
416 default:
417 pkg = "??";
418 break;
419 }
420
421 /* REVISION */
422 switch (get_cpu_rev()) {
423 case CPU_REVA:
424 cpu_r = "A";
425 break;
426 case CPU_REVB:
427 cpu_r = "B";
428 break;
429 case CPU_REVZ:
430 cpu_r = "Z";
431 break;
432 default:
433 cpu_r = "?";
434 break;
435 }
436
437 snprintf(name, SOC_NAME_SIZE, "STM32MP%s%s Rev.%s", cpu_s, pkg, cpu_r);
438 }
439
440 #if defined(CONFIG_DISPLAY_CPUINFO)
print_cpuinfo(void)441 int print_cpuinfo(void)
442 {
443 char name[SOC_NAME_SIZE];
444
445 get_soc_name(name);
446 printf("CPU: %s\n", name);
447
448 return 0;
449 }
450 #endif /* CONFIG_DISPLAY_CPUINFO */
451
setup_boot_mode(void)452 static void setup_boot_mode(void)
453 {
454 const u32 serial_addr[] = {
455 STM32_USART1_BASE,
456 STM32_USART2_BASE,
457 STM32_USART3_BASE,
458 STM32_UART4_BASE,
459 STM32_UART5_BASE,
460 STM32_USART6_BASE,
461 STM32_UART7_BASE,
462 STM32_UART8_BASE
463 };
464 char cmd[60];
465 u32 boot_ctx = readl(TAMP_BOOT_CONTEXT);
466 u32 boot_mode =
467 (boot_ctx & TAMP_BOOT_MODE_MASK) >> TAMP_BOOT_MODE_SHIFT;
468 unsigned int instance = (boot_mode & TAMP_BOOT_INSTANCE_MASK) - 1;
469 u32 forced_mode = (boot_ctx & TAMP_BOOT_FORCED_MASK);
470 struct udevice *dev;
471
472 log_debug("%s: boot_ctx=0x%x => boot_mode=%x, instance=%d forced=%x\n",
473 __func__, boot_ctx, boot_mode, instance, forced_mode);
474 switch (boot_mode & TAMP_BOOT_DEVICE_MASK) {
475 case BOOT_SERIAL_UART:
476 if (instance > ARRAY_SIZE(serial_addr))
477 break;
478 /* serial : search associated node in devicetree */
479 sprintf(cmd, "serial@%x", serial_addr[instance]);
480 if (uclass_get_device_by_name(UCLASS_SERIAL, cmd, &dev)) {
481 /* restore console on error */
482 if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL))
483 gd->flags &= ~(GD_FLG_SILENT |
484 GD_FLG_DISABLE_CONSOLE);
485 printf("uart%d = %s not found in device tree!\n",
486 instance, cmd);
487 break;
488 }
489 sprintf(cmd, "%d", dev_seq(dev));
490 env_set("boot_device", "serial");
491 env_set("boot_instance", cmd);
492
493 /* restore console on uart when not used */
494 if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL) && gd->cur_serial_dev != dev) {
495 gd->flags &= ~(GD_FLG_SILENT |
496 GD_FLG_DISABLE_CONSOLE);
497 printf("serial boot with console enabled!\n");
498 }
499 break;
500 case BOOT_SERIAL_USB:
501 env_set("boot_device", "usb");
502 env_set("boot_instance", "0");
503 break;
504 case BOOT_FLASH_SD:
505 case BOOT_FLASH_EMMC:
506 sprintf(cmd, "%d", instance);
507 env_set("boot_device", "mmc");
508 env_set("boot_instance", cmd);
509 break;
510 case BOOT_FLASH_NAND:
511 env_set("boot_device", "nand");
512 env_set("boot_instance", "0");
513 break;
514 case BOOT_FLASH_SPINAND:
515 env_set("boot_device", "spi-nand");
516 env_set("boot_instance", "0");
517 break;
518 case BOOT_FLASH_NOR:
519 env_set("boot_device", "nor");
520 env_set("boot_instance", "0");
521 break;
522 default:
523 log_debug("unexpected boot mode = %x\n", boot_mode);
524 break;
525 }
526
527 switch (forced_mode) {
528 case BOOT_FASTBOOT:
529 printf("Enter fastboot!\n");
530 env_set("preboot", "env set preboot; fastboot 0");
531 break;
532 case BOOT_STM32PROG:
533 env_set("boot_device", "usb");
534 env_set("boot_instance", "0");
535 break;
536 case BOOT_UMS_MMC0:
537 case BOOT_UMS_MMC1:
538 case BOOT_UMS_MMC2:
539 printf("Enter UMS!\n");
540 instance = forced_mode - BOOT_UMS_MMC0;
541 sprintf(cmd, "env set preboot; ums 0 mmc %d", instance);
542 env_set("preboot", cmd);
543 break;
544 case BOOT_RECOVERY:
545 env_set("preboot", "env set preboot; run altbootcmd");
546 break;
547 case BOOT_NORMAL:
548 break;
549 default:
550 log_debug("unexpected forced boot mode = %x\n", forced_mode);
551 break;
552 }
553
554 /* clear TAMP for next reboot */
555 clrsetbits_le32(TAMP_BOOT_CONTEXT, TAMP_BOOT_FORCED_MASK, BOOT_NORMAL);
556 }
557
558 /*
559 * If there is no MAC address in the environment, then it will be initialized
560 * (silently) from the value in the OTP.
561 */
setup_mac_address(void)562 __weak int setup_mac_address(void)
563 {
564 #if defined(CONFIG_NET)
565 int ret;
566 int i;
567 u32 otp[2];
568 uchar enetaddr[6];
569 struct udevice *dev;
570
571 /* MAC already in environment */
572 if (eth_env_get_enetaddr("ethaddr", enetaddr))
573 return 0;
574
575 ret = uclass_get_device_by_driver(UCLASS_MISC,
576 DM_DRIVER_GET(stm32mp_bsec),
577 &dev);
578 if (ret)
579 return ret;
580
581 ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_MAC),
582 otp, sizeof(otp));
583 if (ret < 0)
584 return ret;
585
586 for (i = 0; i < 6; i++)
587 enetaddr[i] = ((uint8_t *)&otp)[i];
588
589 if (!is_valid_ethaddr(enetaddr)) {
590 log_err("invalid MAC address in OTP %pM\n", enetaddr);
591 return -EINVAL;
592 }
593 log_debug("OTP MAC address = %pM\n", enetaddr);
594 ret = eth_env_set_enetaddr("ethaddr", enetaddr);
595 if (ret)
596 log_err("Failed to set mac address %pM from OTP: %d\n", enetaddr, ret);
597 #endif
598
599 return 0;
600 }
601
setup_serial_number(void)602 static int setup_serial_number(void)
603 {
604 char serial_string[25];
605 u32 otp[3] = {0, 0, 0 };
606 struct udevice *dev;
607 int ret;
608
609 if (env_get("serial#"))
610 return 0;
611
612 ret = uclass_get_device_by_driver(UCLASS_MISC,
613 DM_DRIVER_GET(stm32mp_bsec),
614 &dev);
615 if (ret)
616 return ret;
617
618 ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_SERIAL),
619 otp, sizeof(otp));
620 if (ret < 0)
621 return ret;
622
623 sprintf(serial_string, "%08X%08X%08X", otp[0], otp[1], otp[2]);
624 env_set("serial#", serial_string);
625
626 return 0;
627 }
628
arch_misc_init(void)629 int arch_misc_init(void)
630 {
631 setup_boot_mode();
632 setup_mac_address();
633 setup_serial_number();
634
635 return 0;
636 }
637