1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2016 - 2018 Xilinx, Inc.
4 * Michal Simek <michal.simek@xilinx.com>
5 */
6
7 #include <common.h>
8 #include <init.h>
9 #include <asm/armv8/mmu.h>
10 #include <asm/cache.h>
11 #include <asm/global_data.h>
12 #include <asm/io.h>
13 #include <asm/arch/hardware.h>
14 #include <asm/arch/sys_proto.h>
15 #include <asm/cache.h>
16
17 DECLARE_GLOBAL_DATA_PTR;
18
19 #define VERSAL_MEM_MAP_USED 5
20
21 #define DRAM_BANKS CONFIG_NR_DRAM_BANKS
22
23 #if defined(CONFIG_DEFINE_TCM_OCM_MMAP)
24 #define TCM_MAP 1
25 #else
26 #define TCM_MAP 0
27 #endif
28
29 /* +1 is end of list which needs to be empty */
30 #define VERSAL_MEM_MAP_MAX (VERSAL_MEM_MAP_USED + DRAM_BANKS + TCM_MAP + 1)
31
32 static struct mm_region versal_mem_map[VERSAL_MEM_MAP_MAX] = {
33 {
34 .virt = 0x80000000UL,
35 .phys = 0x80000000UL,
36 .size = 0x70000000UL,
37 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
38 PTE_BLOCK_NON_SHARE |
39 PTE_BLOCK_PXN | PTE_BLOCK_UXN
40 }, {
41 .virt = 0xf0000000UL,
42 .phys = 0xf0000000UL,
43 .size = 0x0fe00000UL,
44 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
45 PTE_BLOCK_NON_SHARE |
46 PTE_BLOCK_PXN | PTE_BLOCK_UXN
47 }, {
48 .virt = 0x400000000UL,
49 .phys = 0x400000000UL,
50 .size = 0x200000000UL,
51 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
52 PTE_BLOCK_NON_SHARE |
53 PTE_BLOCK_PXN | PTE_BLOCK_UXN
54 }, {
55 .virt = 0x600000000UL,
56 .phys = 0x600000000UL,
57 .size = 0x800000000UL,
58 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
59 PTE_BLOCK_INNER_SHARE
60 }, {
61 .virt = 0xe00000000UL,
62 .phys = 0xe00000000UL,
63 .size = 0xf200000000UL,
64 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
65 PTE_BLOCK_NON_SHARE |
66 PTE_BLOCK_PXN | PTE_BLOCK_UXN
67 }
68 };
69
mem_map_fill(void)70 void mem_map_fill(void)
71 {
72 int banks = VERSAL_MEM_MAP_USED;
73
74 #if defined(CONFIG_DEFINE_TCM_OCM_MMAP)
75 versal_mem_map[banks].virt = 0xffe00000UL;
76 versal_mem_map[banks].phys = 0xffe00000UL;
77 versal_mem_map[banks].size = 0x00200000UL;
78 versal_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
79 PTE_BLOCK_INNER_SHARE;
80 banks = banks + 1;
81 #endif
82
83 for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
84 /* Zero size means no more DDR that's this is end */
85 if (!gd->bd->bi_dram[i].size)
86 break;
87
88 #if defined(CONFIG_VERSAL_NO_DDR)
89 if (gd->bd->bi_dram[i].start < 0x80000000UL ||
90 gd->bd->bi_dram[i].start > 0x100000000UL) {
91 printf("Ignore caches over %llx/%llx\n",
92 gd->bd->bi_dram[i].start,
93 gd->bd->bi_dram[i].size);
94 continue;
95 }
96 #endif
97 versal_mem_map[banks].virt = gd->bd->bi_dram[i].start;
98 versal_mem_map[banks].phys = gd->bd->bi_dram[i].start;
99 versal_mem_map[banks].size = gd->bd->bi_dram[i].size;
100 versal_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
101 PTE_BLOCK_INNER_SHARE;
102 banks = banks + 1;
103 }
104 }
105
106 struct mm_region *mem_map = versal_mem_map;
107
get_page_table_size(void)108 u64 get_page_table_size(void)
109 {
110 return 0x14000;
111 }
112
113 #if defined(CONFIG_SYS_MEM_RSVD_FOR_MMU)
arm_reserve_mmu(void)114 int arm_reserve_mmu(void)
115 {
116 tcm_init(TCM_LOCK);
117 gd->arch.tlb_size = PGTABLE_SIZE;
118 gd->arch.tlb_addr = VERSAL_TCM_BASE_ADDR;
119
120 return 0;
121 }
122 #endif
123