1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 *
4 * (C) Copyright 2000-2003
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 *
7 * (C) Copyright 2007, 2012 Freescale Semiconductor, Inc.
8 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
9 */
10
11 #include <common.h>
12 #include <cpu_func.h>
13 #include <init.h>
14 #include <watchdog.h>
15 #include <asm/immap.h>
16 #include <asm/io.h>
17
18 #if defined(CONFIG_CMD_NET)
19 #include <config.h>
20 #include <net.h>
21 #include <asm/fec.h>
22 #endif
23
24 /* The registers in fbcs_t struct can be 16-bit for CONFIG_M5235 or 32-bit wide otherwise. */
25 #ifdef CONFIG_M5235
26 #define out_be_fbcs_reg out_be16
27 #else
28 #define out_be_fbcs_reg out_be32
29 #endif
30
31 /*
32 * Breath some life into the CPU...
33 *
34 * Set up the memory map,
35 * initialize a bunch of registers,
36 * initialize the UPM's
37 */
cpu_init_f(void)38 void cpu_init_f(void)
39 {
40 gpio_t *gpio = (gpio_t *) MMAP_GPIO;
41 fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
42 wdog_t *wdog = (wdog_t *) MMAP_WDOG;
43 scm_t *scm = (scm_t *) MMAP_SCM;
44
45 /* watchdog is enabled by default - disable the watchdog */
46 #ifndef CONFIG_WATCHDOG
47 out_be16(&wdog->cr, 0);
48 #endif
49
50 out_be32(&scm->rambar, CONFIG_SYS_INIT_RAM_ADDR | SCM_RAMBAR_BDE);
51
52 /* Port configuration */
53 out_8(&gpio->par_cs, 0);
54
55 #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
56 out_be_fbcs_reg(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
57 out_be_fbcs_reg(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
58 out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
59 #endif
60
61 #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
62 setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS1);
63 out_be_fbcs_reg(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
64 out_be_fbcs_reg(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
65 out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
66 #endif
67
68 #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
69 setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS2);
70 out_be_fbcs_reg(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
71 out_be_fbcs_reg(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
72 out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
73 #endif
74
75 #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
76 setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS3);
77 out_be_fbcs_reg(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
78 out_be_fbcs_reg(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
79 out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
80 #endif
81
82 #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
83 setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS4);
84 out_be_fbcs_reg(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
85 out_be_fbcs_reg(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
86 out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
87 #endif
88
89 #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL))
90 setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS5);
91 out_be_fbcs_reg(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
92 out_be_fbcs_reg(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
93 out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
94 #endif
95
96 #if (defined(CONFIG_SYS_CS6_BASE) && defined(CONFIG_SYS_CS6_MASK) && defined(CONFIG_SYS_CS6_CTRL))
97 setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS6);
98 out_be_fbcs_reg(&fbcs->csar6, CONFIG_SYS_CS6_BASE);
99 out_be_fbcs_reg(&fbcs->cscr6, CONFIG_SYS_CS6_CTRL);
100 out_be32(&fbcs->csmr6, CONFIG_SYS_CS6_MASK);
101 #endif
102
103 #if (defined(CONFIG_SYS_CS7_BASE) && defined(CONFIG_SYS_CS7_MASK) && defined(CONFIG_SYS_CS7_CTRL))
104 setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS7);
105 out_be_fbcs_reg(&fbcs->csar7, CONFIG_SYS_CS7_BASE);
106 out_be_fbcs_reg(&fbcs->cscr7, CONFIG_SYS_CS7_CTRL);
107 out_be32(&fbcs->csmr7, CONFIG_SYS_CS7_MASK);
108 #endif
109
110 #ifdef CONFIG_SYS_I2C_FSL
111 CONFIG_SYS_I2C_PINMUX_REG &= CONFIG_SYS_I2C_PINMUX_CLR;
112 CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
113 #endif
114
115 icache_enable();
116 }
117
118 /*
119 * initialize higher level parts of CPU like timers
120 */
cpu_init_r(void)121 int cpu_init_r(void)
122 {
123 return (0);
124 }
125
uart_port_conf(int port)126 void uart_port_conf(int port)
127 {
128 gpio_t *gpio = (gpio_t *) MMAP_GPIO;
129
130 /* Setup Ports: */
131 switch (port) {
132 case 0:
133 clrbits_be16(&gpio->par_uart,
134 GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD);
135 setbits_be16(&gpio->par_uart,
136 GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD);
137 break;
138 case 1:
139 clrbits_be16(&gpio->par_uart,
140 GPIO_PAR_UART_U1RXD_MASK | GPIO_PAR_UART_U1TXD_MASK);
141 setbits_be16(&gpio->par_uart,
142 GPIO_PAR_UART_U1RXD_U1RXD | GPIO_PAR_UART_U1TXD_U1TXD);
143 break;
144 case 2:
145 #ifdef CONFIG_SYS_UART2_PRI_GPIO
146 clrbits_be16(&gpio->par_uart,
147 GPIO_PAR_UART_U2RXD | GPIO_PAR_UART_U2TXD);
148 setbits_be16(&gpio->par_uart,
149 GPIO_PAR_UART_U2RXD | GPIO_PAR_UART_U2TXD);
150 #elif defined(CONFIG_SYS_UART2_ALT1_GPIO)
151 clrbits_8(&gpio->par_feci2c,
152 GPIO_PAR_FECI2C_EMDC_MASK | GPIO_PAR_FECI2C_EMDIO_MASK);
153 setbits_8(&gpio->par_feci2c,
154 GPIO_PAR_FECI2C_EMDC_U2TXD | GPIO_PAR_FECI2C_EMDIO_U2RXD);
155 #endif
156 break;
157 }
158 }
159
160 #if defined(CONFIG_CMD_NET)
fecpin_setclear(fec_info_t * info,int setclear)161 int fecpin_setclear(fec_info_t *info, int setclear)
162 {
163 gpio_t *gpio = (gpio_t *) MMAP_GPIO;
164
165 if (setclear) {
166 setbits_8(&gpio->par_feci2c,
167 GPIO_PAR_FECI2C_EMDC_FECEMDC |
168 GPIO_PAR_FECI2C_EMDIO_FECEMDIO);
169 } else {
170 clrbits_8(&gpio->par_feci2c,
171 GPIO_PAR_FECI2C_EMDC_MASK |
172 GPIO_PAR_FECI2C_EMDIO_MASK);
173 }
174
175 return 0;
176 }
177 #endif
178