1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2004,2007-2011 Freescale Semiconductor, Inc.
4 * (C) Copyright 2002, 2003 Motorola Inc.
5 * Xianghua Xiao (X.Xiao@motorola.com)
6 *
7 * (C) Copyright 2000
8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9 */
10
11 #include <config.h>
12 #include <common.h>
13 #include <cpu_func.h>
14 #include <init.h>
15 #include <irq_func.h>
16 #include <log.h>
17 #include <time.h>
18 #include <vsprintf.h>
19 #include <watchdog.h>
20 #include <command.h>
21 #include <fsl_esdhc.h>
22 #include <asm/cache.h>
23 #include <asm/global_data.h>
24 #include <asm/io.h>
25 #include <asm/mmu.h>
26 #include <fsl_ifc.h>
27 #include <asm/fsl_law.h>
28 #include <asm/fsl_lbc.h>
29 #include <post.h>
30 #include <asm/processor.h>
31 #include <fsl_ddr_sdram.h>
32 #include <asm/ppc.h>
33 #include <linux/delay.h>
34
35 DECLARE_GLOBAL_DATA_PTR;
36
37 /*
38 * Default board reset function
39 */
40 static void
__board_reset(void)41 __board_reset(void)
42 {
43 /* Do nothing */
44 }
45 void board_reset(void) __attribute__((weak, alias("__board_reset")));
46
checkcpu(void)47 int checkcpu (void)
48 {
49 sys_info_t sysinfo;
50 uint pvr, svr;
51 uint ver;
52 uint major, minor;
53 struct cpu_type *cpu;
54 char buf1[32], buf2[32];
55 #if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET)
56 ccsr_gur_t __iomem *gur =
57 (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
58 #endif
59
60 /*
61 * Cornet platforms use ddr sync bit in RCW to indicate sync vs async
62 * mode. Previous platform use ddr ratio to do the same. This
63 * information is only for display here.
64 */
65 #ifdef CONFIG_FSL_CORENET
66 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
67 u32 ddr_sync = 0; /* only async mode is supported */
68 #else
69 u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC)
70 >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT;
71 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
72 #else /* CONFIG_FSL_CORENET */
73 #ifdef CONFIG_DDR_CLK_FREQ
74 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
75 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
76 #else
77 u32 ddr_ratio = 0;
78 #endif /* CONFIG_DDR_CLK_FREQ */
79 #endif /* CONFIG_FSL_CORENET */
80
81 unsigned int i, core, nr_cores = cpu_numcores();
82 u32 mask = cpu_mask();
83
84 #ifdef CONFIG_HETROGENOUS_CLUSTERS
85 unsigned int j, dsp_core, dsp_numcores = cpu_num_dspcores();
86 u32 dsp_mask = cpu_dsp_mask();
87 #endif
88
89 svr = get_svr();
90 major = SVR_MAJ(svr);
91 minor = SVR_MIN(svr);
92
93 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
94 if (SVR_SOC_VER(svr) == SVR_T4080) {
95 ccsr_rcpm_t *rcpm =
96 (void __iomem *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
97
98 setbits_be32(&gur->devdisr2, FSL_CORENET_DEVDISR2_DTSEC1_6 ||
99 FSL_CORENET_DEVDISR2_DTSEC1_9);
100 setbits_be32(&gur->devdisr3, FSL_CORENET_DEVDISR3_PCIE3);
101 setbits_be32(&gur->devdisr5, FSL_CORENET_DEVDISR5_DDR3);
102
103 /* It needs SW to disable core4~7 as HW design sake on T4080 */
104 for (i = 4; i < 8; i++)
105 cpu_disable(i);
106
107 /* request core4~7 into PH20 state, prior to entering PCL10
108 * state, all cores in cluster should be placed in PH20 state.
109 */
110 setbits_be32(&rcpm->pcph20setr, 0xf0);
111
112 /* put the 2nd cluster into PCL10 state */
113 setbits_be32(&rcpm->clpcl10setr, 1 << 1);
114 }
115 #endif
116
117 if (cpu_numcores() > 1) {
118 #ifndef CONFIG_MP
119 puts("Unicore software on multiprocessor system!!\n"
120 "To enable mutlticore build define CONFIG_MP\n");
121 #endif
122 volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
123 printf("CPU%d: ", pic->whoami);
124 } else {
125 puts("CPU: ");
126 }
127
128 cpu = gd->arch.cpu;
129
130 puts(cpu->name);
131 if (IS_E_PROCESSOR(svr))
132 puts("E");
133
134 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
135
136 pvr = get_pvr();
137 ver = PVR_VER(pvr);
138 major = PVR_MAJ(pvr);
139 minor = PVR_MIN(pvr);
140
141 printf("Core: ");
142 switch(ver) {
143 case PVR_VER_E500_V1:
144 case PVR_VER_E500_V2:
145 puts("e500");
146 break;
147 case PVR_VER_E500MC:
148 puts("e500mc");
149 break;
150 case PVR_VER_E5500:
151 puts("e5500");
152 break;
153 case PVR_VER_E6500:
154 puts("e6500");
155 break;
156 default:
157 puts("Unknown");
158 break;
159 }
160
161 printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
162
163 if (nr_cores > CONFIG_MAX_CPUS) {
164 panic("\nUnexpected number of cores: %d, max is %d\n",
165 nr_cores, CONFIG_MAX_CPUS);
166 }
167
168 get_sys_info(&sysinfo);
169
170 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
171 if (sysinfo.diff_sysclk == 1)
172 puts("Single Source Clock Configuration\n");
173 #endif
174
175 puts("Clock Configuration:");
176 for_each_cpu(i, core, nr_cores, mask) {
177 if (!(i & 3))
178 printf ("\n ");
179 printf("CPU%d:%-4s MHz, ", core,
180 strmhz(buf1, sysinfo.freq_processor[core]));
181 }
182
183 #ifdef CONFIG_HETROGENOUS_CLUSTERS
184 for_each_cpu(j, dsp_core, dsp_numcores, dsp_mask) {
185 if (!(j & 3))
186 printf("\n ");
187 printf("DSP CPU%d:%-4s MHz, ", j,
188 strmhz(buf1, sysinfo.freq_processor_dsp[dsp_core]));
189 }
190 #endif
191
192 printf("\n CCB:%-4s MHz,", strmhz(buf1, sysinfo.freq_systembus));
193 printf("\n");
194
195 #ifdef CONFIG_FSL_CORENET
196 if (ddr_sync == 1) {
197 printf(" DDR:%-4s MHz (%s MT/s data rate) "
198 "(Synchronous), ",
199 strmhz(buf1, sysinfo.freq_ddrbus/2),
200 strmhz(buf2, sysinfo.freq_ddrbus));
201 } else {
202 printf(" DDR:%-4s MHz (%s MT/s data rate) "
203 "(Asynchronous), ",
204 strmhz(buf1, sysinfo.freq_ddrbus/2),
205 strmhz(buf2, sysinfo.freq_ddrbus));
206 }
207 #else
208 switch (ddr_ratio) {
209 case 0x0:
210 printf(" DDR:%-4s MHz (%s MT/s data rate), ",
211 strmhz(buf1, sysinfo.freq_ddrbus/2),
212 strmhz(buf2, sysinfo.freq_ddrbus));
213 break;
214 case 0x7:
215 printf(" DDR:%-4s MHz (%s MT/s data rate) "
216 "(Synchronous), ",
217 strmhz(buf1, sysinfo.freq_ddrbus/2),
218 strmhz(buf2, sysinfo.freq_ddrbus));
219 break;
220 default:
221 printf(" DDR:%-4s MHz (%s MT/s data rate) "
222 "(Asynchronous), ",
223 strmhz(buf1, sysinfo.freq_ddrbus/2),
224 strmhz(buf2, sysinfo.freq_ddrbus));
225 break;
226 }
227 #endif
228
229 #if defined(CONFIG_FSL_LBC)
230 if (sysinfo.freq_localbus > LCRR_CLKDIV) {
231 printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus));
232 } else {
233 printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
234 sysinfo.freq_localbus);
235 }
236 #endif
237
238 #if defined(CONFIG_FSL_IFC)
239 printf("IFC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus));
240 #endif
241
242 #ifdef CONFIG_CPM2
243 printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freq_systembus));
244 #endif
245
246 #ifdef CONFIG_QE
247 printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freq_qe));
248 #endif
249
250 #if defined(CONFIG_SYS_CPRI)
251 printf(" ");
252 printf("CPRI:%-4s MHz", strmhz(buf1, sysinfo.freq_cpri));
253 #endif
254
255 #if defined(CONFIG_SYS_MAPLE)
256 printf("\n ");
257 printf("MAPLE:%-4s MHz, ", strmhz(buf1, sysinfo.freq_maple));
258 printf("MAPLE-ULB:%-4s MHz, ", strmhz(buf1, sysinfo.freq_maple_ulb));
259 printf("MAPLE-eTVPE:%-4s MHz\n",
260 strmhz(buf1, sysinfo.freq_maple_etvpe));
261 #endif
262
263 #ifdef CONFIG_SYS_DPAA_FMAN
264 for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) {
265 printf(" FMAN%d: %s MHz\n", i + 1,
266 strmhz(buf1, sysinfo.freq_fman[i]));
267 }
268 #endif
269
270 #ifdef CONFIG_SYS_DPAA_QBMAN
271 printf(" QMAN: %s MHz\n", strmhz(buf1, sysinfo.freq_qman));
272 #endif
273
274 #ifdef CONFIG_SYS_DPAA_PME
275 printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freq_pme));
276 #endif
277
278 puts("L1: D-cache 32 KiB enabled\n I-cache 32 KiB enabled\n");
279
280 #ifdef CONFIG_FSL_CORENET
281 /* Display the RCW, so that no one gets confused as to what RCW
282 * we're actually using for this boot.
283 */
284 puts("Reset Configuration Word (RCW):");
285 for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
286 u32 rcw = in_be32(&gur->rcwsr[i]);
287
288 if ((i % 4) == 0)
289 printf("\n %08x:", i * 4);
290 printf(" %08x", rcw);
291 }
292 puts("\n");
293 #endif
294
295 return 0;
296 }
297
298
299 /* ------------------------------------------------------------------------- */
300
do_reset(struct cmd_tbl * cmdtp,int flag,int argc,char * const argv[])301 int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
302 {
303 /* Everything after the first generation of PQ3 parts has RSTCR */
304 #if defined(CONFIG_ARCH_MPC8540) || defined(CONFIG_ARCH_MPC8541) || \
305 defined(CONFIG_ARCH_MPC8555) || defined(CONFIG_ARCH_MPC8560)
306 unsigned long val, msr;
307
308 /*
309 * Initiate hard reset in debug control register DBCR0
310 * Make sure MSR[DE] = 1. This only resets the core.
311 */
312 msr = mfmsr ();
313 msr |= MSR_DE;
314 mtmsr (msr);
315
316 val = mfspr(DBCR0);
317 val |= 0x70000000;
318 mtspr(DBCR0,val);
319 #else
320 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
321
322 /* Attempt board-specific reset */
323 board_reset();
324
325 /* Next try asserting HRESET_REQ */
326 out_be32(&gur->rstcr, 0x2);
327 udelay(100);
328 #endif
329
330 return 1;
331 }
332
333
334 /*
335 * Get timebase clock frequency
336 */
337 #ifndef CONFIG_SYS_FSL_TBCLK_DIV
338 #define CONFIG_SYS_FSL_TBCLK_DIV 8
339 #endif
get_tbclk(void)340 __weak unsigned long get_tbclk(void)
341 {
342 unsigned long tbclk_div = CONFIG_SYS_FSL_TBCLK_DIV;
343
344 return (gd->bus_clk + (tbclk_div >> 1)) / tbclk_div;
345 }
346
347
348 #if defined(CONFIG_WATCHDOG)
349 #define WATCHDOG_MASK (TCR_WP(63) | TCR_WRC(3) | TCR_WIE)
350 void
init_85xx_watchdog(void)351 init_85xx_watchdog(void)
352 {
353 mtspr(SPRN_TCR, (mfspr(SPRN_TCR) & ~WATCHDOG_MASK) |
354 TCR_WP(CONFIG_WATCHDOG_PRESC) | TCR_WRC(CONFIG_WATCHDOG_RC));
355 }
356
357 void
reset_85xx_watchdog(void)358 reset_85xx_watchdog(void)
359 {
360 /*
361 * Clear TSR(WIS) bit by writing 1
362 */
363 mtspr(SPRN_TSR, TSR_WIS);
364 }
365
366 void
watchdog_reset(void)367 watchdog_reset(void)
368 {
369 int re_enable = disable_interrupts();
370
371 reset_85xx_watchdog();
372 if (re_enable)
373 enable_interrupts();
374 }
375 #endif /* CONFIG_WATCHDOG */
376
377 /*
378 * Initializes on-chip MMC controllers.
379 * to override, implement board_mmc_init()
380 */
cpu_mmc_init(struct bd_info * bis)381 int cpu_mmc_init(struct bd_info *bis)
382 {
383 #ifdef CONFIG_FSL_ESDHC
384 return fsl_esdhc_mmc_init(bis);
385 #else
386 return 0;
387 #endif
388 }
389
390 /*
391 * Print out the state of various machine registers.
392 * Currently prints out LAWs, BR0/OR0 for LBC, CSPR/CSOR/Timing
393 * parameters for IFC and TLBs
394 */
print_reginfo(void)395 void print_reginfo(void)
396 {
397 print_tlbcam();
398 #ifdef CONFIG_FSL_LAW
399 print_laws();
400 #endif
401 #if defined(CONFIG_FSL_LBC)
402 print_lbc_regs();
403 #endif
404 #ifdef CONFIG_FSL_IFC
405 print_ifc_regs();
406 #endif
407
408 }
409
410 /* Common ddr init for non-corenet fsl 85xx platforms */
411 #ifndef CONFIG_FSL_CORENET
412 #if (defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)) && \
413 !defined(CONFIG_SYS_INIT_L2_ADDR)
dram_init(void)414 int dram_init(void)
415 {
416 #if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) || \
417 defined(CONFIG_ARCH_QEMU_E500)
418 gd->ram_size = fsl_ddr_sdram_size();
419 #else
420 gd->ram_size = (phys_size_t)CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
421 #endif
422
423 return 0;
424 }
425 #else /* CONFIG_SYS_RAMBOOT */
dram_init(void)426 int dram_init(void)
427 {
428 phys_size_t dram_size = 0;
429
430 #if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN)
431 {
432 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
433 unsigned int x = 10;
434 unsigned int i;
435
436 /*
437 * Work around to stabilize DDR DLL
438 */
439 out_be32(&gur->ddrdllcr, 0x81000000);
440 asm("sync;isync;msync");
441 udelay(200);
442 while (in_be32(&gur->ddrdllcr) != 0x81000100) {
443 setbits_be32(&gur->devdisr, 0x00010000);
444 for (i = 0; i < x; i++)
445 ;
446 clrbits_be32(&gur->devdisr, 0x00010000);
447 x++;
448 }
449 }
450 #endif
451
452 #if defined(CONFIG_SPD_EEPROM) || \
453 defined(CONFIG_DDR_SPD) || \
454 defined(CONFIG_SYS_DDR_RAW_TIMING)
455 dram_size = fsl_ddr_sdram();
456 #else
457 dram_size = fixed_sdram();
458 #endif
459 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
460 dram_size *= 0x100000;
461
462 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
463 /*
464 * Initialize and enable DDR ECC.
465 */
466 ddr_enable_ecc(dram_size);
467 #endif
468
469 #if defined(CONFIG_FSL_LBC)
470 /* Some boards also have sdram on the lbc */
471 lbc_sdram_init();
472 #endif
473
474 debug("DDR: ");
475 gd->ram_size = dram_size;
476
477 return 0;
478 }
479 #endif /* CONFIG_SYS_RAMBOOT */
480 #endif
481
482 #if CONFIG_POST & CONFIG_SYS_POST_MEMORY
483
484 /* Board-specific functions defined in each board's ddr.c */
485 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
486 unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl);
487 void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn,
488 phys_addr_t *rpn);
489 unsigned int
490 setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg);
491
492 void clear_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg);
493
dump_spd_ddr_reg(void)494 static void dump_spd_ddr_reg(void)
495 {
496 int i, j, k, m;
497 u8 *p_8;
498 u32 *p_32;
499 struct ccsr_ddr __iomem *ddr[CONFIG_SYS_NUM_DDR_CTLRS];
500 generic_spd_eeprom_t
501 spd[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR];
502
503 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++)
504 fsl_ddr_get_spd(spd[i], i, CONFIG_DIMM_SLOTS_PER_CTLR);
505
506 puts("SPD data of all dimms (zero value is omitted)...\n");
507 puts("Byte (hex) ");
508 k = 1;
509 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
510 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++)
511 printf("Dimm%d ", k++);
512 }
513 puts("\n");
514 for (k = 0; k < sizeof(generic_spd_eeprom_t); k++) {
515 m = 0;
516 printf("%3d (0x%02x) ", k, k);
517 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
518 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
519 p_8 = (u8 *) &spd[i][j];
520 if (p_8[k]) {
521 printf("0x%02x ", p_8[k]);
522 m++;
523 } else
524 puts(" ");
525 }
526 }
527 if (m)
528 puts("\n");
529 else
530 puts("\r");
531 }
532
533 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
534 switch (i) {
535 case 0:
536 ddr[i] = (void *)CONFIG_SYS_FSL_DDR_ADDR;
537 break;
538 #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
539 case 1:
540 ddr[i] = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
541 break;
542 #endif
543 #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
544 case 2:
545 ddr[i] = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
546 break;
547 #endif
548 #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
549 case 3:
550 ddr[i] = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
551 break;
552 #endif
553 default:
554 printf("%s unexpected controller number = %u\n",
555 __func__, i);
556 return;
557 }
558 }
559 printf("DDR registers dump for all controllers "
560 "(zero value is omitted)...\n");
561 puts("Offset (hex) ");
562 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++)
563 printf(" Base + 0x%04x", (u32)ddr[i] & 0xFFFF);
564 puts("\n");
565 for (k = 0; k < sizeof(struct ccsr_ddr)/4; k++) {
566 m = 0;
567 printf("%6d (0x%04x)", k * 4, k * 4);
568 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
569 p_32 = (u32 *) ddr[i];
570 if (p_32[k]) {
571 printf(" 0x%08x", p_32[k]);
572 m++;
573 } else
574 puts(" ");
575 }
576 if (m)
577 puts("\n");
578 else
579 puts("\r");
580 }
581 puts("\n");
582 }
583
584 /* invalid the TLBs for DDR and setup new ones to cover p_addr */
reset_tlb(phys_addr_t p_addr,u32 size,phys_addr_t * phys_offset)585 static int reset_tlb(phys_addr_t p_addr, u32 size, phys_addr_t *phys_offset)
586 {
587 u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE;
588 unsigned long epn;
589 u32 tsize, valid, ptr;
590 int ddr_esel;
591
592 clear_ddr_tlbs_phys(p_addr, size>>20);
593
594 /* Setup new tlb to cover the physical address */
595 setup_ddr_tlbs_phys(p_addr, size>>20);
596
597 ptr = vstart;
598 ddr_esel = find_tlb_idx((void *)ptr, 1);
599 if (ddr_esel != -1) {
600 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, phys_offset);
601 } else {
602 printf("TLB error in function %s\n", __func__);
603 return -1;
604 }
605
606 return 0;
607 }
608
609 /*
610 * slide the testing window up to test another area
611 * for 32_bit system, the maximum testable memory is limited to
612 * CONFIG_MAX_MEM_MAPPED
613 */
arch_memory_test_advance(u32 * vstart,u32 * size,phys_addr_t * phys_offset)614 int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
615 {
616 phys_addr_t test_cap, p_addr;
617 phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED);
618
619 #if !defined(CONFIG_PHYS_64BIT) || \
620 !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \
621 (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
622 test_cap = p_size;
623 #else
624 test_cap = gd->ram_size;
625 #endif
626 p_addr = (*vstart) + (*size) + (*phys_offset);
627 if (p_addr < test_cap - 1) {
628 p_size = min(test_cap - p_addr, CONFIG_MAX_MEM_MAPPED);
629 if (reset_tlb(p_addr, p_size, phys_offset) == -1)
630 return -1;
631 *vstart = CONFIG_SYS_DDR_SDRAM_BASE;
632 *size = (u32) p_size;
633 printf("Testing 0x%08llx - 0x%08llx\n",
634 (u64)(*vstart) + (*phys_offset),
635 (u64)(*vstart) + (*phys_offset) + (*size) - 1);
636 } else
637 return 1;
638
639 return 0;
640 }
641
642 /* initialization for testing area */
arch_memory_test_prepare(u32 * vstart,u32 * size,phys_addr_t * phys_offset)643 int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
644 {
645 phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED);
646
647 *vstart = CONFIG_SYS_DDR_SDRAM_BASE;
648 *size = (u32) p_size; /* CONFIG_MAX_MEM_MAPPED < 4G */
649 *phys_offset = 0;
650
651 #if !defined(CONFIG_PHYS_64BIT) || \
652 !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \
653 (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
654 if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
655 puts("Cannot test more than ");
656 print_size(CONFIG_MAX_MEM_MAPPED,
657 " without proper 36BIT support.\n");
658 }
659 #endif
660 printf("Testing 0x%08llx - 0x%08llx\n",
661 (u64)(*vstart) + (*phys_offset),
662 (u64)(*vstart) + (*phys_offset) + (*size) - 1);
663
664 return 0;
665 }
666
667 /* invalid TLBs for DDR and remap as normal after testing */
arch_memory_test_cleanup(u32 * vstart,u32 * size,phys_addr_t * phys_offset)668 int arch_memory_test_cleanup(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
669 {
670 unsigned long epn;
671 u32 tsize, valid, ptr;
672 phys_addr_t rpn = 0;
673 int ddr_esel;
674
675 /* disable the TLBs for this testing */
676 ptr = *vstart;
677
678 while (ptr < (*vstart) + (*size)) {
679 ddr_esel = find_tlb_idx((void *)ptr, 1);
680 if (ddr_esel != -1) {
681 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn);
682 disable_tlb(ddr_esel);
683 }
684 ptr += TSIZE_TO_BYTES(tsize);
685 }
686
687 puts("Remap DDR ");
688 setup_ddr_tlbs(gd->ram_size>>20);
689 puts("\n");
690
691 return 0;
692 }
693
arch_memory_failure_handle(void)694 void arch_memory_failure_handle(void)
695 {
696 dump_spd_ddr_reg();
697 }
698 #endif
699